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klte: Use fragmented NFC support from -common 

Change-Id: I78837850d275a3b505742ae4e71d3afb9c082f10
This commit is contained in:
Kevin F. Haggerty 2018-01-01 17:56:42 -07:00
parent ccb8f00e5c
commit c4b5b08b7b
5 changed files with 4 additions and 855 deletions
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5
BoardConfig.mk
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@ -1,5 +1,5 @@
# Copyright (C) 2014-2016 The CyanogenMod Project
# Copyright (C) 2017 The LineageOS Project
# Copyright (C) 2017-2018 The LineageOS Project
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -29,8 +29,7 @@ TARGET_INIT_VENDOR_LIB := libinit_msm8974
TARGET_LIBINIT_MSM8974_DEFINES_FILE := device/samsung/klte/init/init_klte.cpp
# NFC
BOARD_NFC_CHIPSET := pn547
BOARD_NFC_HAL_SUFFIX := msm8974
include $(COMMON_PATH)/nfc/pn547/board.mk
# Radio/RIL
include $(COMMON_PATH)/radio/single/board.mk

343
configs/libnfc-brcm.conf
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@ -1,343 +0,0 @@
## this file is used by Broadcom's Hardware Abstraction Layer at external/libnfc-nci/halimpl/
###############################################################################
# Application options
APPL_TRACE_LEVEL=0xFF
PROTOCOL_TRACE_LEVEL=0xFFFFFFFF
###############################################################################
# performance measurement
# Change this setting to control how often USERIAL log the performance (throughput)
# data on read/write/poll
# defailt is to log performance dara for every 100 read or write
#REPORT_PERFORMANCE_MEASURE=100
###############################################################################
# File used for NFA storage
NFA_STORAGE="/data/nfc"
###############################################################################
# Snooze Mode Settings
#
# By default snooze mode is enabled. Set SNOOZE_MODE_CFG byte[0] to 0
# to disable.
#
# If SNOOZE_MODE_CFG is not provided, the default settings are used:
# They are as follows:
# 8 Sleep Mode (0=Disabled 1=UART 8=SPI/I2C)
# 0 Idle Threshold Host
# 0 Idle Threshold HC
# 0 NFC Wake active mode (0=ActiveLow 1=ActiveHigh)
# 1 Host Wake active mode (0=ActiveLow 1=ActiveHigh)
#
#SNOOZE_MODE_CFG={08:00:00:00:01}
###############################################################################
# Insert a delay in milliseconds after NFC_WAKE and before write to NFCC
NFC_WAKE_DELAY=20
###############################################################################
# Various Delay settings (in ms) used in USERIAL
# POWER_ON_DELAY
# Delay after turning on chip, before writing to transport (default 300)
# PRE_POWER_OFF_DELAY
# Delay after deasserting NFC-Wake before turn off chip (default 0)
# POST_POWER_OFF_DELAY
# Delay after turning off chip, before USERIAL_close returns (default 0)
#
#POWER_ON_DELAY=300
#PRE_POWER_OFF_DELAY=0
#POST_POWER_OFF_DELAY=0
###############################################################################
# LPTD mode configuration
# byte[0] is the length of the remaining bytes in this value
# if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled).
# byte[1] is the param id it should be set to B9.
# byte[2] is the length of the LPTD parameters
# byte[3] indicates if LPTD is enabled
# if set to 0, LPTD will be disabled (parameters will still be sent).
# byte[4-n] are the LPTD parameters.
# By default, LPTD is enabled and default settings are used.
# See nfc_hal_dm_cfg.c for defaults
LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00}
###############################################################################
# Startup Configuration (100 bytes maximum)
#
# For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is
# for UICC1. The values are defined as:
# 0 : UICCx only supports ISO_DEP in low power mode.
# 2 : UICCx only supports Mifare in low power mode.
# 3 : UICCx supports both ISO_DEP and Mifare in low power mode.
#
# AA BB
NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:80:01:01}
###############################################################################
# Startup Vendor Specific Configuration (100 bytes maximum);
# byte[0] TLV total len = 0x5
# byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f
# byte[2] NCI_MSG_FRAME_LOG = 0x9
# byte[3] 2
# byte[4] 0=turn off RF frame logging; 1=turn on
# byte[5] 0=turn off SWP frame logging; 1=turn on
# NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01}
###############################################################################
# Antenna Configuration - This data is used when setting 0xC8 config item
# at startup (before discovery is started). If not used, no value is sent.
#
# The settings for this value are documented here:
# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
# Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
# This document is maintained by Paul Forshaw.
#
# The values marked as ?? should be tweaked per antenna or customer/app:
# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
# array[0] = 0x20 is length of the payload from array[1] to the end
# array[1] = 0xC8 is PREINIT_DSP_CFG
#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
###############################################################################
# Configure crystal frequency when internal LPO can't detect the frequency.
#XTAL_FREQUENCY=0
###############################################################################
# Configure the default Destination Gate used by HCI (the default is 4, which
# is the ETSI loopback gate.
NFA_HCI_DEFAULT_DEST_GATE=0xF0
###############################################################################
# Configure the single default SE to use. The default is to use the first
# SE that is detected by the stack. This value might be used when the phone
# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
# one of them (e.g. 0xF4).
#ACTIVE_SE=0xF3
###############################################################################
# Configure the NFC Extras to open and use a static pipe. If the value is
# not set or set to 0, then the default is use a dynamic pipe based on a
# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value
# for each UICC (where F3="UICC0" and F4="UICC1")
#NFA_HCI_STATIC_PIPE_ID_F3=0x70
#NFA_HCI_STATIC_PIPE_ID_01=0x19
NFA_HCI_STATIC_PIPE_ID_C0=0x19
###############################################################################
# When disconnecting from Oberthur secure element, perform a warm-reset of
# the secure element to deselect the applet.
# The default hex value of the command is 0x3. If this variable is undefined,
# then this feature is not used.
OBERTHUR_WARM_RESET_COMMAND=0x03
###############################################################################
# Force UICC to only listen to the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
UICC_LISTEN_TECH_MASK=0xC7
###############################################################################
# Allow UICC to be powered off if there is no traffic.
# Timeout is in ms. If set to 0, then UICC will not be powered off.
#UICC_IDLE_TIMEOUT=30000
UICC_IDLE_TIMEOUT=0
###############################################################################
# AID for Empty Select command
# If specified, this AID will be substituted when an Empty SELECT command is
# detected. The first byte is the length of the AID. Maximum length is 16.
AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
###############################################################################
# Maximum Number of Credits to be allowed by the NFCC
# This value overrides what the NFCC specifices allowing the host to have
# the control to work-around transport limitations. If this value does
# not exist or is set to 0, the NFCC will provide the number of credits.
MAX_RF_DATA_CREDITS=1
###############################################################################
# This setting allows you to disable registering the T4t Virtual SE that causes
# the NFCC to send PPSE requests to the DH.
# The default setting is enabled (i.e. T4t Virtual SE is registered).
#REGISTER_VIRTUAL_SE=1
###############################################################################
# When screen is turned off, specify the desired power state of the controller.
# 0: power-off-sleep state; DEFAULT
# 1: full-power state
# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
SCREEN_OFF_POWER_STATE=1
###############################################################################
# Firmware patch file
# If the value is not set then patch download is disabled.
FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd"
###############################################################################
# Firmware pre-patch file (sent before the above patch file)
# If the value is not set then pre-patch is not used.
FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd"
###############################################################################
# Firmware patch format
# 1 = HCD
# 2 = NCD (default)
#NFA_CONFIG_FORMAT=2
###############################################################################
# SPD Debug mode
# If set to 1, any failure of downloading a patch will trigger a hard-stop
#SPD_DEBUG=0
###############################################################################
# SPD Max Retry Count
# The number of attempts to download a patch before giving up (defualt is 3).
# Note, this resets after a power-cycle.
#SPD_MAX_RETRY_COUNT=3
###############################################################################
# transport driver
#
# TRANSPORT_DRIVER=<driver>
#
# where <driver> can be, for example:
# "/dev/ttyS" (UART)
# "/dev/bcmi2cnfc" (I2C)
# "hwtun" (HW Tunnel)
# "/dev/bcmspinfc" (SPI)
# "/dev/btusb0" (BT USB)
TRANSPORT_DRIVER="/dev/bcm2079x"
###############################################################################
# power control driver
# Specify a kernel driver that support ioctl commands to control NFC_EN and
# NFC_WAKE gpio signals.
#
# POWER_CONTRL_DRIVER=<driver>
# where <driver> can be, for example:
# "/dev/nfcpower"
# "/dev/bcmi2cnfc" (I2C)
# "/dev/bcmspinfc" (SPI)
# i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal
POWER_CONTROL_DRIVER="/dev/bcm2079x"
###############################################################################
# I2C transport driver options
#
BCMI2CNFC_ADDRESS=0
###############################################################################
# I2C transport driver try to read multiple packets in read() if data is available
# remove the comment below to enable this feature
#READ_MULTIPLE_PACKETS=1
###############################################################################
# SPI transport driver options
#SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00}
###############################################################################
# UART transport driver options
#
# PORT=1,2,3,...
# BAUD=115200, 19200, 9600, 4800,
# DATABITS=8, 7, 6, 5
# PARITY="even" | "odd" | "none"
# STOPBITS="0" | "1" | "1.5" | "2"
#UART_PORT=2
#UART_BAUD=115200
#UART_DATABITS=8
#UART_PARITY="none"
#UART_STOPBITS="1"
###############################################################################
# Insert a delay in microseconds per byte after a write to NFCC.
# after writing a block of data to the NFCC, delay this an amopunt of time before
# writing next block of data. the delay is calculated as below
# NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds
# e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write
NFC_WRITE_DELAY=20
###############################################################################
# Maximum Number of Credits to be allowed by the NFCC
# This value overrides what the NFCC specifices allowing the host to have
# the control to work-around transport limitations. If this value does
# not exist or is set to 0, the NFCC will provide the number of credits.
MAX_RF_DATA_CREDITS=1
###############################################################################
# Antenna Configuration - This data is used when setting 0xC8 config item
# at startup (before discovery is started). If not used, no value is sent.
#
# The settings for this value are documented here:
# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
# Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
# This document is maintained by Paul Forshaw.
#
# The values marked as ?? should be tweaked per antenna or customer/app:
# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
# array[0] = 0x20 is length of the payload from array[1] to the end
# array[1] = 0xC8 is PREINIT_DSP_CFG
#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
###############################################################################
# Force tag polling for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
# NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
# NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
POLLING_TECH_MASK=0x6F
###############################################################################
# Force P2P to only listen for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
P2P_LISTEN_TECH_MASK=0xC4
PRESERVE_STORAGE=0x01
###############################################################################
# Maximum EE supported number
# NXP PN547C2 0x02
# NXP PN65T 0x03
NFA_MAX_EE_SUPPORTED=0x02
###############################################################################
# NCI Hal Module name
NCI_HAL_MODULE="nfc_nci"
###############################################################################
# Vendor Specific Proprietary Protocol & Discovery Configuration
# Set to 0xFF if unsupported
# byte[0] NCI_PROTOCOL_18092_ACTIVE
# byte[1] NCI_PROTOCOL_B_PRIME
# byte[2] NCI_PROTOCOL_DUAL
# byte[3] NCI_PROTOCOL_15693
# byte[4] NCI_PROTOCOL_KOVIO
# byte[5] NCI_PROTOCOL_MIFARE
# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:77:FF:FF}
###############################################################################
# Enable/Disable NFC-F HCE
# Disable 0x00
# Enable non-zero value
ENABLE_NFCF_HCE=0x00

477
configs/libnfc-nxp.conf
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@ -1,477 +0,0 @@
## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
###############################################################################
# Application options
# Logging Levels
# NXPLOG_DEFAULT_LOGLEVEL 0x01
# ANDROID_LOG_DEBUG 0x03
# ANDROID_LOG_WARN 0x02
# ANDROID_LOG_ERROR 0x01
# ANDROID_LOG_SILENT 0x00
#
NXPLOG_EXTNS_LOGLEVEL=0x02
NXPLOG_NCIHAL_LOGLEVEL=0x02
NXPLOG_NCIX_LOGLEVEL=0x02
NXPLOG_NCIR_LOGLEVEL=0x02
NXPLOG_FWDNLD_LOGLEVEL=0x02
NXPLOG_TML_LOGLEVEL=0x02
###############################################################################
# Extension for Mifare reader enable
# 0x00 - Disabled
# 0x01 - Enabled
MIFARE_READER_ENABLE=0x01
###############################################################################
# File location for Firmware
#FW_STORAGE="/vendor/firmware/libpn547_fw.so"
###############################################################################
# Nfc Device Node name
NXP_NFC_DEV_NODE="/dev/pn547"
###############################################################################
# File name for Firmware
NXP_FW_NAME="libpn547_fw.so"
###############################################################################
# System clock source selection configuration
# CLK_SRC_XTAL - 0x01
# CLK_SRC_PLL - 0x02
NXP_SYS_CLK_SRC_SEL=0x02
###############################################################################
# System clock frequency selection configuration for PLL
# CLK_FREQ_13MHZ - 0x01
# CLK_FREQ_19_2MHZ - 0x02
# CLK_FREQ_24MHZ - 0x03
# CLK_FREQ_26MHZ - 0x04
# CLK_FREQ_38_4MHZ - 0x05
# CLK_FREQ_52MHZ - 0x06
NXP_SYS_CLK_FREQ_SEL=0x02
###############################################################################
# The timeout value to be used for clock request acknowledgment
# min value = 0x01 to max = 0x0A
NXP_SYS_CLOCK_TO_CFG=0x0A
###############################################################################
# NXP proprietary settings
NXP_ACT_PROP_EXTN={2F, 02, 00}
###############################################################################
# NFC forum profile settings
NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
###############################################################################
# Standby enable settings
# 0x00 - Disabled
# 0x01 - Enabled
NXP_CORE_STANDBY={2F, 00, 01, 01}
###############################################################################
# NXP RF ALM (NO BOOSTER) configuration settings for FW VERSION = 08.01.1F
###############################################################################
# A0, 0D, 03, 00, 40, 02 RF_CLIF_BOOT CLIF_ANA_NFCLD_REG
# A0, 0D, 03, 04, 43, 20 RF_CLIF_CFG_INITIATOR CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 03, 04, FF, 05 RF_CLIF_CFG_INITIATOR SMU_PMU_REG (0x40024010)
# A0, 0D, 06, 06, 44, A3, 90, 03, 00 RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
# A0, 0D, 06, 06, 30, CF, 00, 08, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 06, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 04, 06, 03, 00, 6E RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 03, 06, 48, 1F RF_CLIF_CFG_TARGET CLIF_ANA_CLK_MAN_REG
# A0, 0D, 03, 06, 43, A0 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 06, 42, 00, 00, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 06, 41, 80, 00, 00, 00 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 06, 37, 18 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 06, FF, 05, 00, 00, 00 RF_CLIF_CFG_TARGET SMU_PMU_REG (0x40024010)
# A0, 0D, 06, 08, 44, 00, 00, 00, 00 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_RX_REG
# A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 20, 16, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 20, 15, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 22, 44, 22, 00, 02, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
# A0, 0D, 06, 22, 2D, 50, 44, 0C, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 32, 03, 40, 3D RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 0D, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 32, 14, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 32, 4A, 30, 07, 01, 1F RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 34, 2D, 24, 77, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 34, 34, 00, 00, E4, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 34, 44, 21, 00, 02, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 06, 35, 44, 21, 00, 02, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 06, 38, 4A, 53, 07, 01, 1B RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 38, 16, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 38, 15, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3C, 4A, 52, 07, 01, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 3C, 16, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 3C, 15, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 40, 0D, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 40, 14, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 40, 16, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 40, 15, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 46, 44, 21, 00, 02, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 46, 2D, 05, 47, 0E, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 44, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 44, 16, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 44, 15, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 4A, 44, 22, 00, 02, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4A, 2D, 05, 37, 0C, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 48, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 48, 16, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 48, 15, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 4E, 44, 22, 00, 02, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4E, 2D, 05, 37, 0C, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 4C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 4C, 16, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 4C, 15, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 52, 44, 22, 00, 02, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 52, 2D, 05, 25, 0C, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 50, 4A, 11, 0F, 01, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 50, 16, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 50, 15, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 56, 44, 22, 00, 02, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 5C, 2D, 05, 69, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 5C, 44, 21, 00, 02, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 54, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 54, 16, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 54, 15, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 5A, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 5A, 16, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 5A, 15, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 98, 2F, AF, 05, 80, 0F RF_CLIF_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 9A, 42, 00, 00, FF, FF RF_CLIF_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 30, 44, A3, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 74, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 74, 30, DF, 00, 07, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 78, 2F, 1F, 06, 80, 01 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 78, 30, 3F, 00, 04, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 78, 44, A2, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 03, 78, 47, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_AGC_REG
# A0, 0D, 06, 7C, 2F, AF, 05, 80, 0F RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 7C, 30, CF, 00, 07, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 7D, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 80, 2F, AF, 05, 80, 90 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 80, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 84, 2F, AF, 05, 80, 92 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 84, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 88, 2F, 7F, 04, 80, 10 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 88, 30, 5F, 00, 16, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 88, 47, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_AGC_REG
# A0, 0D, 06, 88, 44, A1, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 03, 0C, 48, 1F RF_CLIF_CFG_T_PASSIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 03, 10, 43, 20 RF_CLIF_CFG_T_ACTIVE CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 6A, 16, 00 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 6A, 15, 01 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 8C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 8C, 16, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 8C, 15, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 92, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 92, 16, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 92, 15, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 0A, 30, CF, 00, 08, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 0A, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 03, 0A, 48, 10 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 06, 0A, 44, A3, 90, 03, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_1={
20, 02, F3, 20,
A0, 0D, 03, 00, 40, 03,
A0, 0D, 03, 04, 43, 20,
A0, 0D, 03, 04, FF, 05,
A0, 0D, 06, 06, 44, A3, 90, 03, 00,
A0, 0D, 06, 06, 30, CF, 00, 08, 00,
A0, 0D, 06, 06, 2F, 8F, 05, 80, 0C,
A0, 0D, 04, 06, 03, 00, 71,
A0, 0D, 03, 06, 48, 18,
A0, 0D, 03, 06, 43, A0,
A0, 0D, 06, 06, 42, 00, 00, F1, F6,
A0, 0D, 06, 06, 41, 80, 00, 00, 00,
A0, 0D, 03, 06, 37, 18,
A0, 0D, 03, 06, 16, 00,
A0, 0D, 03, 06, 15, 00,
A0, 0D, 06, 06, FF, 05, 00, 00, 00,
A0, 0D, 06, 08, 44, 00, 00, 00, 00,
A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
A0, 0D, 06, 20, 42, 88, 10, FF, FF,
A0, 0D, 03, 20, 16, 00,
A0, 0D, 03, 20, 15, 00,
A0, 0D, 06, 22, 44, 22, 00, 02, 00,
A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
A0, 0D, 04, 32, 03, 40, 3D,
A0, 0D, 06, 32, 42, F8, 10, FF, FF,
A0, 0D, 03, 32, 16, 00,
A0, 0D, 03, 32, 15, 01,
A0, 0D, 03, 32, 0D, 22,
A0, 0D, 03, 32, 14, 22,
A0, 0D, 06, 32, 4A, 30, 07, 01, 1F,
A0, 0D, 06, 34, 2D, 24, 77, 0C, 00,
A0, 0D, 06, 34, 34, 00, 00, E4, 03,
A0, 0D, 06, 34, 44, 21, 00, 02, 00
}
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_2={
20, 02, F4, 1F,
A0, 0D, 06, 35, 44, 21, 00, 02, 00,
A0, 0D, 06, 38, 4A, 53, 07, 01, 1B,
A0, 0D, 06, 38, 42, 68, 10, FF, FF,
A0, 0D, 03, 38, 16, 00,
A0, 0D, 03, 38, 15, 00,
A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 3C, 4A, 52, 07, 01, 1B,
A0, 0D, 06, 3C, 42, 68, 10, FF, FF,
A0, 0D, 03, 3C, 16, 00,
A0, 0D, 03, 3C, 15, 00,
A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 40, 42, F0, 10, FF, FF,
A0, 0D, 03, 40, 0D, 02,
A0, 0D, 03, 40, 14, 02,
A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
A0, 0D, 03, 40, 16, 00,
A0, 0D, 03, 40, 15, 00,
A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 46, 44, 21, 00, 02, 00,
A0, 0D, 06, 46, 2D, 05, 47, 0E, 00,
A0, 0D, 06, 44, 4A, 33, 07, 01, 07,
A0, 0D, 06, 44, 42, 88, 10, FF, FF,
A0, 0D, 03, 44, 16, 00,
A0, 0D, 03, 44, 15, 00,
A0, 0D, 06, 4A, 44, 22, 00, 02, 00,
A0, 0D, 06, 4A, 2D, 05, 37, 0C, 00,
A0, 0D, 06, 48, 4A, 33, 07, 01, 07,
A0, 0D, 06, 48, 42, 88, 10, FF, FF,
A0, 0D, 03, 48, 16, 00,
A0, 0D, 03, 48, 15, 00,
A0, 0D, 06, 4E, 44, 22, 00, 02, 00
}
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_3={
20, 02, F7, 1E,
A0, 0D, 06, 4E, 2D, 05, 37, 0C, 00,
A0, 0D, 06, 4C, 4A, 33, 07, 01, 07,
A0, 0D, 06, 4C, 42, 88, 10, FF, FF,
A0, 0D, 03, 4C, 16, 00,
A0, 0D, 03, 4C, 15, 00,
A0, 0D, 06, 52, 44, 22, 00, 02, 00,
A0, 0D, 06, 52, 2D, 05, 25, 0C, 00,
A0, 0D, 06, 50, 42, 90, 10, FF, FF,
A0, 0D, 06, 50, 4A, 11, 0F, 01, 07,
A0, 0D, 03, 50, 16, 00,
A0, 0D, 03, 50, 15, 00,
A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
A0, 0D, 06, 56, 44, 22, 00, 02, 00,
A0, 0D, 06, 5C, 2D, 05, 69, 0C, 00,
A0, 0D, 06, 5C, 44, 21, 00, 02, 00,
A0, 0D, 06, 54, 42, 88, 10, FF, FF,
A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
A0, 0D, 03, 54, 16, 00,
A0, 0D, 03, 54, 15, 00,
A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
A0, 0D, 03, 5A, 16, 00,
A0, 0D, 03, 5A, 15, 00,
A0, 0D, 06, 98, 2F, AF, 05, 80, 0F,
A0, 0D, 06, 9A, 42, 00, 00, F1, F6,
A0, 0D, 06, 30, 44, A3, 90, 03, 00,
A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
A0, 0D, 06, 70, 2F, 8F, 05, 80, 12
}
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_4={
20, 02, F7, 1E,
A0, 0D, 06, 70, 30, CF, 00, 08, 00,
A0, 0D, 06, 74, 2F, 8F, 05, 80, 12,
A0, 0D, 06, 74, 30, DF, 00, 07, 00,
A0, 0D, 06, 78, 2F, 1F, 06, 80, 01,
A0, 0D, 06, 78, 30, 3F, 00, 04, 00,
A0, 0D, 06, 78, 44, A2, 90, 03, 00,
A0, 0D, 03, 78, 47, 00,
A0, 0D, 06, 7C, 2F, AF, 05, 80, 0F,
A0, 0D, 06, 7C, 30, CF, 00, 07, 00,
A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
A0, 0D, 06, 7D, 30, CF, 00, 08, 00,
A0, 0D, 06, 80, 2F, AF, 05, 80, 90,
A0, 0D, 06, 80, 44, A3, 90, 03, 00,
A0, 0D, 06, 84, 2F, AF, 05, 80, 92,
A0, 0D, 06, 84, 44, A3, 90, 03, 00,
A0, 0D, 06, 88, 2F, 7F, 04, 80, 10,
A0, 0D, 06, 88, 30, 5F, 00, 16, 00,
A0, 0D, 03, 88, 47, 00,
A0, 0D, 06, 88, 44, A1, 90, 03, 00,
A0, 0D, 03, 0C, 48, 18,
A0, 0D, 03, 10, 43, 20,
A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
A0, 0D, 03, 6A, 16, 00,
A0, 0D, 03, 6A, 15, 01,
A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F,
A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
A0, 0D, 03, 8C, 16, 00,
A0, 0D, 03, 8C, 15, 00,
A0, 0D, 06, 92, 42, 90, 10, FF, FF
}
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_5={
20, 02, 37, 07,
A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
A0, 0D, 03, 92, 16, 00,
A0, 0D, 03, 92, 15, 00,
A0, 0D, 06, 0A, 30, CF, 00, 08, 00,
A0, 0D, 06, 0A, 2F, 8F, 05, 80, 0C,
A0, 0D, 03, 0A, 48, 10,
A0, 0D, 06, 0A, 44, A3, 90, 03, 00
}
# *** ALM(NO BOOSTER) FW VERSION = 08.01.1F ***
NXP_RF_CONF_BLK_6={
}
###############################################################################
# Core configuration extensions
# It includes
# A002 - Clock Request
# 0x00 - Disabled
# 0x01 - Enabled
# A003 - Clock Selection
# Please refer to User Manual
# A004 - Clock Time Out
# Defined in ms
# A00E - Load Modulation Mode
# 0x00 - PLM
# 0x01 - ALM
# A011 - Clock specific configuration
# Please refer to User Manual
# A012 - NFCEE interface 2 configuration
# 0x00 - SWP 2 interface is used
# 0x02 - DWP interface is used
# A013 - TVdd configuration
# 0x00 - TVdd is set to 3.1V in Poll mode
# 0x02 - TVdd is set to 2.7V in Poll mode
# A040-A043 - Low Power Card Detector
# Please refer to Application Note of LPCD
# A05E - Jewel Reader
# 0x00 - RID is not sent during activation
# 0x01 - RID is sent during activation
# A061 - Retry after LPCD
# 0b0000XXXX - Number of retry if activation failed
# 0bXXXX0000 - Duration to wait before retry (10ms per step)
# Please refer to User Manual
# A0CD - SWP interface 1: S1 line behavior
# Defined S1 High time-out during Activation sequence
# A0EC - SWP1 interface
# 0x00 - Disabled
# 0x01 - Enabled
# A0ED - SWP2 interface
# 0x00 - Disabled
# 0x01 - Enabled
NXP_CORE_CONF_EXTN={20, 02, 40, 0F,
A0, 02, 01, 01,
A0, 04, 01, 0A,
A0, 0E, 01, 01,
A0, 11, 04, 01, 22, 67, CD,
A0, 12, 01, 00,
A0, 13, 01, 00,
A0, 40, 01, 01,
A0, 41, 01, 02,
A0, 42, 01, 19,
A0, 43, 01, 00,
A0, 5E, 01, 01,
A0, 61, 01, 00,
A0, CD, 01, 0F,
A0, EC, 01, 01,
A0, ED, 01, 00
}
###############################################################################
# Core configuration settings
# It includes
# 18 - Poll Mode NFC-F: PF_BIT_RATE
# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
# 33 - Lis. Mode NFC-A: LA_SEL_INFO
# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
# 60 - Lis. Mode NFC-DEP: LN_WT
# 80 - Other Param.: RF_FIELD_INFO
# 81 - Other Param.: RF_NFCEE_ACTION
# 82 - Other Param.: NFCDEP_OP
NXP_CORE_CONF={ 20, 02, 2E, 0E,
18, 01, 01,
21, 01, 00,
28, 01, 01,
30, 01, 08,
31, 01, 03,
33, 04, 01, 02, 03, 04,
50, 01, 02,
54, 01, 06,
5B, 01, 00,
60, 01, 0E,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
3C, 01, 04
}
###############################################################################
# Mifare Classic Key settings
#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
# A0, 52, 06, D3, F7, D3, F7, D3, F7,
# A0, 53, 06, FF, FF, FF, FF, FF, FF,
# A0, 54, 06, 00, 00, 00, 00, 00, 00}
###############################################################################
# Default SE Options
# No secure element 0x00
# eSE 0x01
# UICC 0x02
# MULTI_SE 0x03
NXP_DEFAULT_SE=0x02
###############################################################################
NXP_DEFAULT_NFCEE_TIMEOUT=0x06
###############################################################################
#Enable SWP full power mode when phone is power off
NXP_SWP_FULL_PWR_ON=0x00
###############################################################################
#Chip type
#PN547C2 0x01
#PN65T 0x02
NXP_NFC_CHIP=0x01

20
configs/nfcee_access.xml
View File

@ -1,20 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<resources xmlns:xliff="urn:oasis:names:tc:xliff:document:1.2">
<!-- Applications granted NFCEE access on user builds
See packages/apps/Nfc/etc/sample_nfcee_access.xml for full documentation.
-->
<!-- Samsung nfcextras Signature -->
<signer android:signature="30820411308202f9a003020102020900fd222d6fc87acde0300d06092a864886f70d010105050030819e310b3009060355040613024b523113301106035504080c0a536f7574684b6f7265613112301006035504070c095375776f6e43697479311b3019060355040a0c1253616d73756e67436f72706f726174696f6e310c300a060355040b0c03444d433114301206035504030c0b53616d73756e67436572743125302306092a864886f70d01090116166d2e73656375726974794073616d73756e672e636f6d3020170d3133303132343035323231305a180f32313132313233313035323231305a30819e310b3009060355040613024b523113301106035504080c0a536f7574684b6f7265613112301006035504070c095375776f6e43697479311b3019060355040a0c1253616d73756e67436f72706f726174696f6e310c300a060355040b0c03444d433114301206035504030c0b53616d73756e67436572743125302306092a864886f70d01090116166d2e73656375726974794073616d73756e672e636f6d30820120300d06092a864886f70d01010105000382010d00308201080282010100a2c51f56a1c8bf64ada0af152ced2344ac070b447efc85f1b69ce90fbc2b7a71257240c215eedbf7445c474fe34d62bc3035d79ba110859118f1200ecc9ae48b56400e187591272d59734e456d9dfd5a1f3227a30b9448bda84c2901b501295445e204ddb6f9f9e36b2560998f1764e446176fe5d83987220f8ed15106dc7c8ecb6798de45f5fbae54efe2b35a379631f545f84c98243aa4d92ef339330f954ad32e4e97aff69cbf68928484b03a8fa8eafdc8ff2a9801f249302d467b05f99a1680e4fb5b11624d5e53d67f09e86b82dd7305e3e483b12e3720fcccc2bc8857f13b6e1d60512074004f67d86241940eaba34afda2af3904b04913fa50f499f7020103a350304e301d0603551d0e04160414eef0f8211dccf6e442f3388889c9a3ea3ce0236c301f0603551d23041830168014eef0f8211dccf6e442f3388889c9a3ea3ce0236c300c0603551d13040530030101ff300d06092a864886f70d01010505000382010100395c7e7900c471e03fa9850905c6ab1edc5a8b7d43a16689d9bb1ec1a06513c4ea8f7471c6e474244174261cc151ae8d1a61019e0ed81fffee8afa1d01d85a32de796f4b46d0d5ddfcca7d1f90d523b54751f505a4e3b059569f24ba2564d72fbc4081533840f618c2993d935134d3c987605e032f6a12889af3190af1714a90f2a3476b8e0016ab45564bf10e611899babd86af33149ca6838b0a885c752ffe879f37997f262e819c62cf59caa794cfaaf8e3c462f5092a34264f0634316b13a67a644e104dc4070e8b6628a46f41da7e3c741f6edc21152f9f947dde6fe14b58f34e4d9e7abd103cb1ca9e09eb4fa5b553baa413329bd3919caca2d52e6d4b" />
<!-- Samsung Platform signature -->
<signer android:signature="308204d4308203bca003020102020900d20995a79c0daad6300d06092a864886f70d01010505003081a2310b3009060355040613024b52311430120603550408130b536f757468204b6f726561311330110603550407130a5375776f6e2043697479311c301a060355040a131353616d73756e6720436f72706f726174696f6e310c300a060355040b1303444d43311530130603550403130c53616d73756e6720436572743125302306092a864886f70d0109011616616e64726f69642e6f734073616d73756e672e636f6d301e170d3131303632323132323531325a170d3338313130373132323531325a3081a2310b3009060355040613024b52311430120603550408130b536f757468204b6f726561311330110603550407130a5375776f6e2043697479311c301a060355040a131353616d73756e6720436f72706f726174696f6e310c300a060355040b1303444d43311530130603550403130c53616d73756e6720436572743125302306092a864886f70d0109011616616e64726f69642e6f734073616d73756e672e636f6d30820120300d06092a864886f70d01010105000382010d00308201080282010100c986384a3e1f2fb206670e78ef232215c0d26f45a22728db99a44da11c35ac33a71fe071c4a2d6825a9b4c88b333ed96f3c5e6c666d60f3ee94c490885abcf8dc660f707aabc77ead3e2d0d8aee8108c15cd260f2e85042c28d2f292daa3c6da0c7bf2391db7841aade8fdf0c9d0defcf77124e6d2de0a9e0d2da746c3670e4ffcdc85b701bb4744861b96ff7311da3603c5a10336e55ffa34b4353eedc85f51015e1518c67e309e39f87639ff178107f109cd18411a6077f26964b6e63f8a70b9619db04306a323c1a1d23af867e19f14f570ffe573d0e3a0c2b30632aaec3173380994be1e341e3a90bd2e4b615481f46db39ea83816448ec35feb1735c1f3020103a382010b30820107301d0603551d0e04160414932c3af70b627a0c7610b5a0e7427d6cfaea3f1e3081d70603551d230481cf3081cc8014932c3af70b627a0c7610b5a0e7427d6cfaea3f1ea181a8a481a53081a2310b3009060355040613024b52311430120603550408130b536f757468204b6f726561311330110603550407130a5375776f6e2043697479311c301a060355040a131353616d73756e6720436f72706f726174696f6e310c300a060355040b1303444d43311530130603550403130c53616d73756e6720436572743125302306092a864886f70d0109011616616e64726f69642e6f734073616d73756e672e636f6d820900d20995a79c0daad6300c0603551d13040530030101ff300d06092a864886f70d01010505000382010100329601fe40e036a4a86cc5d49dd8c1b5415998e72637538b0d430369ac51530f63aace8c019a1a66616a2f1bb2c5fabd6f313261f380e3471623f053d9e3c53f5fd6d1965d7b000e4dc244c1b27e2fe9a323ff077f52c4675e86247aa801187137e30c9bbf01c567a4299db4bf0b25b7d7107a7b81ee102f72ff47950164e26752e114c42f8b9d2a42e7308897ec640ea1924ed13abbe9d120912b62f4926493a86db94c0b46f44c6161d58c2f648164890c512dfb28d42c855bf470dbee2dab6960cad04e81f71525ded46cdd0f359f99c460db9f007d96ce83b4b218ac2d82c48f12608d469733f05a3375594669ccbf8a495544d6c5701e9369c08c810158">
<package android:name="org.simalliance.openmobileapi.service" />
<package android:name="com.samsung.android.walletmanager" />
<package android:name="com.skms.android.agent" />
<package android:name="com.sec.android.wallet" />
<package android:name="com.samsung.android.spay" />
<package android:name="com.samsung.android.spayfw" />
</signer>
</resources>

14
device.mk
View File

@ -1,6 +1,6 @@
#
# Copyright (C) 2014 The CyanogenMod Project
# Copyright (C) 2017 The LineageOS Project
# Copyright (C) 2017-2018 The LineageOS Project
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -27,17 +27,7 @@ DEVICE_PACKAGE_OVERLAYS += $(LOCAL_PATH)/overlay
$(call inherit-product, device/samsung/klte-common/fingerprint/product.mk)
# NFC
# See https://github.com/LineageOS/android_system_nfc/blob/lineage-15.0/halimpl/pn54x/Android.mk#L15
# for magic values of NXP_CHIP_TYPE.
NXP_CHIP_TYPE := 1
PRODUCT_PACKAGES += \
libpn547_fw \
nfc_nci.msm8974
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/configs/libnfc-brcm.conf:system/vendor/etc/libnfc-brcm.conf \
$(LOCAL_PATH)/configs/libnfc-nxp.conf:system/vendor/etc/libnfc-nxp.conf \
$(LOCAL_PATH)/configs/nfcee_access.xml:system/vendor/etc/nfcee_access.xml
$(call inherit-product, device/samsung/klte-common/nfc/pn547/product.mk)
# common klte
$(call inherit-product, device/samsung/klte-common/klte.mk)