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https://github.com/followmsi/android_kernel_google_msm.git
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msm: kgsl: Check if GPU is hung when reserving space in rb
A busy loop is executed when we allocate space from the ringbuffer. If the GPU is hung then we can wait indefinitely in the busy loop. Add a wait time to this busy loop, and if the wait time elapses then report a GPU hang instead of waiting indefinitely. Change-Id: I035c39063cbfa25380702720f929df5319e73e61 Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
This commit is contained in:
Shubhraprakash Das
Stephen Boyd
parent
9c9bb87b87
commit
06f2ea67a5
13 changed files with 159 additions and 75 deletions
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@ -246,6 +246,7 @@ error:
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}
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static void adreno_iommu_setstate(struct kgsl_device *device,
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unsigned int context_id,
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uint32_t flags)
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{
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unsigned int pt_val, reg_pt_val;
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@ -256,11 +257,17 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
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struct kgsl_memdesc **reg_map_desc;
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void *reg_map_array = NULL;
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int num_iommu_units, i;
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struct kgsl_context *context;
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struct adreno_context *adreno_ctx = NULL;
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if (!adreno_dev->drawctxt_active)
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return kgsl_mmu_device_setstate(&device->mmu, flags);
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num_iommu_units = kgsl_mmu_get_reg_map_desc(&device->mmu,
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®_map_array);
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context = idr_find(&device->context_idr, context_id);
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adreno_ctx = context->devctxt;
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reg_map_desc = reg_map_array;
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if (kgsl_mmu_enable_clk(&device->mmu,
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@ -375,7 +382,6 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
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sizedwords += (cmds - &link[0]);
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if (sizedwords) {
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unsigned int ts;
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/*
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* add an interrupt at the end of commands so that the smmu
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* disable clock off function will get called
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@ -383,9 +389,13 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
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*cmds++ = cp_type3_packet(CP_INTERRUPT, 1);
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*cmds++ = CP_INT_CNTL__RB_INT_MASK;
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sizedwords += 2;
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ts = adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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/* This returns the per context timestamp but we need to
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* use the global timestamp for iommu clock disablement */
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adreno_ringbuffer_issuecmds(device, adreno_ctx,
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KGSL_CMD_FLAGS_PMODE,
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&link[0], sizedwords);
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kgsl_mmu_disable_clk_on_ts(&device->mmu, ts, true);
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kgsl_mmu_disable_clk_on_ts(&device->mmu,
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adreno_dev->ringbuffer.timestamp[KGSL_MEMSTORE_GLOBAL], true);
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}
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done:
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if (num_iommu_units)
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@ -393,6 +403,7 @@ done:
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}
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static void adreno_gpummu_setstate(struct kgsl_device *device,
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unsigned int context_id,
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uint32_t flags)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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@ -400,6 +411,8 @@ static void adreno_gpummu_setstate(struct kgsl_device *device,
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unsigned int *cmds = &link[0];
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int sizedwords = 0;
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unsigned int mh_mmu_invalidate = 0x00000003; /*invalidate all and tc */
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struct kgsl_context *context;
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struct adreno_context *adreno_ctx = NULL;
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/*
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* Fix target freeze issue by adding TLB flush for each submit
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@ -414,6 +427,9 @@ static void adreno_gpummu_setstate(struct kgsl_device *device,
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* easier to filter out the mmu accesses from the dump
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*/
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if (!kgsl_cff_dump_enable && adreno_dev->drawctxt_active) {
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context = idr_find(&device->context_idr, context_id);
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adreno_ctx = context->devctxt;
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if (flags & KGSL_MMUFLAGS_PTUPDATE) {
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/* wait for graphics pipe to be idle */
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*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
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@ -486,7 +502,8 @@ static void adreno_gpummu_setstate(struct kgsl_device *device,
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sizedwords += 2;
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}
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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adreno_ringbuffer_issuecmds(device, adreno_ctx,
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KGSL_CMD_FLAGS_PMODE,
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&link[0], sizedwords);
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} else {
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kgsl_mmu_device_setstate(&device->mmu, flags);
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@ -494,13 +511,14 @@ static void adreno_gpummu_setstate(struct kgsl_device *device,
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}
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static void adreno_setstate(struct kgsl_device *device,
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unsigned int context_id,
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uint32_t flags)
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{
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/* call the mmu specific handler */
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if (KGSL_MMU_TYPE_GPU == kgsl_mmu_get_mmutype())
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return adreno_gpummu_setstate(device, flags);
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return adreno_gpummu_setstate(device, context_id, flags);
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else if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype())
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return adreno_iommu_setstate(device, flags);
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return adreno_iommu_setstate(device, context_id, flags);
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}
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static unsigned int
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@ -896,8 +914,7 @@ done:
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return ret;
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}
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static int
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adreno_dump_and_recover(struct kgsl_device *device)
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int adreno_dump_and_recover(struct kgsl_device *device)
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{
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int result = -ETIMEDOUT;
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@ -937,6 +954,7 @@ adreno_dump_and_recover(struct kgsl_device *device)
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done:
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return result;
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}
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EXPORT_SYMBOL(adreno_dump_and_recover);
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static int adreno_getproperty(struct kgsl_device *device,
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enum kgsl_property_type type,
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@ -1325,6 +1343,7 @@ static int kgsl_check_interrupt_timestamp(struct kgsl_device *device,
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int status;
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unsigned int ref_ts, enableflag;
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unsigned int context_id;
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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mutex_lock(&device->mutex);
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context_id = _get_context_id(context);
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@ -1370,8 +1389,15 @@ static int kgsl_check_interrupt_timestamp(struct kgsl_device *device,
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* get an interrupt */
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cmds[0] = cp_type3_packet(CP_NOP, 1);
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cmds[1] = 0;
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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&cmds[0], 2);
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if (adreno_dev->drawctxt_active)
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adreno_ringbuffer_issuecmds(device,
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adreno_dev->drawctxt_active,
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KGSL_CMD_FLAGS_NONE, &cmds[0], 2);
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else
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/* We would never call this function if there
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* was no active contexts running */
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BUG();
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}
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}
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unlock:
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@ -99,7 +99,8 @@ struct adreno_gpudev {
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int (*ctxt_create)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_save)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_restore)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_draw_workaround)(struct adreno_device *);
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void (*ctxt_draw_workaround)(struct adreno_device *,
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struct adreno_context *);
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irqreturn_t (*irq_handler)(struct adreno_device *);
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void (*irq_control)(struct adreno_device *, int);
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void * (*snapshot)(struct adreno_device *, void *, int *, int);
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@ -143,6 +144,8 @@ struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
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void *adreno_snapshot(struct kgsl_device *device, void *snapshot, int *remain,
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int hang);
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int adreno_dump_and_recover(struct kgsl_device *device);
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static inline int adreno_is_a200(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A200);
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@ -1450,7 +1450,8 @@ done:
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return ret;
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}
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static void a2xx_drawctxt_workaround(struct adreno_device *adreno_dev)
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static void a2xx_drawctxt_draw_workaround(struct adreno_device *adreno_dev,
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struct adreno_context *context)
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{
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struct kgsl_device *device = &adreno_dev->dev;
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unsigned int cmd[11];
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@ -1497,7 +1498,7 @@ static void a2xx_drawctxt_workaround(struct adreno_device *adreno_dev)
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| adreno_dev->pix_shader_start;
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}
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_PMODE,
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&cmd[0], cmds - cmd);
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}
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@ -1516,12 +1517,13 @@ static void a2xx_drawctxt_save(struct adreno_device *adreno_dev,
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if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
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/* save registers and constants. */
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->reg_save, 3);
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if (context->flags & CTXT_FLAGS_SHADER_SAVE) {
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/* save shader partitioning and instructions. */
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adreno_ringbuffer_issuecmds(device,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_PMODE,
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context->shader_save, 3);
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@ -1529,7 +1531,8 @@ static void a2xx_drawctxt_save(struct adreno_device *adreno_dev,
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* fixup shader partitioning parameter for
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* SET_SHADER_BASES.
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*/
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->shader_fixup, 3);
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context->flags |= CTXT_FLAGS_SHADER_RESTORE;
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@ -1541,19 +1544,21 @@ static void a2xx_drawctxt_save(struct adreno_device *adreno_dev,
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/* save gmem.
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* (note: changes shader. shader must already be saved.)
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*/
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_PMODE,
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context->context_gmem_shadow.gmem_save, 3);
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/* Restore TP0_CHICKEN */
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if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->chicken_restore, 3);
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}
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adreno_dev->gpudev->ctx_switches_since_last_draw = 0;
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context->flags |= CTXT_FLAGS_GMEM_RESTORE;
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} else if (adreno_is_a2xx(adreno_dev))
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a2xx_drawctxt_workaround(adreno_dev);
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a2xx_drawctxt_draw_workaround(adreno_dev, context);
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}
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static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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@ -1564,7 +1569,8 @@ static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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if (context == NULL) {
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/* No context - set the default apgetable and thats it */
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kgsl_mmu_setstate(&device->mmu, device->mmu.defaultpagetable);
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kgsl_mmu_setstate(&device->mmu, device->mmu.defaultpagetable,
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adreno_dev->drawctxt_active->id);
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return;
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}
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@ -1576,8 +1582,9 @@ static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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cmds[3] = device->memstore.gpuaddr +
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KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context);
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cmds[4] = context->id;
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE, cmds, 5);
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kgsl_mmu_setstate(&device->mmu, context->pagetable);
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adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_NONE,
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cmds, 5);
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kgsl_mmu_setstate(&device->mmu, context->pagetable, context->id);
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#ifndef CONFIG_MSM_KGSL_CFF_DUMP_NO_CONTEXT_MEM_DUMP
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kgsl_cffdump_syncmem(NULL, &context->gpustate,
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@ -1589,12 +1596,14 @@ static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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* (note: changes shader. shader must not already be restored.)
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*/
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if (context->flags & CTXT_FLAGS_GMEM_RESTORE) {
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_PMODE,
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context->context_gmem_shadow.gmem_restore, 3);
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if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
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/* Restore TP0_CHICKEN */
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->chicken_restore, 3);
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}
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@ -1604,12 +1613,12 @@ static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
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/* restore registers and constants. */
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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context->reg_restore, 3);
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE, context->reg_restore, 3);
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/* restore shader instructions & partitioning. */
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if (context->flags & CTXT_FLAGS_SHADER_RESTORE) {
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adreno_ringbuffer_issuecmds(device,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->shader_restore, 3);
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}
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@ -1618,8 +1627,8 @@ static void a2xx_drawctxt_restore(struct adreno_device *adreno_dev,
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if (adreno_is_a20x(adreno_dev)) {
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cmds[0] = cp_type3_packet(CP_SET_BIN_BASE_OFFSET, 1);
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cmds[1] = context->bin_base_offset;
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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cmds, 2);
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE, cmds, 2);
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}
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}
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@ -2011,7 +2020,7 @@ struct adreno_gpudev adreno_a2xx_gpudev = {
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.ctxt_create = a2xx_drawctxt_create,
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.ctxt_save = a2xx_drawctxt_save,
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.ctxt_restore = a2xx_drawctxt_restore,
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.ctxt_draw_workaround = a2xx_drawctxt_workaround,
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.ctxt_draw_workaround = a2xx_drawctxt_draw_workaround,
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.irq_handler = a2xx_irq_handler,
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.irq_control = a2xx_irq_control,
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.snapshot = a2xx_snapshot,
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@ -2226,16 +2226,17 @@ static void a3xx_drawctxt_save(struct adreno_device *adreno_dev,
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if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
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/* Fixup self modifying IBs for save operations */
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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context->save_fixup, 3);
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE, context->save_fixup, 3);
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/* save registers and constants. */
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_NONE,
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context->regconstant_save, 3);
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if (context->flags & CTXT_FLAGS_SHADER_SAVE) {
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/* Save shader instructions */
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adreno_ringbuffer_issuecmds(device,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_PMODE, context->shader_save, 3);
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context->flags |= CTXT_FLAGS_SHADER_RESTORE;
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@ -2249,7 +2250,8 @@ static void a3xx_drawctxt_save(struct adreno_device *adreno_dev,
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* already be saved.)
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*/
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
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adreno_ringbuffer_issuecmds(device, context,
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KGSL_CMD_FLAGS_PMODE,
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context->context_gmem_shadow.
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gmem_save, 3);
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context->flags |= CTXT_FLAGS_GMEM_RESTORE;
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@ -2264,7 +2266,8 @@ static void a3xx_drawctxt_restore(struct adreno_device *adreno_dev,
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if (context == NULL) {
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/* No context - set the default pagetable and thats it */
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kgsl_mmu_setstate(&device->mmu, device->mmu.defaultpagetable);
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kgsl_mmu_setstate(&device->mmu, device->mmu.defaultpagetable,
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adreno_dev->drawctxt_active->id);
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return;
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}
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@ -2276,8 +2279,9 @@ static void a3xx_drawctxt_restore(struct adreno_device *adreno_dev,
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cmds[3] = device->memstore.gpuaddr +
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KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context);
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cmds[4] = context->id;
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adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE, cmds, 5);
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kgsl_mmu_setstate(&device->mmu, context->pagetable);
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adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_NONE,
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cmds, 5);
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kgsl_mmu_setstate(&device->mmu, context->pagetable, context->id);
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/*
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* Restore GMEM. (note: changes shader.
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@ -2285,29 +2289,34 @@ static void a3xx_drawctxt_restore(struct adreno_device *adreno_dev,
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*/
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||||
if (context->flags & CTXT_FLAGS_GMEM_RESTORE) {
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE,
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_PMODE,
|
||||
context->context_gmem_shadow.
|
||||
gmem_restore, 3);
|
||||
context->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
|
||||
}
|
||||
|
||||
if (!(context->flags & CTXT_FLAGS_PREAMBLE)) {
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
|
||||
context->reg_restore, 3);
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_NONE, context->reg_restore, 3);
|
||||
|
||||
/* Fixup self modifying IBs for restore operations */
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_NONE,
|
||||
context->restore_fixup, 3);
|
||||
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_NONE,
|
||||
context->constant_restore, 3);
|
||||
|
||||
if (context->flags & CTXT_FLAGS_SHADER_RESTORE)
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_NONE,
|
||||
context->shader_restore, 3);
|
||||
|
||||
/* Restore HLSQ_CONTROL_0 register */
|
||||
adreno_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NONE,
|
||||
adreno_ringbuffer_issuecmds(device, context,
|
||||
KGSL_CMD_FLAGS_NONE,
|
||||
context->hlsqcontrol_restore, 3);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -274,7 +274,7 @@ void adreno_drawctxt_switch(struct adreno_device *adreno_dev,
|
|||
if (adreno_dev->gpudev->ctxt_draw_workaround &&
|
||||
adreno_is_a225(adreno_dev))
|
||||
adreno_dev->gpudev->ctxt_draw_workaround(
|
||||
adreno_dev);
|
||||
adreno_dev, drawctxt);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@ adreno_ringbuffer_waitspace(struct adreno_ringbuffer *rb, unsigned int numcmds,
|
|||
unsigned int freecmds;
|
||||
unsigned int *cmds;
|
||||
uint cmds_gpu;
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
|
||||
unsigned long wait_timeout = msecs_to_jiffies(adreno_dev->wait_timeout);
|
||||
unsigned long wait_time;
|
||||
|
||||
/* if wptr ahead, fill the remaining with NOPs */
|
||||
if (wptr_ahead) {
|
||||
|
|
@ -79,13 +82,27 @@ adreno_ringbuffer_waitspace(struct adreno_ringbuffer *rb, unsigned int numcmds,
|
|||
rb->wptr = 0;
|
||||
}
|
||||
|
||||
wait_time = jiffies + wait_timeout;
|
||||
/* wait for space in ringbuffer */
|
||||
do {
|
||||
while (1) {
|
||||
GSL_RB_GET_READPTR(rb, &rb->rptr);
|
||||
|
||||
freecmds = rb->rptr - rb->wptr;
|
||||
|
||||
} while ((freecmds != 0) && (freecmds <= numcmds));
|
||||
if (freecmds == 0 || freecmds > numcmds)
|
||||
break;
|
||||
|
||||
if (time_after(jiffies, wait_time)) {
|
||||
KGSL_DRV_ERR(rb->device,
|
||||
"Timed out while waiting for freespace in ringbuffer "
|
||||
"rptr: 0x%x, wptr: 0x%x\n", rb->rptr, rb->wptr);
|
||||
if (!adreno_dump_and_recover(rb->device))
|
||||
wait_time = jiffies + wait_timeout;
|
||||
else
|
||||
/* GPU is hung and we cannot recover */
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int *adreno_ringbuffer_allocspace(struct adreno_ringbuffer *rb,
|
||||
|
|
@ -439,15 +456,13 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
|||
unsigned int context_id = KGSL_MEMSTORE_GLOBAL;
|
||||
unsigned int gpuaddr = rb->device->memstore.gpuaddr;
|
||||
|
||||
if (context != NULL) {
|
||||
/*
|
||||
* if the context was not created with per context timestamp
|
||||
* support, we must use the global timestamp since issueibcmds
|
||||
* will be returning that one.
|
||||
*/
|
||||
if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS)
|
||||
context_id = context->id;
|
||||
}
|
||||
/*
|
||||
* if the context was not created with per context timestamp
|
||||
* support, we must use the global timestamp since issueibcmds
|
||||
* will be returning that one.
|
||||
*/
|
||||
if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS)
|
||||
context_id = context->id;
|
||||
|
||||
/* reserve space to temporarily turn off protected mode
|
||||
* error checking if needed
|
||||
|
|
@ -460,7 +475,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
|||
total_sizedwords += 7;
|
||||
|
||||
total_sizedwords += 2; /* scratchpad ts for recovery */
|
||||
if (context) {
|
||||
if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
|
||||
total_sizedwords += 3; /* sop timestamp */
|
||||
total_sizedwords += 4; /* eop timestamp */
|
||||
total_sizedwords += 3; /* global timestamp without cache
|
||||
|
|
@ -470,6 +485,15 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
|||
}
|
||||
|
||||
ringcmds = adreno_ringbuffer_allocspace(rb, total_sizedwords);
|
||||
/* GPU may hang during space allocation, if thats the case the current
|
||||
* context may have hung the GPU */
|
||||
if (context->flags & CTXT_FLAGS_GPU_HANG) {
|
||||
KGSL_CTXT_WARN(rb->device,
|
||||
"Context %p caused a gpu hang. Will not accept commands for context %d\n",
|
||||
context, context->id);
|
||||
return rb->timestamp[context_id];
|
||||
}
|
||||
|
||||
rcmd_gpu = rb->buffer_desc.gpuaddr
|
||||
+ sizeof(uint)*(rb->wptr-total_sizedwords);
|
||||
|
||||
|
|
@ -525,7 +549,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
|||
GSL_RB_WRITE(ringcmds, rcmd_gpu, 0x00);
|
||||
}
|
||||
|
||||
if (context) {
|
||||
if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
|
||||
/* start-of-pipeline timestamp */
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
cp_type3_packet(CP_MEM_WRITE, 2));
|
||||
|
|
@ -593,6 +617,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
|||
|
||||
unsigned int
|
||||
adreno_ringbuffer_issuecmds(struct kgsl_device *device,
|
||||
struct adreno_context *drawctxt,
|
||||
unsigned int flags,
|
||||
unsigned int *cmds,
|
||||
int sizedwords)
|
||||
|
|
@ -603,7 +628,7 @@ adreno_ringbuffer_issuecmds(struct kgsl_device *device,
|
|||
if (device->state & KGSL_STATE_HUNG)
|
||||
return kgsl_readtimestamp(device, KGSL_MEMSTORE_GLOBAL,
|
||||
KGSL_TIMESTAMP_RETIRED);
|
||||
return adreno_ringbuffer_addcmds(rb, NULL, flags, cmds, sizedwords);
|
||||
return adreno_ringbuffer_addcmds(rb, drawctxt, flags, cmds, sizedwords);
|
||||
}
|
||||
|
||||
static bool _parse_ibs(struct kgsl_device_private *dev_priv, uint gpuaddr,
|
||||
|
|
@ -870,7 +895,7 @@ adreno_ringbuffer_issueibcmds(struct kgsl_device_private *dev_priv,
|
|||
*cmds++ = cp_nop_packet(1);
|
||||
*cmds++ = KGSL_END_OF_IB_IDENTIFIER;
|
||||
|
||||
kgsl_setstate(&device->mmu,
|
||||
kgsl_setstate(&device->mmu, context->id,
|
||||
kgsl_mmu_pt_get_flags(device->mmu.hwpagetable,
|
||||
device->id));
|
||||
|
||||
|
|
|
|||
|
|
@ -104,6 +104,7 @@ void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb);
|
|||
void adreno_ringbuffer_close(struct adreno_ringbuffer *rb);
|
||||
|
||||
unsigned int adreno_ringbuffer_issuecmds(struct kgsl_device *device,
|
||||
struct adreno_context *drawctxt,
|
||||
unsigned int flags,
|
||||
unsigned int *cmdaddr,
|
||||
int sizedwords);
|
||||
|
|
|
|||
|
|
@ -97,7 +97,8 @@ struct kgsl_functable {
|
|||
/* Optional functions - these functions are not mandatory. The
|
||||
driver will check that the function pointer is not NULL before
|
||||
calling the hook */
|
||||
void (*setstate) (struct kgsl_device *device, uint32_t flags);
|
||||
void (*setstate) (struct kgsl_device *device, unsigned int context_id,
|
||||
uint32_t flags);
|
||||
int (*drawctxt_create) (struct kgsl_device *device,
|
||||
struct kgsl_pagetable *pagetable, struct kgsl_context *context,
|
||||
uint32_t flags);
|
||||
|
|
|
|||
|
|
@ -485,7 +485,8 @@ static void kgsl_gpummu_default_setstate(struct kgsl_mmu *mmu,
|
|||
}
|
||||
|
||||
static void kgsl_gpummu_setstate(struct kgsl_mmu *mmu,
|
||||
struct kgsl_pagetable *pagetable)
|
||||
struct kgsl_pagetable *pagetable,
|
||||
unsigned int context_id)
|
||||
{
|
||||
if (mmu->flags & KGSL_FLAGS_STARTED) {
|
||||
/* page table not current, then setup mmu to use new
|
||||
|
|
@ -499,7 +500,7 @@ static void kgsl_gpummu_setstate(struct kgsl_mmu *mmu,
|
|||
kgsl_mmu_pt_get_flags(pagetable, mmu->device->id);
|
||||
|
||||
/* call device specific set page table */
|
||||
kgsl_setstate(mmu, KGSL_MMUFLAGS_TLBFLUSH |
|
||||
kgsl_setstate(mmu, context_id, KGSL_MMUFLAGS_TLBFLUSH |
|
||||
KGSL_MMUFLAGS_PTUPDATE);
|
||||
}
|
||||
}
|
||||
|
|
@ -583,7 +584,7 @@ static int kgsl_gpummu_start(struct kgsl_mmu *mmu)
|
|||
kgsl_regwrite(mmu->device, MH_MMU_VA_RANGE,
|
||||
(KGSL_PAGETABLE_BASE |
|
||||
(CONFIG_MSM_KGSL_PAGE_TABLE_SIZE >> 16)));
|
||||
kgsl_setstate(mmu, KGSL_MMUFLAGS_TLBFLUSH);
|
||||
kgsl_setstate(mmu, KGSL_MEMSTORE_GLOBAL, KGSL_MMUFLAGS_TLBFLUSH);
|
||||
mmu->flags |= KGSL_FLAGS_STARTED;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -617,7 +617,8 @@ static int kgsl_iommu_get_pt_lsb(struct kgsl_mmu *mmu,
|
|||
}
|
||||
|
||||
static void kgsl_iommu_setstate(struct kgsl_mmu *mmu,
|
||||
struct kgsl_pagetable *pagetable)
|
||||
struct kgsl_pagetable *pagetable,
|
||||
unsigned int context_id)
|
||||
{
|
||||
if (mmu->flags & KGSL_FLAGS_STARTED) {
|
||||
struct kgsl_iommu *iommu = mmu->priv;
|
||||
|
|
@ -634,7 +635,8 @@ static void kgsl_iommu_setstate(struct kgsl_mmu *mmu,
|
|||
flags |= KGSL_MMUFLAGS_TLBFLUSH;
|
||||
flags |= kgsl_mmu_pt_get_flags(mmu->hwpagetable,
|
||||
mmu->device->id);
|
||||
kgsl_setstate(mmu, KGSL_MMUFLAGS_PTUPDATE | flags);
|
||||
kgsl_setstate(mmu, context_id,
|
||||
KGSL_MMUFLAGS_PTUPDATE | flags);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -543,13 +543,14 @@ void kgsl_mmu_putpagetable(struct kgsl_pagetable *pagetable)
|
|||
}
|
||||
EXPORT_SYMBOL(kgsl_mmu_putpagetable);
|
||||
|
||||
void kgsl_setstate(struct kgsl_mmu *mmu, uint32_t flags)
|
||||
void kgsl_setstate(struct kgsl_mmu *mmu, unsigned int context_id,
|
||||
uint32_t flags)
|
||||
{
|
||||
struct kgsl_device *device = mmu->device;
|
||||
if (KGSL_MMU_TYPE_NONE == kgsl_mmu_type)
|
||||
return;
|
||||
else if (device->ftbl->setstate)
|
||||
device->ftbl->setstate(device, flags);
|
||||
device->ftbl->setstate(device, context_id, flags);
|
||||
else if (mmu->mmu_ops->mmu_device_setstate)
|
||||
mmu->mmu_ops->mmu_device_setstate(mmu, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -125,7 +125,8 @@ struct kgsl_mmu_ops {
|
|||
int (*mmu_start) (struct kgsl_mmu *mmu);
|
||||
void (*mmu_stop) (struct kgsl_mmu *mmu);
|
||||
void (*mmu_setstate) (struct kgsl_mmu *mmu,
|
||||
struct kgsl_pagetable *pagetable);
|
||||
struct kgsl_pagetable *pagetable,
|
||||
unsigned int context_id);
|
||||
void (*mmu_device_setstate) (struct kgsl_mmu *mmu,
|
||||
uint32_t flags);
|
||||
void (*mmu_pagefault) (struct kgsl_mmu *mmu);
|
||||
|
|
@ -193,7 +194,8 @@ int kgsl_mmu_map_global(struct kgsl_pagetable *pagetable,
|
|||
int kgsl_mmu_unmap(struct kgsl_pagetable *pagetable,
|
||||
struct kgsl_memdesc *memdesc);
|
||||
unsigned int kgsl_virtaddr_to_physaddr(void *virtaddr);
|
||||
void kgsl_setstate(struct kgsl_mmu *mmu, uint32_t flags);
|
||||
void kgsl_setstate(struct kgsl_mmu *mmu, unsigned int context_id,
|
||||
uint32_t flags);
|
||||
int kgsl_mmu_get_ptname_from_ptbase(unsigned int pt_base);
|
||||
int kgsl_mmu_pt_get_flags(struct kgsl_pagetable *pt,
|
||||
enum kgsl_deviceid id);
|
||||
|
|
@ -219,10 +221,11 @@ static inline unsigned int kgsl_mmu_get_current_ptbase(struct kgsl_mmu *mmu)
|
|||
}
|
||||
|
||||
static inline void kgsl_mmu_setstate(struct kgsl_mmu *mmu,
|
||||
struct kgsl_pagetable *pagetable)
|
||||
struct kgsl_pagetable *pagetable,
|
||||
unsigned int context_id)
|
||||
{
|
||||
if (mmu->mmu_ops && mmu->mmu_ops->mmu_setstate)
|
||||
mmu->mmu_ops->mmu_setstate(mmu, pagetable);
|
||||
mmu->mmu_ops->mmu_setstate(mmu, pagetable, context_id);
|
||||
}
|
||||
|
||||
static inline void kgsl_mmu_device_setstate(struct kgsl_mmu *mmu,
|
||||
|
|
|
|||
|
|
@ -444,11 +444,13 @@ z180_cmdstream_issueibcmds(struct kgsl_device_private *dev_priv,
|
|||
(ctrl & KGSL_CONTEXT_CTX_SWITCH)) {
|
||||
KGSL_CMD_INFO(device, "context switch %d -> %d\n",
|
||||
context->id, z180_dev->ringbuffer.prevctx);
|
||||
kgsl_mmu_setstate(&device->mmu, pagetable);
|
||||
kgsl_mmu_setstate(&device->mmu, pagetable,
|
||||
KGSL_MEMSTORE_GLOBAL);
|
||||
cnt = PACKETSIZE_STATESTREAM;
|
||||
ofs = 0;
|
||||
}
|
||||
kgsl_setstate(&device->mmu,
|
||||
KGSL_MEMSTORE_GLOBAL,
|
||||
kgsl_mmu_pt_get_flags(device->mmu.hwpagetable,
|
||||
device->id));
|
||||
|
||||
|
|
@ -861,7 +863,8 @@ z180_drawctxt_destroy(struct kgsl_device *device,
|
|||
if (z180_dev->ringbuffer.prevctx == context->id) {
|
||||
z180_dev->ringbuffer.prevctx = Z180_INVALID_CONTEXT;
|
||||
device->mmu.hwpagetable = device->mmu.defaultpagetable;
|
||||
kgsl_setstate(&device->mmu, KGSL_MMUFLAGS_PTUPDATE);
|
||||
kgsl_setstate(&device->mmu, KGSL_MEMSTORE_GLOBAL,
|
||||
KGSL_MMUFLAGS_PTUPDATE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue