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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Browse source 
Pull crypto updates from Herbert Xu:
 - New cipher/hash driver for ARM ux500.
 - Code clean-up for aesni-intel.
 - Misc fixes.

Fixed up conflicts in arch/arm/mach-ux500/devices-common.h, where quite
frankly some of it made no sense at all (the pull brought in a
declaration for the dbx500_add_platform_device_noirq() function, which
neither exists nor is used anywhere).

Also some trivial add-add context conflicts in the Kconfig file in
drivers/{char/hw_random,crypto}/

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: aesni-intel - move more common code to ablk_init_common
  crypto: aesni-intel - use crypto_[un]register_algs
  crypto: ux500 - Cleanup hardware identification
  crypto: ux500 - Update DMA handling for 3.4
  mach-ux500: crypto - core support for CRYP/HASH module.
  crypto: ux500 - Add driver for HASH hardware
  crypto: ux500 - Add driver for CRYP hardware
  hwrng: Kconfig - modify default state for atmel-rng driver
  hwrng: omap - use devm_request_and_ioremap
  crypto: crypto4xx - move up err_request_irq label
  crypto, xor: Sanitize checksumming function selection output
  crypto: caam - add backward compatible string sec4.0
This commit is contained in:
Linus Torvalds 2012-05-23 15:59:10 -07:00
commit 0bd3fbd4ab
30 changed files with 5777 additions and 511 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

48
arch/arm/mach-ux500/board-mop500.c
View file

@ -47,6 +47,7 @@
#include <mach/setup.h>
#include <mach/devices.h>
#include <mach/irqs.h>
#include <mach/crypto-ux500.h>
#include "ste-dma40-db8500.h"
#include "devices-db8500.h"
@ -417,6 +418,45 @@ static void mop500_prox_deactivate(struct device *dev)
regulator_put(prox_regulator);
}
static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
},
.engine_to_mem = {
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
}
};
static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_16,
.dst_info.psize = STEDMA40_PSIZE_LOG_16,
};
static struct hash_platform_data u8500_hash1_platform_data = {
.mem_to_engine = &u8500_hash_dma_cfg_tx,
.dma_filter = stedma40_filter,
};
/* add any platform devices here - TODO */
static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
@ -624,6 +664,12 @@ static void __init mop500_uart_init(struct device *parent)
db8500_add_uart2(parent, &uart2_plat);
}
static void __init u8500_cryp1_hash1_init(struct device *parent)
{
db8500_add_cryp1(parent, &u8500_cryp1_platform_data);
db8500_add_hash1(parent, &u8500_hash1_platform_data);
}
static struct platform_device *snowball_platform_devs[] __initdata = {
&snowball_led_dev,
&snowball_key_dev,
@ -654,6 +700,8 @@ static void __init mop500_init_machine(void)
mop500_msp_init(parent);
mop500_uart_init(parent);
u8500_cryp1_hash1_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);

18
arch/arm/mach-ux500/clock.c
View file

@ -381,14 +381,15 @@ static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
/* Peripheral Cluster #6 */
/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL);
static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk);
static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
static struct clk clk_dummy_apb_pclk = {
@ -430,6 +431,7 @@ static struct clk_lookup u8500_clks[] = {
CLK(pka, "pka", NULL),
CLK(hash0, "hash0", NULL),
CLK(cryp0, "cryp0", NULL),
CLK(cryp1, "cryp1", NULL),
/* PRCMU level clock gating */

50
arch/arm/mach-ux500/devices-common.h
View file

@ -13,6 +13,7 @@
#include <linux/sys_soc.h>
#include <linux/amba/bus.h>
#include <plat/i2c.h>
#include <mach/crypto-ux500.h>
struct spi_master_cntlr;
@ -85,6 +86,55 @@ dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
0, NULL, 0);
}
struct cryp_platform_data;
static inline struct platform_device *
dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq,
struct cryp_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
DEFINE_RES_IRQ(irq),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "cryp1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct hash_platform_data;
static inline struct platform_device *
dbx500_add_hash1(struct device *parent, int id, resource_size_t base,
struct hash_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "hash1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct nmk_gpio_platform_data;
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,

3
arch/arm/mach-ux500/devices-db8500.c
View file

@ -104,6 +104,8 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
};
/* Mapping between source event lines and physical device address */
@ -139,6 +141,7 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
};
/* Reserved event lines for memcpy only */

4
arch/arm/mach-ux500/devices-db8500.h
View file

@ -114,4 +114,8 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
IRQ_DB8500_UART2, pdata)
#define db8500_add_cryp1(parent, pdata) \
dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata)
#define db8500_add_hash1(parent, pdata) \
dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata)
#endif

22
arch/arm/mach-ux500/include/mach/crypto-ux500.h Normal file
View file

@ -0,0 +1,22 @@
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYPTO_UX500_H
#define _CRYPTO_UX500_H
#include <linux/dmaengine.h>
#include <plat/ste_dma40.h>
struct hash_platform_data {
void *mem_to_engine;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
struct cryp_platform_data {
struct stedma40_chan_cfg mem_to_engine;
struct stedma40_chan_cfg engine_to_mem;
};
#endif

3
arch/arm/mach-ux500/include/mach/devices.h
View file

@ -14,6 +14,9 @@ extern struct platform_device u8500_gpio_devs[];
extern struct amba_device ux500_pl031_device;
extern struct platform_device ux500_hash1_device;
extern struct platform_device ux500_cryp1_device;
extern struct platform_device u8500_dma40_device;
extern struct platform_device ux500_ske_keypad_device;

3
arch/arm/mach-ux500/include/mach/hardware.h
View file

@ -33,6 +33,9 @@
#include <mach/db8500-regs.h>
#define MSP_TX_RX_REG_OFFSET 0
#define CRYP1_RX_REG_OFFSET 0x10
#define CRYP1_TX_REG_OFFSET 0x8
#define HASH1_TX_REG_OFFSET 0x4
#ifndef __ASSEMBLY__

793
arch/x86/crypto/aesni-intel_glue.c
View file

@ -222,27 +222,6 @@ static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
}
}
static struct crypto_alg aesni_alg = {
.cra_name = "aes",
.cra_driver_name = "aes-aesni",
.cra_priority = 300,
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
.cra_alignmask = 0,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(aesni_alg.cra_list),
.cra_u = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key,
.cia_encrypt = aes_encrypt,
.cia_decrypt = aes_decrypt
}
}
};
static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
{
struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
@ -257,27 +236,6 @@ static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
aesni_dec(ctx, dst, src);
}
static struct crypto_alg __aesni_alg = {
.cra_name = "__aes-aesni",
.cra_driver_name = "__driver-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
.cra_alignmask = 0,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(__aesni_alg.cra_list),
.cra_u = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key,
.cia_encrypt = __aes_encrypt,
.cia_decrypt = __aes_decrypt
}
}
};
static int ecb_encrypt(struct blkcipher_desc *desc,
struct scatterlist *dst, struct scatterlist *src,
unsigned int nbytes)
@ -326,28 +284,6 @@ static int ecb_decrypt(struct blkcipher_desc *desc,
return err;
}
static struct crypto_alg blk_ecb_alg = {
.cra_name = "__ecb-aes-aesni",
.cra_driver_name = "__driver-ecb-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(blk_ecb_alg.cra_list),
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = aes_set_key,
.encrypt = ecb_encrypt,
.decrypt = ecb_decrypt,
},
},
};
static int cbc_encrypt(struct blkcipher_desc *desc,
struct scatterlist *dst, struct scatterlist *src,
unsigned int nbytes)
@ -396,28 +332,6 @@ static int cbc_decrypt(struct blkcipher_desc *desc,
return err;
}
static struct crypto_alg blk_cbc_alg = {
.cra_name = "__cbc-aes-aesni",
.cra_driver_name = "__driver-cbc-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(blk_cbc_alg.cra_list),
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = aes_set_key,
.encrypt = cbc_encrypt,
.decrypt = cbc_decrypt,
},
},
};
#ifdef CONFIG_X86_64
static void ctr_crypt_final(struct crypto_aes_ctx *ctx,
struct blkcipher_walk *walk)
@ -461,29 +375,6 @@ static int ctr_crypt(struct blkcipher_desc *desc,
return err;
}
static struct crypto_alg blk_ctr_alg = {
.cra_name = "__ctr-aes-aesni",
.cra_driver_name = "__driver-ctr-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(blk_ctr_alg.cra_list),
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = aes_set_key,
.encrypt = ctr_crypt,
.decrypt = ctr_crypt,
},
},
};
#endif
static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
@ -551,281 +442,65 @@ static void ablk_exit(struct crypto_tfm *tfm)
cryptd_free_ablkcipher(ctx->cryptd_tfm);
}
static void ablk_init_common(struct crypto_tfm *tfm,
struct cryptd_ablkcipher *cryptd_tfm)
static int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name)
{
struct async_aes_ctx *ctx = crypto_tfm_ctx(tfm);
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher(drv_name, 0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ctx->cryptd_tfm = cryptd_tfm;
tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) +
crypto_ablkcipher_reqsize(&cryptd_tfm->base);
return 0;
}
static int ablk_ecb_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("__driver-ecb-aes-aesni", 0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "__driver-ecb-aes-aesni");
}
static struct crypto_alg ablk_ecb_alg = {
.cra_name = "ecb(aes)",
.cra_driver_name = "ecb-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_ecb_alg.cra_list),
.cra_init = ablk_ecb_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
};
static int ablk_cbc_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("__driver-cbc-aes-aesni", 0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "__driver-cbc-aes-aesni");
}
static struct crypto_alg ablk_cbc_alg = {
.cra_name = "cbc(aes)",
.cra_driver_name = "cbc-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_cbc_alg.cra_list),
.cra_init = ablk_cbc_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
};
#ifdef CONFIG_X86_64
static int ablk_ctr_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("__driver-ctr-aes-aesni", 0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "__driver-ctr-aes-aesni");
}
static struct crypto_alg ablk_ctr_alg = {
.cra_name = "ctr(aes)",
.cra_driver_name = "ctr-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_ctr_alg.cra_list),
.cra_init = ablk_ctr_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_encrypt,
.geniv = "chainiv",
},
},
};
#ifdef HAS_CTR
static int ablk_rfc3686_ctr_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher(
"rfc3686(__driver-ctr-aes-aesni)", 0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "rfc3686(__driver-ctr-aes-aesni)");
}
static struct crypto_alg ablk_rfc3686_ctr_alg = {
.cra_name = "rfc3686(ctr(aes))",
.cra_driver_name = "rfc3686-ctr-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_rfc3686_ctr_alg.cra_list),
.cra_init = ablk_rfc3686_ctr_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE+CTR_RFC3686_NONCE_SIZE,
.max_keysize = AES_MAX_KEY_SIZE+CTR_RFC3686_NONCE_SIZE,
.ivsize = CTR_RFC3686_IV_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
.geniv = "seqiv",
},
},
};
#endif
#endif
#ifdef HAS_LRW
static int ablk_lrw_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("fpu(lrw(__driver-aes-aesni))",
0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "fpu(lrw(__driver-aes-aesni))");
}
static struct crypto_alg ablk_lrw_alg = {
.cra_name = "lrw(aes)",
.cra_driver_name = "lrw-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_lrw_alg.cra_list),
.cra_init = ablk_lrw_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
.max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
};
#endif
#ifdef HAS_PCBC
static int ablk_pcbc_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("fpu(pcbc(__driver-aes-aesni))",
0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "fpu(pcbc(__driver-aes-aesni))");
}
static struct crypto_alg ablk_pcbc_alg = {
.cra_name = "pcbc(aes)",
.cra_driver_name = "pcbc-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_pcbc_alg.cra_list),
.cra_init = ablk_pcbc_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
};
#endif
#ifdef HAS_XTS
static int ablk_xts_init(struct crypto_tfm *tfm)
{
struct cryptd_ablkcipher *cryptd_tfm;
cryptd_tfm = cryptd_alloc_ablkcipher("fpu(xts(__driver-aes-aesni))",
0, 0);
if (IS_ERR(cryptd_tfm))
return PTR_ERR(cryptd_tfm);
ablk_init_common(tfm, cryptd_tfm);
return 0;
return ablk_init_common(tfm, "fpu(xts(__driver-aes-aesni))");
}
static struct crypto_alg ablk_xts_alg = {
.cra_name = "xts(aes)",
.cra_driver_name = "xts-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(ablk_xts_alg.cra_list),
.cra_init = ablk_xts_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = 2 * AES_MIN_KEY_SIZE,
.max_keysize = 2 * AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
};
#endif
#ifdef CONFIG_X86_64
@ -1050,32 +725,6 @@ static int rfc4106_decrypt(struct aead_request *req)
}
}
static struct crypto_alg rfc4106_alg = {
.cra_name = "rfc4106(gcm(aes))",
.cra_driver_name = "rfc4106-gcm-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) + AESNI_ALIGN,
.cra_alignmask = 0,
.cra_type = &crypto_nivaead_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(rfc4106_alg.cra_list),
.cra_init = rfc4106_init,
.cra_exit = rfc4106_exit,
.cra_u = {
.aead = {
.setkey = rfc4106_set_key,
.setauthsize = rfc4106_set_authsize,
.encrypt = rfc4106_encrypt,
.decrypt = rfc4106_decrypt,
.geniv = "seqiv",
.ivsize = 8,
.maxauthsize = 16,
},
},
};
static int __driver_rfc4106_encrypt(struct aead_request *req)
{
u8 one_entry_in_sg = 0;
@ -1233,26 +882,316 @@ static int __driver_rfc4106_decrypt(struct aead_request *req)
}
return retval;
}
#endif
static struct crypto_alg __rfc4106_alg = {
static struct crypto_alg aesni_algs[] = { {
.cra_name = "aes",
.cra_driver_name = "aes-aesni",
.cra_priority = 300,
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx) +
AESNI_ALIGN - 1,
.cra_alignmask = 0,
.cra_module = THIS_MODULE,
.cra_u = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key,
.cia_encrypt = aes_encrypt,
.cia_decrypt = aes_decrypt
}
}
}, {
.cra_name = "__aes-aesni",
.cra_driver_name = "__driver-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx) +
AESNI_ALIGN - 1,
.cra_alignmask = 0,
.cra_module = THIS_MODULE,
.cra_u = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key,
.cia_encrypt = __aes_encrypt,
.cia_decrypt = __aes_decrypt
}
}
}, {
.cra_name = "__ecb-aes-aesni",
.cra_driver_name = "__driver-ecb-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx) +
AESNI_ALIGN - 1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = aes_set_key,
.encrypt = ecb_encrypt,
.decrypt = ecb_decrypt,
},
},
}, {
.cra_name = "__cbc-aes-aesni",
.cra_driver_name = "__driver-cbc-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct crypto_aes_ctx) +
AESNI_ALIGN - 1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = aes_set_key,
.encrypt = cbc_encrypt,
.decrypt = cbc_decrypt,
},
},
}, {
.cra_name = "ecb(aes)",
.cra_driver_name = "ecb-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_ecb_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
}, {
.cra_name = "cbc(aes)",
.cra_driver_name = "cbc-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_cbc_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
#ifdef CONFIG_X86_64
}, {
.cra_name = "__ctr-aes-aesni",
.cra_driver_name = "__driver-ctr-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct crypto_aes_ctx) +
AESNI_ALIGN - 1,
.cra_alignmask = 0,
.cra_type = &crypto_blkcipher_type,
.cra_module = THIS_MODULE,
.cra_u = {
.blkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = aes_set_key,
.encrypt = ctr_crypt,
.decrypt = ctr_crypt,
},
},
}, {
.cra_name = "ctr(aes)",
.cra_driver_name = "ctr-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_ctr_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_encrypt,
.geniv = "chainiv",
},
},
}, {
.cra_name = "__gcm-aes-aesni",
.cra_driver_name = "__driver-gcm-aes-aesni",
.cra_priority = 0,
.cra_flags = CRYPTO_ALG_TYPE_AEAD,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) + AESNI_ALIGN,
.cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
AESNI_ALIGN,
.cra_alignmask = 0,
.cra_type = &crypto_aead_type,
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(__rfc4106_alg.cra_list),
.cra_u = {
.aead = {
.encrypt = __driver_rfc4106_encrypt,
.decrypt = __driver_rfc4106_decrypt,
},
},
};
}, {
.cra_name = "rfc4106(gcm(aes))",
.cra_driver_name = "rfc4106-gcm-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
AESNI_ALIGN,
.cra_alignmask = 0,
.cra_type = &crypto_nivaead_type,
.cra_module = THIS_MODULE,
.cra_init = rfc4106_init,
.cra_exit = rfc4106_exit,
.cra_u = {
.aead = {
.setkey = rfc4106_set_key,
.setauthsize = rfc4106_set_authsize,
.encrypt = rfc4106_encrypt,
.decrypt = rfc4106_decrypt,
.geniv = "seqiv",
.ivsize = 8,
.maxauthsize = 16,
},
},
#ifdef HAS_CTR
}, {
.cra_name = "rfc3686(ctr(aes))",
.cra_driver_name = "rfc3686-ctr-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = 1,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_rfc3686_ctr_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE +
CTR_RFC3686_NONCE_SIZE,
.max_keysize = AES_MAX_KEY_SIZE +
CTR_RFC3686_NONCE_SIZE,
.ivsize = CTR_RFC3686_IV_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
.geniv = "seqiv",
},
},
#endif
#endif
#ifdef HAS_LRW
}, {
.cra_name = "lrw(aes)",
.cra_driver_name = "lrw-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_lrw_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
.max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
#endif
#ifdef HAS_PCBC
}, {
.cra_name = "pcbc(aes)",
.cra_driver_name = "pcbc-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_pcbc_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
#endif
#ifdef HAS_XTS
}, {
.cra_name = "xts(aes)",
.cra_driver_name = "xts-aes-aesni",
.cra_priority = 400,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct async_aes_ctx),
.cra_alignmask = 0,
.cra_type = &crypto_ablkcipher_type,
.cra_module = THIS_MODULE,
.cra_init = ablk_xts_init,
.cra_exit = ablk_exit,
.cra_u = {
.ablkcipher = {
.min_keysize = 2 * AES_MIN_KEY_SIZE,
.max_keysize = 2 * AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
.setkey = ablk_set_key,
.encrypt = ablk_encrypt,
.decrypt = ablk_decrypt,
},
},
#endif
} };
static const struct x86_cpu_id aesni_cpu_id[] = {
@ -1263,120 +1202,24 @@ MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
static int __init aesni_init(void)
{
int err;
int err, i;
if (!x86_match_cpu(aesni_cpu_id))
return -ENODEV;
if ((err = crypto_fpu_init()))
goto fpu_err;
if ((err = crypto_register_alg(&aesni_alg)))
goto aes_err;
if ((err = crypto_register_alg(&__aesni_alg)))
goto __aes_err;
if ((err = crypto_register_alg(&blk_ecb_alg)))
goto blk_ecb_err;
if ((err = crypto_register_alg(&blk_cbc_alg)))
goto blk_cbc_err;
if ((err = crypto_register_alg(&ablk_ecb_alg)))
goto ablk_ecb_err;
if ((err = crypto_register_alg(&ablk_cbc_alg)))
goto ablk_cbc_err;
#ifdef CONFIG_X86_64
if ((err = crypto_register_alg(&blk_ctr_alg)))
goto blk_ctr_err;
if ((err = crypto_register_alg(&ablk_ctr_alg)))
goto ablk_ctr_err;
if ((err = crypto_register_alg(&__rfc4106_alg)))
goto __aead_gcm_err;
if ((err = crypto_register_alg(&rfc4106_alg)))
goto aead_gcm_err;
#ifdef HAS_CTR
if ((err = crypto_register_alg(&ablk_rfc3686_ctr_alg)))
goto ablk_rfc3686_ctr_err;
#endif
#endif
#ifdef HAS_LRW
if ((err = crypto_register_alg(&ablk_lrw_alg)))
goto ablk_lrw_err;
#endif
#ifdef HAS_PCBC
if ((err = crypto_register_alg(&ablk_pcbc_alg)))
goto ablk_pcbc_err;
#endif
#ifdef HAS_XTS
if ((err = crypto_register_alg(&ablk_xts_alg)))
goto ablk_xts_err;
#endif
return err;
err = crypto_fpu_init();
if (err)
return err;
#ifdef HAS_XTS
ablk_xts_err:
#endif
#ifdef HAS_PCBC
crypto_unregister_alg(&ablk_pcbc_alg);
ablk_pcbc_err:
#endif
#ifdef HAS_LRW
crypto_unregister_alg(&ablk_lrw_alg);
ablk_lrw_err:
#endif
#ifdef CONFIG_X86_64
#ifdef HAS_CTR
crypto_unregister_alg(&ablk_rfc3686_ctr_alg);
ablk_rfc3686_ctr_err:
#endif
crypto_unregister_alg(&rfc4106_alg);
aead_gcm_err:
crypto_unregister_alg(&__rfc4106_alg);
__aead_gcm_err:
crypto_unregister_alg(&ablk_ctr_alg);
ablk_ctr_err:
crypto_unregister_alg(&blk_ctr_alg);
blk_ctr_err:
#endif
crypto_unregister_alg(&ablk_cbc_alg);
ablk_cbc_err:
crypto_unregister_alg(&ablk_ecb_alg);
ablk_ecb_err:
crypto_unregister_alg(&blk_cbc_alg);
blk_cbc_err:
crypto_unregister_alg(&blk_ecb_alg);
blk_ecb_err:
crypto_unregister_alg(&__aesni_alg);
__aes_err:
crypto_unregister_alg(&aesni_alg);
aes_err:
fpu_err:
return err;
for (i = 0; i < ARRAY_SIZE(aesni_algs); i++)
INIT_LIST_HEAD(&aesni_algs[i].cra_list);
return crypto_register_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
}
static void __exit aesni_exit(void)
{
#ifdef HAS_XTS
crypto_unregister_alg(&ablk_xts_alg);
#endif
#ifdef HAS_PCBC
crypto_unregister_alg(&ablk_pcbc_alg);
#endif
#ifdef HAS_LRW
crypto_unregister_alg(&ablk_lrw_alg);
#endif
#ifdef CONFIG_X86_64
#ifdef HAS_CTR
crypto_unregister_alg(&ablk_rfc3686_ctr_alg);
#endif
crypto_unregister_alg(&rfc4106_alg);
crypto_unregister_alg(&__rfc4106_alg);
crypto_unregister_alg(&ablk_ctr_alg);
crypto_unregister_alg(&blk_ctr_alg);
#endif
crypto_unregister_alg(&ablk_cbc_alg);
crypto_unregister_alg(&ablk_ecb_alg);
crypto_unregister_alg(&blk_cbc_alg);
crypto_unregister_alg(&blk_ecb_alg);
crypto_unregister_alg(&__aesni_alg);
crypto_unregister_alg(&aesni_alg);
crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
crypto_fpu_exit();
}

5
crypto/xor.c
View file

@ -129,9 +129,9 @@ calibrate_xor_blocks(void)
if (fastest) {
printk(KERN_INFO "xor: automatically using best "
"checksumming function: %s\n",
fastest->name);
"checksumming function:\n");
xor_speed(fastest);
goto out;
} else {
printk(KERN_INFO "xor: measuring software checksum speed\n");
XOR_TRY_TEMPLATES;
@ -146,6 +146,7 @@ calibrate_xor_blocks(void)
#undef xor_speed
out:
free_pages((unsigned long)b1, 2);
active_template = fastest;

2
drivers/char/hw_random/Kconfig
View file

@ -63,7 +63,7 @@ config HW_RANDOM_AMD
config HW_RANDOM_ATMEL
tristate "Atmel Random Number Generator support"
depends on HW_RANDOM && HAVE_CLK
default HW_RANDOM
default (HW_RANDOM && ARCH_AT91)
---help---
This driver provides kernel-side support for the Random Number
Generator hardware found on Atmel AT91 devices.

22
drivers/char/hw_random/omap-rng.c
View file

@ -115,22 +115,12 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENOENT;
goto err_region;
}
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
ret = -EBUSY;
goto err_region;
}
dev_set_drvdata(&pdev->dev, res);
rng_base = ioremap(res->start, resource_size(res));
rng_base = devm_request_and_ioremap(&pdev->dev, res);
if (!rng_base) {
ret = -ENOMEM;
goto err_ioremap;
}
dev_set_drvdata(&pdev->dev, res);
ret = hwrng_register(&omap_rng_ops);
if (ret)
@ -145,11 +135,8 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
return 0;
err_register:
iounmap(rng_base);
rng_base = NULL;
err_ioremap:
release_mem_region(res->start, resource_size(res));
err_region:
if (cpu_is_omap24xx()) {
clk_disable(rng_ick);
clk_put(rng_ick);
@ -159,20 +146,15 @@ err_region:
static int __exit omap_rng_remove(struct platform_device *pdev)
{
struct resource *res = dev_get_drvdata(&pdev->dev);
hwrng_unregister(&omap_rng_ops);
omap_rng_write_reg(RNG_MASK_REG, 0x0);
iounmap(rng_base);
if (cpu_is_omap24xx()) {
clk_disable(rng_ick);
clk_put(rng_ick);
}
release_mem_region(res->start, resource_size(res));
rng_base = NULL;
return 0;

11
drivers/crypto/Kconfig
View file

@ -314,4 +314,15 @@ config CRYPTO_DEV_NX
module supports acceleration for AES and SHA2 algorithms. If you
choose 'M' here, this module will be called nx_crypto.
config CRYPTO_DEV_UX500
tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
depends on ARCH_U8500
select CRYPTO_ALGAPI
help
Driver for ST-Ericsson UX500 crypto engine.
if CRYPTO_DEV_UX500
source "drivers/crypto/ux500/Kconfig"
endif # if CRYPTO_DEV_UX500
endif # CRYPTO_HW

1
drivers/crypto/Makefile
View file

@ -14,3 +14,4 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/

2
drivers/crypto/amcc/crypto4xx_core.c
View file

@ -1244,9 +1244,9 @@ err_start_dev:
iounmap(core_dev->dev->ce_base);
err_iomap:
free_irq(core_dev->irq, dev);
err_request_irq:
irq_dispose_mapping(core_dev->irq);
tasklet_kill(&core_dev->tasklet);
err_request_irq:
crypto4xx_destroy_sdr(core_dev->dev);
err_build_sdr:
crypto4xx_destroy_gdr(core_dev->dev);

14
drivers/crypto/caam/caamalg.c
View file

@ -2267,8 +2267,11 @@ static void __exit caam_algapi_exit(void)
int i, err;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node)
return;
if (!dev_node) {
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
if (!dev_node)
return;
}
pdev = of_find_device_by_node(dev_node);
if (!pdev)
@ -2350,8 +2353,11 @@ static int __init caam_algapi_init(void)
int i = 0, err = 0;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node)
return -ENODEV;
if (!dev_node) {
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
if (!dev_node)
return -ENODEV;
}
pdev = of_find_device_by_node(dev_node);
if (!pdev)

16
drivers/crypto/caam/ctrl.c
View file

@ -98,6 +98,12 @@ static int caam_probe(struct platform_device *pdev)
rspec = 0;
for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
rspec++;
if (!rspec) {
/* for backward compatible with device trees */
for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
rspec++;
}
ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL);
if (ctrlpriv->jrdev == NULL) {
iounmap(&topregs->ctrl);
@ -111,6 +117,13 @@ static int caam_probe(struct platform_device *pdev)
ctrlpriv->total_jobrs++;
ring++;
}
if (!ring) {
for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
caam_jr_probe(pdev, np, ring);
ctrlpriv->total_jobrs++;
ring++;
}
}
/* Check to see if QI present. If so, enable */
ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
@ -226,6 +239,9 @@ static struct of_device_id caam_match[] = {
{
.compatible = "fsl,sec-v4.0",
},
{
.compatible = "fsl,sec4.0",
},
{},
};
MODULE_DEVICE_TABLE(of, caam_match);

30
drivers/crypto/ux500/Kconfig Normal file
View file

@ -0,0 +1,30 @@
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
config CRYPTO_DEV_UX500_CRYP
tristate "UX500 crypto driver for CRYP block"
depends on CRYPTO_DEV_UX500
select CRYPTO_DES
help
This selects the crypto driver for the UX500_CRYP hardware. It supports
AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
config CRYPTO_DEV_UX500_HASH
tristate "UX500 crypto driver for HASH block"
depends on CRYPTO_DEV_UX500
select CRYPTO_HASH
select CRYPTO_HMAC
help
This selects the hash driver for the UX500_HASH hardware.
Depends on UX500/STM DMA if running in DMA mode.
config CRYPTO_DEV_UX500_DEBUG
bool "Activate ux500 platform debug-mode for crypto and hash block"
depends on CRYPTO_DEV_UX500_CRYP || CRYPTO_DEV_UX500_HASH
default n
help
Say Y if you want to add debug prints to ux500_hash and
ux500_cryp devices.

8
drivers/crypto/ux500/Makefile Normal file
View file

@ -0,0 +1,8 @@
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += hash/
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += cryp/

13
drivers/crypto/ux500/cryp/Makefile Normal file
View file

@ -0,0 +1,13 @@
#/*
# * Copyright (C) ST-Ericsson SA 2010
# * Author: shujuan.chen@stericsson.com for ST-Ericsson.
# * License terms: GNU General Public License (GPL) version 2 */
ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
CFLAGS_cryp_core.o := -DDEBUG -O0
CFLAGS_cryp.o := -DDEBUG -O0
CFLAGS_cryp_irq.o := -DDEBUG -O0
endif
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += ux500_cryp.o
ux500_cryp-objs := cryp.o cryp_irq.o cryp_core.o

389
drivers/crypto/ux500/cryp/cryp.c Normal file
View file

@ -0,0 +1,389 @@
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <mach/hardware.h>
#include "cryp_p.h"
#include "cryp.h"
/**
* cryp_wait_until_done - wait until the device logic is not busy
*/
void cryp_wait_until_done(struct cryp_device_data *device_data)
{
while (cryp_is_logic_busy(device_data))
cpu_relax();
}
/**
* cryp_check - This routine checks Peripheral and PCell Id
* @device_data: Pointer to the device data struct for base address.
*/
int cryp_check(struct cryp_device_data *device_data)
{
int peripheralid2 = 0;
if (NULL == device_data)
return -EINVAL;
peripheralid2 = readl_relaxed(&device_data->base->periphId2);
if (peripheralid2 != CRYP_PERIPHERAL_ID2_DB8500)
return -EPERM;
/* Check Peripheral and Pcell Id Register for CRYP */
if ((CRYP_PERIPHERAL_ID0 ==
readl_relaxed(&device_data->base->periphId0))
&& (CRYP_PERIPHERAL_ID1 ==
readl_relaxed(&device_data->base->periphId1))
&& (CRYP_PERIPHERAL_ID3 ==
readl_relaxed(&device_data->base->periphId3))
&& (CRYP_PCELL_ID0 ==
readl_relaxed(&device_data->base->pcellId0))
&& (CRYP_PCELL_ID1 ==
readl_relaxed(&device_data->base->pcellId1))
&& (CRYP_PCELL_ID2 ==
readl_relaxed(&device_data->base->pcellId2))
&& (CRYP_PCELL_ID3 ==
readl_relaxed(&device_data->base->pcellId3))) {
return 0;
}
return -EPERM;
}
/**
* cryp_activity - This routine enables/disable the cryptography function.
* @device_data: Pointer to the device data struct for base address.
* @cryp_crypen: Enable/Disable functionality
*/
void cryp_activity(struct cryp_device_data *device_data,
enum cryp_crypen cryp_crypen)
{
CRYP_PUT_BITS(&device_data->base->cr,
cryp_crypen,
CRYP_CR_CRYPEN_POS,
CRYP_CR_CRYPEN_MASK);
}
/**
* cryp_flush_inoutfifo - Resets both the input and the output FIFOs
* @device_data: Pointer to the device data struct for base address.
*/
void cryp_flush_inoutfifo(struct cryp_device_data *device_data)
{
/*
* We always need to disble the hardware before trying to flush the
* FIFO. This is something that isn't written in the design
* specification, but we have been informed by the hardware designers
* that this must be done.
*/
cryp_activity(device_data, CRYP_CRYPEN_DISABLE);
cryp_wait_until_done(device_data);
CRYP_SET_BITS(&device_data->base->cr, CRYP_CR_FFLUSH_MASK);
/*
* CRYP_SR_INFIFO_READY_MASK is the expected value on the status
* register when starting a new calculation, which means Input FIFO is
* not full and input FIFO is empty.
*/
while (readl_relaxed(&device_data->base->sr) !=
CRYP_SR_INFIFO_READY_MASK)
cpu_relax();
}
/**
* cryp_set_configuration - This routine set the cr CRYP IP
* @device_data: Pointer to the device data struct for base address.
* @cryp_config: Pointer to the configuration parameter
* @control_register: The control register to be written later on.
*/
int cryp_set_configuration(struct cryp_device_data *device_data,
struct cryp_config *cryp_config,
u32 *control_register)
{
u32 cr_for_kse;
if (NULL == device_data || NULL == cryp_config)
return -EINVAL;
*control_register |= (cryp_config->keysize << CRYP_CR_KEYSIZE_POS);
/* Prepare key for decryption in AES_ECB and AES_CBC mode. */
if ((CRYP_ALGORITHM_DECRYPT == cryp_config->algodir) &&
((CRYP_ALGO_AES_ECB == cryp_config->algomode) ||
(CRYP_ALGO_AES_CBC == cryp_config->algomode))) {
cr_for_kse = *control_register;
/*
* This seems a bit odd, but it is indeed needed to set this to
* encrypt even though it is a decryption that we are doing. It
* also mentioned in the design spec that you need to do this.
* After the keyprepartion for decrypting is done you should set
* algodir back to decryption, which is done outside this if
* statement.
*
* According to design specification we should set mode ECB
* during key preparation even though we might be running CBC
* when enter this function.
*
* Writing to KSE_ENABLED will drop CRYPEN when key preparation
* is done. Therefore we need to set CRYPEN again outside this
* if statement when running decryption.
*/
cr_for_kse |= ((CRYP_ALGORITHM_ENCRYPT << CRYP_CR_ALGODIR_POS) |
(CRYP_ALGO_AES_ECB << CRYP_CR_ALGOMODE_POS) |
(CRYP_CRYPEN_ENABLE << CRYP_CR_CRYPEN_POS) |
(KSE_ENABLED << CRYP_CR_KSE_POS));
writel_relaxed(cr_for_kse, &device_data->base->cr);
cryp_wait_until_done(device_data);
}
*control_register |=
((cryp_config->algomode << CRYP_CR_ALGOMODE_POS) |
(cryp_config->algodir << CRYP_CR_ALGODIR_POS));
return 0;
}
/**
* cryp_configure_protection - set the protection bits in the CRYP logic.
* @device_data: Pointer to the device data struct for base address.
* @p_protect_config: Pointer to the protection mode and
* secure mode configuration
*/
int cryp_configure_protection(struct cryp_device_data *device_data,
struct cryp_protection_config *p_protect_config)
{
if (NULL == p_protect_config)
return -EINVAL;
CRYP_WRITE_BIT(&device_data->base->cr,
(u32) p_protect_config->secure_access,
CRYP_CR_SECURE_MASK);
CRYP_PUT_BITS(&device_data->base->cr,
p_protect_config->privilege_access,
CRYP_CR_PRLG_POS,
CRYP_CR_PRLG_MASK);
return 0;
}
/**
* cryp_is_logic_busy - returns the busy status of the CRYP logic
* @device_data: Pointer to the device data struct for base address.
*/
int cryp_is_logic_busy(struct cryp_device_data *device_data)
{
return CRYP_TEST_BITS(&device_data->base->sr,
CRYP_SR_BUSY_MASK);
}
/**
* cryp_configure_for_dma - configures the CRYP IP for DMA operation
* @device_data: Pointer to the device data struct for base address.
* @dma_req: Specifies the DMA request type value.
*/
void cryp_configure_for_dma(struct cryp_device_data *device_data,
enum cryp_dma_req_type dma_req)
{
CRYP_SET_BITS(&device_data->base->dmacr,
(u32) dma_req);
}
/**
* cryp_configure_key_values - configures the key values for CRYP operations
* @device_data: Pointer to the device data struct for base address.
* @key_reg_index: Key value index register
* @key_value: The key value struct
*/
int cryp_configure_key_values(struct cryp_device_data *device_data,
enum cryp_key_reg_index key_reg_index,
struct cryp_key_value key_value)
{
while (cryp_is_logic_busy(device_data))
cpu_relax();
switch (key_reg_index) {
case CRYP_KEY_REG_1:
writel_relaxed(key_value.key_value_left,
&device_data->base->key_1_l);
writel_relaxed(key_value.key_value_right,
&device_data->base->key_1_r);
break;
case CRYP_KEY_REG_2:
writel_relaxed(key_value.key_value_left,
&device_data->base->key_2_l);
writel_relaxed(key_value.key_value_right,
&device_data->base->key_2_r);
break;
case CRYP_KEY_REG_3:
writel_relaxed(key_value.key_value_left,
&device_data->base->key_3_l);
writel_relaxed(key_value.key_value_right,
&device_data->base->key_3_r);
break;
case CRYP_KEY_REG_4:
writel_relaxed(key_value.key_value_left,
&device_data->base->key_4_l);
writel_relaxed(key_value.key_value_right,
&device_data->base->key_4_r);
break;
default:
return -EINVAL;
}
return 0;
}
/**
* cryp_configure_init_vector - configures the initialization vector register
* @device_data: Pointer to the device data struct for base address.
* @init_vector_index: Specifies the index of the init vector.
* @init_vector_value: Specifies the value for the init vector.
*/
int cryp_configure_init_vector(struct cryp_device_data *device_data,
enum cryp_init_vector_index
init_vector_index,
struct cryp_init_vector_value
init_vector_value)
{
while (cryp_is_logic_busy(device_data))
cpu_relax();
switch (init_vector_index) {
case CRYP_INIT_VECTOR_INDEX_0:
writel_relaxed(init_vector_value.init_value_left,
&device_data->base->init_vect_0_l);
writel_relaxed(init_vector_value.init_value_right,
&device_data->base->init_vect_0_r);
break;
case CRYP_INIT_VECTOR_INDEX_1:
writel_relaxed(init_vector_value.init_value_left,
&device_data->base->init_vect_1_l);
writel_relaxed(init_vector_value.init_value_right,
&device_data->base->init_vect_1_r);
break;
default:
return -EINVAL;
}
return 0;
}
/**
* cryp_save_device_context - Store hardware registers and
* other device context parameter
* @device_data: Pointer to the device data struct for base address.
* @ctx: Crypto device context
*/
void cryp_save_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx,
int cryp_mode)
{
enum cryp_algo_mode algomode;
struct cryp_register *src_reg = device_data->base;
struct cryp_config *config =
(struct cryp_config *)device_data->current_ctx;
/*
* Always start by disable the hardware and wait for it to finish the
* ongoing calculations before trying to reprogram it.
*/
cryp_activity(device_data, CRYP_CRYPEN_DISABLE);
cryp_wait_until_done(device_data);
if (cryp_mode == CRYP_MODE_DMA)
cryp_configure_for_dma(device_data, CRYP_DMA_DISABLE_BOTH);
if (CRYP_TEST_BITS(&src_reg->sr, CRYP_SR_IFEM_MASK) == 0)
ctx->din = readl_relaxed(&src_reg->din);
ctx->cr = readl_relaxed(&src_reg->cr) & CRYP_CR_CONTEXT_SAVE_MASK;
switch (config->keysize) {
case CRYP_KEY_SIZE_256:
ctx->key_4_l = readl_relaxed(&src_reg->key_4_l);
ctx->key_4_r = readl_relaxed(&src_reg->key_4_r);
case CRYP_KEY_SIZE_192:
ctx->key_3_l = readl_relaxed(&src_reg->key_3_l);
ctx->key_3_r = readl_relaxed(&src_reg->key_3_r);
case CRYP_KEY_SIZE_128:
ctx->key_2_l = readl_relaxed(&src_reg->key_2_l);
ctx->key_2_r = readl_relaxed(&src_reg->key_2_r);
default:
ctx->key_1_l = readl_relaxed(&src_reg->key_1_l);
ctx->key_1_r = readl_relaxed(&src_reg->key_1_r);
}
/* Save IV for CBC mode for both AES and DES. */
algomode = ((ctx->cr & CRYP_CR_ALGOMODE_MASK) >> CRYP_CR_ALGOMODE_POS);
if (algomode == CRYP_ALGO_TDES_CBC ||
algomode == CRYP_ALGO_DES_CBC ||
algomode == CRYP_ALGO_AES_CBC) {
ctx->init_vect_0_l = readl_relaxed(&src_reg->init_vect_0_l);
ctx->init_vect_0_r = readl_relaxed(&src_reg->init_vect_0_r);
ctx->init_vect_1_l = readl_relaxed(&src_reg->init_vect_1_l);
ctx->init_vect_1_r = readl_relaxed(&src_reg->init_vect_1_r);
}
}
/**
* cryp_restore_device_context - Restore hardware registers and
* other device context parameter
* @device_data: Pointer to the device data struct for base address.
* @ctx: Crypto device context
*/
void cryp_restore_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx)
{
struct cryp_register *reg = device_data->base;
struct cryp_config *config =
(struct cryp_config *)device_data->current_ctx;
/*
* Fall through for all items in switch statement. DES is captured in
* the default.
*/
switch (config->keysize) {
case CRYP_KEY_SIZE_256:
writel_relaxed(ctx->key_4_l, &reg->key_4_l);
writel_relaxed(ctx->key_4_r, &reg->key_4_r);
case CRYP_KEY_SIZE_192:
writel_relaxed(ctx->key_3_l, &reg->key_3_l);
writel_relaxed(ctx->key_3_r, &reg->key_3_r);
case CRYP_KEY_SIZE_128:
writel_relaxed(ctx->key_2_l, &reg->key_2_l);
writel_relaxed(ctx->key_2_r, &reg->key_2_r);
default:
writel_relaxed(ctx->key_1_l, &reg->key_1_l);
writel_relaxed(ctx->key_1_r, &reg->key_1_r);
}
/* Restore IV for CBC mode for AES and DES. */
if (config->algomode == CRYP_ALGO_TDES_CBC ||
config->algomode == CRYP_ALGO_DES_CBC ||
config->algomode == CRYP_ALGO_AES_CBC) {
writel_relaxed(ctx->init_vect_0_l, &reg->init_vect_0_l);
writel_relaxed(ctx->init_vect_0_r, &reg->init_vect_0_r);
writel_relaxed(ctx->init_vect_1_l, &reg->init_vect_1_l);
writel_relaxed(ctx->init_vect_1_r, &reg->init_vect_1_r);
}
}

308
drivers/crypto/ux500/cryp/cryp.h Normal file
View file

@ -0,0 +1,308 @@
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_H_
#define _CRYP_H_
#include <linux/completion.h>
#include <linux/dmaengine.h>
#include <linux/klist.h>
#include <linux/mutex.h>
#define DEV_DBG_NAME "crypX crypX:"
/* CRYP enable/disable */
enum cryp_crypen {
CRYP_CRYPEN_DISABLE = 0,
CRYP_CRYPEN_ENABLE = 1
};
/* CRYP Start Computation enable/disable */
enum cryp_start {
CRYP_START_DISABLE = 0,
CRYP_START_ENABLE = 1
};
/* CRYP Init Signal enable/disable */
enum cryp_init {
CRYP_INIT_DISABLE = 0,
CRYP_INIT_ENABLE = 1
};
/* Cryp State enable/disable */
enum cryp_state {
CRYP_STATE_DISABLE = 0,
CRYP_STATE_ENABLE = 1
};
/* Key preparation bit enable */
enum cryp_key_prep {
KSE_DISABLED = 0,
KSE_ENABLED = 1
};
/* Key size for AES */
#define CRYP_KEY_SIZE_128 (0)
#define CRYP_KEY_SIZE_192 (1)
#define CRYP_KEY_SIZE_256 (2)
/* AES modes */
enum cryp_algo_mode {
CRYP_ALGO_TDES_ECB,
CRYP_ALGO_TDES_CBC,
CRYP_ALGO_DES_ECB,
CRYP_ALGO_DES_CBC,
CRYP_ALGO_AES_ECB,
CRYP_ALGO_AES_CBC,
CRYP_ALGO_AES_CTR,
CRYP_ALGO_AES_XTS
};
/* Cryp Encryption or Decryption */
enum cryp_algorithm_dir {
CRYP_ALGORITHM_ENCRYPT,
CRYP_ALGORITHM_DECRYPT
};
/* Hardware access method */
enum cryp_mode {
CRYP_MODE_POLLING,
CRYP_MODE_INTERRUPT,
CRYP_MODE_DMA
};
/**
* struct cryp_config -
* @keysize: Key size for AES
* @algomode: AES modes
* @algodir: Cryp Encryption or Decryption
*
* CRYP configuration structure to be passed to set configuration
*/
struct cryp_config {
int keysize;
enum cryp_algo_mode algomode;
enum cryp_algorithm_dir algodir;
};
/**
* struct cryp_protection_config -
* @privilege_access: Privileged cryp state enable/disable
* @secure_access: Secure cryp state enable/disable
*
* Protection configuration structure for setting privilage access
*/
struct cryp_protection_config {
enum cryp_state privilege_access;
enum cryp_state secure_access;
};
/* Cryp status */
enum cryp_status_id {
CRYP_STATUS_BUSY = 0x10,
CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
};
/* Cryp DMA interface */
enum cryp_dma_req_type {
CRYP_DMA_DISABLE_BOTH,
CRYP_DMA_ENABLE_IN_DATA,
CRYP_DMA_ENABLE_OUT_DATA,
CRYP_DMA_ENABLE_BOTH_DIRECTIONS
};
enum cryp_dma_channel {
CRYP_DMA_RX = 0,
CRYP_DMA_TX
};
/* Key registers */
enum cryp_key_reg_index {
CRYP_KEY_REG_1,
CRYP_KEY_REG_2,
CRYP_KEY_REG_3,
CRYP_KEY_REG_4
};
/* Key register left and right */
struct cryp_key_value {
u32 key_value_left;
u32 key_value_right;
};
/* Cryp Initialization structure */
enum cryp_init_vector_index {
CRYP_INIT_VECTOR_INDEX_0,
CRYP_INIT_VECTOR_INDEX_1
};
/* struct cryp_init_vector_value -
* @init_value_left
* @init_value_right
* */
struct cryp_init_vector_value {
u32 init_value_left;
u32 init_value_right;
};
/**
* struct cryp_device_context - structure for a cryp context.
* @cr: control register
* @dmacr: DMA control register
* @imsc: Interrupt mask set/clear register
* @key_1_l: Key 1l register
* @key_1_r: Key 1r register
* @key_2_l: Key 2l register
* @key_2_r: Key 2r register
* @key_3_l: Key 3l register
* @key_3_r: Key 3r register
* @key_4_l: Key 4l register
* @key_4_r: Key 4r register
* @init_vect_0_l: Initialization vector 0l register
* @init_vect_0_r: Initialization vector 0r register
* @init_vect_1_l: Initialization vector 1l register
* @init_vect_1_r: Initialization vector 0r register
* @din: Data in register
* @dout: Data out register
*
* CRYP power management specifc structure.
*/
struct cryp_device_context {
u32 cr;
u32 dmacr;
u32 imsc;
u32 key_1_l;
u32 key_1_r;
u32 key_2_l;
u32 key_2_r;
u32 key_3_l;
u32 key_3_r;
u32 key_4_l;
u32 key_4_r;
u32 init_vect_0_l;
u32 init_vect_0_r;
u32 init_vect_1_l;
u32 init_vect_1_r;
u32 din;
u32 dout;
};
struct cryp_dma {
dma_cap_mask_t mask;
struct completion cryp_dma_complete;
struct dma_chan *chan_cryp2mem;
struct dma_chan *chan_mem2cryp;
struct stedma40_chan_cfg *cfg_cryp2mem;
struct stedma40_chan_cfg *cfg_mem2cryp;
int sg_src_len;
int sg_dst_len;
struct scatterlist *sg_src;
struct scatterlist *sg_dst;
int nents_src;
int nents_dst;
};
/**
* struct cryp_device_data - structure for a cryp device.
* @base: Pointer to the hardware base address.
* @dev: Pointer to the devices dev structure.
* @clk: Pointer to the device's clock control.
* @pwr_regulator: Pointer to the device's power control.
* @power_status: Current status of the power.
* @ctx_lock: Lock for current_ctx.
* @current_ctx: Pointer to the currently allocated context.
* @list_node: For inclusion into a klist.
* @dma: The dma structure holding channel configuration.
* @power_state: TRUE = power state on, FALSE = power state off.
* @power_state_spinlock: Spinlock for power_state.
* @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
*/
struct cryp_device_data {
struct cryp_register __iomem *base;
struct device *dev;
struct clk *clk;
struct regulator *pwr_regulator;
int power_status;
struct spinlock ctx_lock;
struct cryp_ctx *current_ctx;
struct klist_node list_node;
struct cryp_dma dma;
bool power_state;
struct spinlock power_state_spinlock;
bool restore_dev_ctx;
};
void cryp_wait_until_done(struct cryp_device_data *device_data);
/* Initialization functions */
int cryp_check(struct cryp_device_data *device_data);
void cryp_activity(struct cryp_device_data *device_data,
enum cryp_crypen cryp_crypen);
void cryp_flush_inoutfifo(struct cryp_device_data *device_data);
int cryp_set_configuration(struct cryp_device_data *device_data,
struct cryp_config *cryp_config,
u32 *control_register);
void cryp_configure_for_dma(struct cryp_device_data *device_data,
enum cryp_dma_req_type dma_req);
int cryp_configure_key_values(struct cryp_device_data *device_data,
enum cryp_key_reg_index key_reg_index,
struct cryp_key_value key_value);
int cryp_configure_init_vector(struct cryp_device_data *device_data,
enum cryp_init_vector_index
init_vector_index,
struct cryp_init_vector_value
init_vector_value);
int cryp_configure_protection(struct cryp_device_data *device_data,
struct cryp_protection_config *p_protect_config);
/* Power management funtions */
void cryp_save_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx,
int cryp_mode);
void cryp_restore_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx);
/* Data transfer and status bits. */
int cryp_is_logic_busy(struct cryp_device_data *device_data);
int cryp_get_status(struct cryp_device_data *device_data);
/**
* cryp_write_indata - This routine writes 32 bit data into the data input
* register of the cryptography IP.
* @device_data: Pointer to the device data struct for base address.
* @write_data: Data to write.
*/
int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);
/**
* cryp_read_outdata - This routine reads the data from the data output
* register of the CRYP logic
* @device_data: Pointer to the device data struct for base address.
* @read_data: Read the data from the output FIFO.
*/
int cryp_read_outdata(struct cryp_device_data *device_data, u32 *read_data);
#endif /* _CRYP_H_ */

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/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2.
*/
#include <linux/kernel.h>
#include <linux/bitmap.h>
#include <linux/device.h>
#include "cryp.h"
#include "cryp_p.h"
#include "cryp_irq.h"
#include "cryp_irqp.h"
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i | irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i & ~irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
return (readl_relaxed(&device_data->base->mis) & irq_src) > 0;
}

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/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_IRQ_H_
#define _CRYP_IRQ_H_
#include "cryp.h"
enum cryp_irq_src_id {
CRYP_IRQ_SRC_INPUT_FIFO = 0x1,
CRYP_IRQ_SRC_OUTPUT_FIFO = 0x2,
CRYP_IRQ_SRC_ALL = 0x3
};
/**
* M0 Funtions
*/
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src);
#endif /* _CRYP_IRQ_H_ */

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/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __CRYP_IRQP_H_
#define __CRYP_IRQP_H_
#include "cryp_irq.h"
/**
*
* CRYP Registers - Offset mapping
* +-----------------+
* 00h | CRYP_CR | Configuration register
* +-----------------+
* 04h | CRYP_SR | Status register
* +-----------------+
* 08h | CRYP_DIN | Data In register
* +-----------------+
* 0ch | CRYP_DOUT | Data out register
* +-----------------+
* 10h | CRYP_DMACR | DMA control register
* +-----------------+
* 14h | CRYP_IMSC | IMSC
* +-----------------+
* 18h | CRYP_RIS | Raw interrupt status
* +-----------------+
* 1ch | CRYP_MIS | Masked interrupt status.
* +-----------------+
* Key registers
* IVR registers
* Peripheral
* Cell IDs
*
* Refer data structure for other register map
*/
/**
* struct cryp_register
* @cr - Configuration register
* @status - Status register
* @din - Data input register
* @din_size - Data input size register
* @dout - Data output register
* @dout_size - Data output size register
* @dmacr - Dma control register
* @imsc - Interrupt mask set/clear register
* @ris - Raw interrupt status
* @mis - Masked interrupt statu register
* @key_1_l - Key register 1 L
* @key_1_r - Key register 1 R
* @key_2_l - Key register 2 L
* @key_2_r - Key register 2 R
* @key_3_l - Key register 3 L
* @key_3_r - Key register 3 R
* @key_4_l - Key register 4 L
* @key_4_r - Key register 4 R
* @init_vect_0_l - init vector 0 L
* @init_vect_0_r - init vector 0 R
* @init_vect_1_l - init vector 1 L
* @init_vect_1_r - init vector 1 R
* @cryp_unused1 - unused registers
* @itcr - Integration test control register
* @itip - Integration test input register
* @itop - Integration test output register
* @cryp_unused2 - unused registers
* @periphId0 - FE0 CRYP Peripheral Identication Register
* @periphId1 - FE4
* @periphId2 - FE8
* @periphId3 - FEC
* @pcellId0 - FF0 CRYP PCell Identication Register
* @pcellId1 - FF4
* @pcellId2 - FF8
* @pcellId3 - FFC
*/
struct cryp_register {
u32 cr; /* Configuration register */
u32 sr; /* Status register */
u32 din; /* Data input register */
u32 din_size; /* Data input size register */
u32 dout; /* Data output register */
u32 dout_size; /* Data output size register */
u32 dmacr; /* Dma control register */
u32 imsc; /* Interrupt mask set/clear register */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt statu register */
u32 key_1_l; /*Key register 1 L */
u32 key_1_r; /*Key register 1 R */
u32 key_2_l; /*Key register 2 L */
u32 key_2_r; /*Key register 2 R */
u32 key_3_l; /*Key register 3 L */
u32 key_3_r; /*Key register 3 R */
u32 key_4_l; /*Key register 4 L */
u32 key_4_r; /*Key register 4 R */
u32 init_vect_0_l; /*init vector 0 L */
u32 init_vect_0_r; /*init vector 0 R */
u32 init_vect_1_l; /*init vector 1 L */
u32 init_vect_1_r; /*init vector 1 R */
u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */
u32 itcr; /*Integration test control register */
u32 itip; /*Integration test input register */
u32 itop; /*Integration test output register */
u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */
u32 periphId0; /* FE0 CRYP Peripheral Identication Register */
u32 periphId1; /* FE4 */
u32 periphId2; /* FE8 */
u32 periphId3; /* FEC */
u32 pcellId0; /* FF0 CRYP PCell Identication Register */
u32 pcellId1; /* FF4 */
u32 pcellId2; /* FF8 */
u32 pcellId3; /* FFC */
};
#endif

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/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_P_H_
#define _CRYP_P_H_
#include <linux/io.h>
#include <linux/bitops.h>
#include "cryp.h"
#include "cryp_irqp.h"
/**
* Generic Macros
*/
#define CRYP_SET_BITS(reg_name, mask) \
writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
#define CRYP_WRITE_BIT(reg_name, val, mask) \
writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
((val) & (mask))), reg_name)
#define CRYP_TEST_BITS(reg_name, val) \
(readl_relaxed(reg_name) & (val))
#define CRYP_PUT_BITS(reg, val, shift, mask) \
writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
(((u32)val << shift) & (mask))), reg)
/**
* CRYP specific Macros
*/
#define CRYP_PERIPHERAL_ID0 0xE3
#define CRYP_PERIPHERAL_ID1 0x05
#define CRYP_PERIPHERAL_ID2_DB8500 0x28
#define CRYP_PERIPHERAL_ID3 0x00
#define CRYP_PCELL_ID0 0x0D
#define CRYP_PCELL_ID1 0xF0
#define CRYP_PCELL_ID2 0x05
#define CRYP_PCELL_ID3 0xB1
/**
* CRYP register default values
*/
#define MAX_DEVICE_SUPPORT 2
/* Priv set, keyrden set and datatype 8bits swapped set as default. */
#define CRYP_CR_DEFAULT 0x0482
#define CRYP_DMACR_DEFAULT 0x0
#define CRYP_IMSC_DEFAULT 0x0
#define CRYP_DIN_DEFAULT 0x0
#define CRYP_DOUT_DEFAULT 0x0
#define CRYP_KEY_DEFAULT 0x0
#define CRYP_INIT_VECT_DEFAULT 0x0
/**
* CRYP Control register specific mask
*/
#define CRYP_CR_SECURE_MASK BIT(0)
#define CRYP_CR_PRLG_MASK BIT(1)
#define CRYP_CR_ALGODIR_MASK BIT(2)
#define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3))
#define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6))
#define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8))
#define CRYP_CR_KEYRDEN_MASK BIT(10)
#define CRYP_CR_KSE_MASK BIT(11)
#define CRYP_CR_START_MASK BIT(12)
#define CRYP_CR_INIT_MASK BIT(13)
#define CRYP_CR_FFLUSH_MASK BIT(14)
#define CRYP_CR_CRYPEN_MASK BIT(15)
#define CRYP_CR_CONTEXT_SAVE_MASK (CRYP_CR_SECURE_MASK |\
CRYP_CR_PRLG_MASK |\
CRYP_CR_ALGODIR_MASK |\
CRYP_CR_ALGOMODE_MASK |\
CRYP_CR_DATATYPE_MASK |\
CRYP_CR_KEYSIZE_MASK |\
CRYP_CR_KEYRDEN_MASK |\
CRYP_CR_DATATYPE_MASK)
#define CRYP_SR_INFIFO_READY_MASK (BIT(0) | BIT(1))
#define CRYP_SR_IFEM_MASK BIT(0)
#define CRYP_SR_BUSY_MASK BIT(4)
/**
* Bit position used while setting bits in register
*/
#define CRYP_CR_PRLG_POS 1
#define CRYP_CR_ALGODIR_POS 2
#define CRYP_CR_ALGOMODE_POS 3
#define CRYP_CR_DATATYPE_POS 6
#define CRYP_CR_KEYSIZE_POS 8
#define CRYP_CR_KEYRDEN_POS 10
#define CRYP_CR_KSE_POS 11
#define CRYP_CR_START_POS 12
#define CRYP_CR_INIT_POS 13
#define CRYP_CR_CRYPEN_POS 15
#define CRYP_SR_BUSY_POS 4
/**
* CRYP PCRs------PC_NAND control register
* BIT_MASK
*/
#define CRYP_DMA_REQ_MASK (BIT(1) | BIT(0))
#define CRYP_DMA_REQ_MASK_POS 0
struct cryp_system_context {
/* CRYP Register structure */
struct cryp_register *p_cryp_reg[MAX_DEVICE_SUPPORT];
};
#endif

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#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
CFLAGS_hash_core.o := -DDEBUG -O0
endif
obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += ux500_hash.o
ux500_hash-objs := hash_core.o

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/*
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen (shujuan.chen@stericsson.com)
* Author: Joakim Bech (joakim.xx.bech@stericsson.com)
* Author: Berne Hebark (berne.hebark@stericsson.com))
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _HASH_ALG_H
#define _HASH_ALG_H
#include <linux/bitops.h>
#define HASH_BLOCK_SIZE 64
#define HASH_DMA_ALIGN_SIZE 4
#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
#define HASH_BYTES_PER_WORD 4
/* Maximum value of the length's high word */
#define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
/* Power on Reset values HASH registers */
#define HASH_RESET_CR_VALUE 0x0
#define HASH_RESET_STR_VALUE 0x0
/* Number of context swap registers */
#define HASH_CSR_COUNT 52
#define HASH_RESET_CSRX_REG_VALUE 0x0
#define HASH_RESET_CSFULL_REG_VALUE 0x0
#define HASH_RESET_CSDATAIN_REG_VALUE 0x0
#define HASH_RESET_INDEX_VAL 0x0
#define HASH_RESET_BIT_INDEX_VAL 0x0
#define HASH_RESET_BUFFER_VAL 0x0
#define HASH_RESET_LEN_HIGH_VAL 0x0
#define HASH_RESET_LEN_LOW_VAL 0x0
/* Control register bitfields */
#define HASH_CR_RESUME_MASK 0x11FCF
#define HASH_CR_SWITCHON_POS 31
#define HASH_CR_SWITCHON_MASK BIT(31)
#define HASH_CR_EMPTYMSG_POS 20
#define HASH_CR_EMPTYMSG_MASK BIT(20)
#define HASH_CR_DINF_POS 12
#define HASH_CR_DINF_MASK BIT(12)
#define HASH_CR_NBW_POS 8
#define HASH_CR_NBW_MASK 0x00000F00UL
#define HASH_CR_LKEY_POS 16
#define HASH_CR_LKEY_MASK BIT(16)
#define HASH_CR_ALGO_POS 7
#define HASH_CR_ALGO_MASK BIT(7)
#define HASH_CR_MODE_POS 6
#define HASH_CR_MODE_MASK BIT(6)
#define HASH_CR_DATAFORM_POS 4
#define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5))
#define HASH_CR_DMAE_POS 3
#define HASH_CR_DMAE_MASK BIT(3)
#define HASH_CR_INIT_POS 2
#define HASH_CR_INIT_MASK BIT(2)
#define HASH_CR_PRIVN_POS 1
#define HASH_CR_PRIVN_MASK BIT(1)
#define HASH_CR_SECN_POS 0
#define HASH_CR_SECN_MASK BIT(0)
/* Start register bitfields */
#define HASH_STR_DCAL_POS 8
#define HASH_STR_DCAL_MASK BIT(8)
#define HASH_STR_DEFAULT 0x0
#define HASH_STR_NBLW_POS 0
#define HASH_STR_NBLW_MASK 0x0000001FUL
#define HASH_NBLW_MAX_VAL 0x1F
/* PrimeCell IDs */
#define HASH_P_ID0 0xE0
#define HASH_P_ID1 0x05
#define HASH_P_ID2 0x38
#define HASH_P_ID3 0x00
#define HASH_CELL_ID0 0x0D
#define HASH_CELL_ID1 0xF0
#define HASH_CELL_ID2 0x05
#define HASH_CELL_ID3 0xB1
#define HASH_SET_BITS(reg_name, mask) \
writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
#define HASH_CLEAR_BITS(reg_name, mask) \
writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
#define HASH_PUT_BITS(reg, val, shift, mask) \
writel_relaxed(((readl(reg) & ~(mask)) | \
(((u32)val << shift) & (mask))), reg)
#define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len))
#define HASH_INITIALIZE \
HASH_PUT_BITS( \
&device_data->base->cr, \
0x01, HASH_CR_INIT_POS, \
HASH_CR_INIT_MASK)
#define HASH_SET_DATA_FORMAT(data_format) \
HASH_PUT_BITS( \
&device_data->base->cr, \
(u32) (data_format), HASH_CR_DATAFORM_POS, \
HASH_CR_DATAFORM_MASK)
#define HASH_SET_NBLW(val) \
HASH_PUT_BITS( \
&device_data->base->str, \
(u32) (val), HASH_STR_NBLW_POS, \
HASH_STR_NBLW_MASK)
#define HASH_SET_DCAL \
HASH_PUT_BITS( \
&device_data->base->str, \
0x01, HASH_STR_DCAL_POS, \
HASH_STR_DCAL_MASK)
/* Hardware access method */
enum hash_mode {
HASH_MODE_CPU,
HASH_MODE_DMA
};
/**
* struct uint64 - Structure to handle 64 bits integers.
* @high_word: Most significant bits.
* @low_word: Least significant bits.
*
* Used to handle 64 bits integers.
*/
struct uint64 {
u32 high_word;
u32 low_word;
};
/**
* struct hash_register - Contains all registers in ux500 hash hardware.
* @cr: HASH control register (0x000).
* @din: HASH data input register (0x004).
* @str: HASH start register (0x008).
* @hx: HASH digest register 0..7 (0x00c-0x01C).
* @padding0: Reserved (0x02C).
* @itcr: Integration test control register (0x080).
* @itip: Integration test input register (0x084).
* @itop: Integration test output register (0x088).
* @padding1: Reserved (0x08C).
* @csfull: HASH context full register (0x0F8).
* @csdatain: HASH context swap data input register (0x0FC).
* @csrx: HASH context swap register 0..51 (0x100-0x1CC).
* @padding2: Reserved (0x1D0).
* @periphid0: HASH peripheral identification register 0 (0xFE0).
* @periphid1: HASH peripheral identification register 1 (0xFE4).
* @periphid2: HASH peripheral identification register 2 (0xFE8).
* @periphid3: HASH peripheral identification register 3 (0xFEC).
* @cellid0: HASH PCell identification register 0 (0xFF0).
* @cellid1: HASH PCell identification register 1 (0xFF4).
* @cellid2: HASH PCell identification register 2 (0xFF8).
* @cellid3: HASH PCell identification register 3 (0xFFC).
*
* The device communicates to the HASH via 32-bit-wide control registers
* accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure
* with the registers used.
*/
struct hash_register {
u32 cr;
u32 din;
u32 str;
u32 hx[8];
u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
u32 itcr;
u32 itip;
u32 itop;
u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
u32 csfull;
u32 csdatain;
u32 csrx[HASH_CSR_COUNT];
u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
u32 periphid0;
u32 periphid1;
u32 periphid2;
u32 periphid3;
u32 cellid0;
u32 cellid1;
u32 cellid2;
u32 cellid3;
};
/**
* struct hash_state - Hash context state.
* @temp_cr: Temporary HASH Control Register.
* @str_reg: HASH Start Register.
* @din_reg: HASH Data Input Register.
* @csr[52]: HASH Context Swap Registers 0-39.
* @csfull: HASH Context Swap Registers 40 ie Status flags.
* @csdatain: HASH Context Swap Registers 41 ie Input data.
* @buffer: Working buffer for messages going to the hardware.
* @length: Length of the part of message hashed so far (floor(N/64) * 64).
* @index: Valid number of bytes in buffer (N % 64).
* @bit_index: Valid number of bits in buffer (N % 8).
*
* This structure is used between context switches, i.e. when ongoing jobs are
* interupted with new jobs. When this happens we need to store intermediate
* results in software.
*
* WARNING: "index" is the member of the structure, to be sure that "buffer"
* is aligned on a 4-bytes boundary. This is highly implementation dependent
* and MUST be checked whenever this code is ported on new platforms.
*/
struct hash_state {
u32 temp_cr;
u32 str_reg;
u32 din_reg;
u32 csr[52];
u32 csfull;
u32 csdatain;
u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
struct uint64 length;
u8 index;
u8 bit_index;
};
/**
* enum hash_device_id - HASH device ID.
* @HASH_DEVICE_ID_0: Hash hardware with ID 0
* @HASH_DEVICE_ID_1: Hash hardware with ID 1
*/
enum hash_device_id {
HASH_DEVICE_ID_0 = 0,
HASH_DEVICE_ID_1 = 1
};
/**
* enum hash_data_format - HASH data format.
* @HASH_DATA_32_BITS: 32 bits data format
* @HASH_DATA_16_BITS: 16 bits data format
* @HASH_DATA_8_BITS: 8 bits data format.
* @HASH_DATA_1_BITS: 1 bit data format.
*/
enum hash_data_format {
HASH_DATA_32_BITS = 0x0,
HASH_DATA_16_BITS = 0x1,
HASH_DATA_8_BITS = 0x2,
HASH_DATA_1_BIT = 0x3
};
/**
* enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm.
* @HASH_ALGO_SHA1: Indicates that SHA1 is used.
* @HASH_ALGO_SHA2: Indicates that SHA2 (SHA256) is used.
*/
enum hash_algo {
HASH_ALGO_SHA1 = 0x0,
HASH_ALGO_SHA256 = 0x1
};
/**
* enum hash_op - Enumeration for selecting between HASH or HMAC mode.
* @HASH_OPER_MODE_HASH: Indicates usage of normal HASH mode.
* @HASH_OPER_MODE_HMAC: Indicates usage of HMAC.
*/
enum hash_op {
HASH_OPER_MODE_HASH = 0x0,
HASH_OPER_MODE_HMAC = 0x1
};
/**
* struct hash_config - Configuration data for the hardware.
* @data_format: Format of data entered into the hash data in register.
* @algorithm: Algorithm selection bit.
* @oper_mode: Operating mode selection bit.
*/
struct hash_config {
int data_format;
int algorithm;
int oper_mode;
};
/**
* struct hash_dma - Structure used for dma.
* @mask: DMA capabilities bitmap mask.
* @complete: Used to maintain state for a "completion".
* @chan_mem2hash: DMA channel.
* @cfg_mem2hash: DMA channel configuration.
* @sg_len: Scatterlist length.
* @sg: Scatterlist.
* @nents: Number of sg entries.
*/
struct hash_dma {
dma_cap_mask_t mask;
struct completion complete;
struct dma_chan *chan_mem2hash;
void *cfg_mem2hash;
int sg_len;
struct scatterlist *sg;
int nents;
};
/**
* struct hash_ctx - The context used for hash calculations.
* @key: The key used in the operation.
* @keylen: The length of the key.
* @state: The state of the current calculations.
* @config: The current configuration.
* @digestsize: The size of current digest.
* @device: Pointer to the device structure.
*/
struct hash_ctx {
u8 *key;
u32 keylen;
struct hash_config config;
int digestsize;
struct hash_device_data *device;
};
/**
* struct hash_ctx - The request context used for hash calculations.
* @state: The state of the current calculations.
* @dma_mode: Used in special cases (workaround), e.g. need to change to
* cpu mode, if not supported/working in dma mode.
* @updated: Indicates if hardware is initialized for new operations.
*/
struct hash_req_ctx {
struct hash_state state;
bool dma_mode;
u8 updated;
};
/**
* struct hash_device_data - structure for a hash device.
* @base: Pointer to the hardware base address.
* @list_node: For inclusion in klist.
* @dev: Pointer to the device dev structure.
* @ctx_lock: Spinlock for current_ctx.
* @current_ctx: Pointer to the currently allocated context.
* @power_state: TRUE = power state on, FALSE = power state off.
* @power_state_lock: Spinlock for power_state.
* @regulator: Pointer to the device's power control.
* @clk: Pointer to the device's clock control.
* @restore_dev_state: TRUE = saved state, FALSE = no saved state.
* @dma: Structure used for dma.
*/
struct hash_device_data {
struct hash_register __iomem *base;
struct klist_node list_node;
struct device *dev;
struct spinlock ctx_lock;
struct hash_ctx *current_ctx;
bool power_state;
struct spinlock power_state_lock;
struct regulator *regulator;
struct clk *clk;
bool restore_dev_state;
struct hash_state state; /* Used for saving and resuming state */
struct hash_dma dma;
};
int hash_check_hw(struct hash_device_data *device_data);
int hash_setconfiguration(struct hash_device_data *device_data,
struct hash_config *config);
void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
void hash_get_digest(struct hash_device_data *device_data,
u8 *digest, int algorithm);
int hash_hw_update(struct ahash_request *req);
int hash_save_state(struct hash_device_data *device_data,
struct hash_state *state);
int hash_resume_state(struct hash_device_data *device_data,
const struct hash_state *state);
#endif

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