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msm: acpuclock-8064: Add PVS tables for 1.7 GHz parts
Add all seven PVS bins. Change-Id: Ifa49a8e81f5fe2c478cf5ff7545c25c4f7430d6e Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
This commit is contained in:
Patrick Daly
Stephen Boyd
parent
08ced2f233
commit
1a722e1de8
1 changed files with 127 additions and 20 deletions
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@ -241,20 +241,127 @@ static struct acpu_level tbl_faster[] __initdata = {
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static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
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{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1250000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 962500 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1000000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1025000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1037500 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1087500 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1150000 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1175000 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1225000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 962500 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1012500 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1037500 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1050000 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1087500 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1112500 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1187500 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 925000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 937500 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1012500 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1037500 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1100000 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1137500 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1162500 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1000000 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1037500 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1062500 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1100000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1125000 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 950000 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 962500 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 975000 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1000000 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1037500 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1075000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1100000 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 987500 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1012500 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1050000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1075000 },
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{ 0, { 0 } }
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};
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static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 975000 },
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{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1000000 },
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{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1025000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1050000 },
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{ 0, { 0 } }
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};
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@ -398,12 +505,12 @@ static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
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[0][PVS_FASTER] = {tbl_faster, sizeof(tbl_faster), 25000 },
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[1][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][1] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][2] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][3] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][4] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][5] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][6] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
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[1][1] = { tbl_PVS1_1700MHz, sizeof(tbl_PVS1_1700MHz), 0 },
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[1][2] = { tbl_PVS2_1700MHz, sizeof(tbl_PVS2_1700MHz), 0 },
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[1][3] = { tbl_PVS3_1700MHz, sizeof(tbl_PVS3_1700MHz), 0 },
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[1][4] = { tbl_PVS4_1700MHz, sizeof(tbl_PVS4_1700MHz), 0 },
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[1][5] = { tbl_PVS5_1700MHz, sizeof(tbl_PVS5_1700MHz), 0 },
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[1][6] = { tbl_PVS6_1700MHz, sizeof(tbl_PVS6_1700MHz), 0 },
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[2][0] = { tbl_PVS0_2000MHz, sizeof(tbl_PVS0_2000MHz), 0 },
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[2][1] = { tbl_PVS1_2000MHz, sizeof(tbl_PVS1_2000MHz), 0 },
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