mirror of
https://github.com/followmsi/android_kernel_google_msm.git
synced 2024-11-06 23:17:41 +00:00
msm_fb: display: wait4vsync before set suspend flag
Since wait4vsync checks suspend flag, wait4vsync needs to be executed before suspend flag set to enforce wait happen. Also, when timing generator is turned off, wait4vsync can not be used anymore since the last vsync may have passed before wait4vsync called. This patch fixed commit_comp timeout cause fence timeout happen on hdmi plug and unplug cases. CRs-fixed: 449027 Change-Id: I0f5520538bb290643a648c937296b6bc097fe051 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
This commit is contained in:
parent
f7f116bf52
commit
24683eeb25
3 changed files with 62 additions and 36 deletions
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@ -486,6 +486,20 @@ void mdp4_dsi_video_base_swap(int cndx, struct mdp4_overlay_pipe *pipe)
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vctrl->base_pipe = pipe;
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}
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/* timing generator off */
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static void mdp4_dsi_video_tg_off(struct vsycn_ctrl *vctrl)
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{
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unsigned long flags;
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spin_lock_irqsave(&vctrl->spin_lock, flags);
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INIT_COMPLETION(vctrl->vsync_comp);
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vctrl->wait_vsync_cnt++;
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MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); /* turn off timing generator */
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spin_unlock_irqrestore(&vctrl->spin_lock, flags);
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mdp4_dsi_video_wait4vsync(0);
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}
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int mdp4_dsi_video_on(struct platform_device *pdev)
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{
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int dsi_width;
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@ -585,8 +599,7 @@ int mdp4_dsi_video_on(struct platform_device *pdev)
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if (!(mfd->cont_splash_done)) {
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mfd->cont_splash_done = 1;
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MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
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mdp4_dsi_video_wait4vsync(0);
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mdp4_dsi_video_tg_off(vctrl);
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mipi_dsi_controller_cfg(0);
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/* Clks are enabled in probe.
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Disabling clocks now */
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@ -722,11 +735,10 @@ int mdp4_dsi_video_off(struct platform_device *pdev)
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vctrl = &vsync_ctrl_db[cndx];
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pipe = vctrl->base_pipe;
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atomic_set(&vctrl->suspend, 1);
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atomic_set(&vctrl->vsync_resume, 0);
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mdp4_dsi_video_wait4vsync(cndx);
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atomic_set(&vctrl->vsync_resume, 0);
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complete_all(&vctrl->vsync_comp);
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if (pipe->ov_blt_addr) {
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@ -740,8 +752,6 @@ int mdp4_dsi_video_off(struct platform_device *pdev)
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mdp_histogram_ctrl_all(FALSE);
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MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
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dsi_video_enabled = 0;
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undx = vctrl->update_ndx;
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@ -768,7 +778,6 @@ int mdp4_dsi_video_off(struct platform_device *pdev)
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mdp4_mixer_stage_down(pipe, 1);
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mdp4_overlay_pipe_free(pipe);
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vctrl->base_pipe = NULL;
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msleep(20);
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} else {
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/* system suspending */
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mdp4_mixer_stage_down(vctrl->base_pipe, 1);
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@ -777,6 +786,10 @@ int mdp4_dsi_video_off(struct platform_device *pdev)
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}
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}
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mdp4_dsi_video_tg_off(vctrl);
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atomic_set(&vctrl->suspend, 1);
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if (vctrl->vsync_irq_enabled) {
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vctrl->vsync_irq_enabled = 0;
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vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
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@ -570,20 +570,6 @@ static int mdp4_dtv_start(struct msm_fb_data_type *mfd)
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return 0;
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}
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static int mdp4_dtv_stop(struct msm_fb_data_type *mfd)
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{
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int cndx = 0;
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struct vsycn_ctrl *vctrl;
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vctrl = &vsync_ctrl_db[cndx];
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if (vctrl->base_pipe == NULL)
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return -EINVAL;
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MDP_OUTP(MDP_BASE + DTV_BASE, 0);
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return 0;
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}
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int mdp4_dtv_on(struct platform_device *pdev)
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{
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struct msm_fb_data_type *mfd;
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@ -629,6 +615,20 @@ int mdp4_dtv_on(struct platform_device *pdev)
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return ret;
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}
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/* timing generator off */
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static void mdp4_dtv_tg_off(struct vsycn_ctrl *vctrl)
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{
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unsigned long flags;
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spin_lock_irqsave(&vctrl->spin_lock, flags);
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INIT_COMPLETION(vctrl->vsync_comp);
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vctrl->wait_vsync_cnt++;
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MDP_OUTP(MDP_BASE + DTV_BASE, 0); /* turn off timing generator */
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spin_unlock_irqrestore(&vctrl->spin_lock, flags);
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mdp4_dtv_wait4vsync(0);
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}
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int mdp4_dtv_off(struct platform_device *pdev)
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{
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struct msm_fb_data_type *mfd;
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@ -643,11 +643,10 @@ int mdp4_dtv_off(struct platform_device *pdev)
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vctrl = &vsync_ctrl_db[cndx];
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atomic_set(&vctrl->suspend, 1);
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atomic_set(&vctrl->vsync_resume, 0);
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mdp4_dtv_wait4vsync(cndx);
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atomic_set(&vctrl->vsync_resume, 0);
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complete_all(&vctrl->vsync_comp);
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pipe = vctrl->base_pipe;
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@ -666,10 +665,12 @@ int mdp4_dtv_off(struct platform_device *pdev)
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mdp4_overlay_pipe_free(pipe);
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vctrl->base_pipe = NULL;
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}
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mdp4_dtv_stop(mfd);
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mdp4_dtv_wait4vsync(cndx);
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}
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mdp4_dtv_tg_off(vctrl);
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atomic_set(&vctrl->suspend, 1);
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mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);
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undx = vctrl->update_ndx;
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@ -867,7 +868,7 @@ int mdp4_overlay_dtv_unset(struct msm_fb_data_type *mfd,
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if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE &&
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pipe->pipe_type == OVERLAY_TYPE_RGB) {
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result = mdp4_dtv_stop(mfd);
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mdp4_dtv_tg_off(vctrl);
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vctrl->base_pipe = NULL;
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}
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return result;
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@ -347,9 +347,6 @@ void mdp4_lcdc_wait4vsync(int cndx)
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if (atomic_read(&vctrl->suspend) > 0)
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return;
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/* start timing generator & mmu if they are not started yet */
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mdp4_overlay_lcdc_start();
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mdp4_lcdc_vsync_irq_ctrl(cndx, 1);
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spin_lock_irqsave(&vctrl->spin_lock, flags);
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@ -688,10 +685,24 @@ int mdp4_lcdc_on(struct platform_device *pdev)
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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mdp_histogram_ctrl_all(TRUE);
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mdp4_overlay_lcdc_start();
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return ret;
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}
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/* timing generator off */
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static void mdp4_lcdc_tg_off(struct vsycn_ctrl *vctrl)
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{
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unsigned long flags;
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spin_lock_irqsave(&vctrl->spin_lock, flags);
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INIT_COMPLETION(vctrl->vsync_comp);
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vctrl->wait_vsync_cnt++;
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MDP_OUTP(MDP_BASE + LCDC_BASE, 0); /* turn off timing generator */
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spin_unlock_irqrestore(&vctrl->spin_lock, flags);
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mdp4_lcdc_wait4vsync(0);
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}
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int mdp4_lcdc_off(struct platform_device *pdev)
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{
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int ret = 0;
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@ -707,10 +718,9 @@ int mdp4_lcdc_off(struct platform_device *pdev)
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vctrl = &vsync_ctrl_db[cndx];
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pipe = vctrl->base_pipe;
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atomic_set(&vctrl->suspend, 1);
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atomic_set(&vctrl->vsync_resume, 0);
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mdp4_lcdc_wait4vsync(cndx);
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msleep(20); /* >= 17 ms */
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atomic_set(&vctrl->vsync_resume, 0);
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complete_all(&vctrl->vsync_comp);
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@ -725,8 +735,6 @@ int mdp4_lcdc_off(struct platform_device *pdev)
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mdp_histogram_ctrl_all(FALSE);
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MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
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lcdc_enabled = 0;
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undx = vctrl->update_ndx;
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@ -761,6 +769,10 @@ int mdp4_lcdc_off(struct platform_device *pdev)
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}
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}
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mdp4_lcdc_tg_off(vctrl);
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atomic_set(&vctrl->suspend, 1);
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/* MDP clock disable */
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mdp_clk_ctrl(0);
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mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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