Piteball/android_kernel_google_msm
1
0
Fork 0
mirror of https://github.com/followmsi/android_kernel_google_msm.git synced 2024-11-06 23:17:41 +00:00
Code Issues Projects Releases Wiki Activity

msm: Fix correct topology for qseecom bus scaling.

Browse source 
Currently, bus scaling topology for qseecom is incorrect.
 -Added the correct topology paths for accessing Crypto
  Engine which is controlled by QSEE.
 -Removed setting the clock frequency of DFAB. This is
  done by the bus driver.
 -Removed references to the dfab clock instance defined
  in clocks file.

Change-Id: Ib6953ea3bf5721d458bfe2aa06c54be329a8fdb9
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
(cherry picked from commit 1e8c7242fd3f32ade703484d2113f4a6f442a0e8)

Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
This commit is contained in:
Ramesh Masavarapu 2012-09-04 11:52:57 -07:00 committed by Stephen Boyd
parent d582953aa3
commit 2a1f81cc66
5 changed files with 64 additions and 37 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
arch/arm/mach-msm/board-8064.c
View file

@ -1555,10 +1555,16 @@ static struct platform_device msm_device_iris_fm __devinitdata = {
/* qseecom bus scaling */
static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
{
.src = MSM_BUS_MASTER_SPS,
.src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ib = 0,
.ab = 0,
.ib = 0,
},
{
.src = MSM_BUS_MASTER_ADM_PORT1,
.dst = MSM_BUS_SLAVE_GSBI1_UART,
.ab = 0,
.ib = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
@ -1570,10 +1576,16 @@ static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
{
.src = MSM_BUS_MASTER_SPS,
.src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ib = (492 * 8) * 1000000UL,
.ab = (492 * 8) * 100000UL,
.ab = 70000000UL,
.ib = 70000000UL,
},
{
.src = MSM_BUS_MASTER_ADM_PORT1,
.dst = MSM_BUS_SLAVE_GSBI1_UART,
.ab = 2480000000UL,
.ib = 2480000000UL,
},
{
.src = MSM_BUS_MASTER_SPDM,
@ -1585,10 +1597,16 @@ static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
{
.src = MSM_BUS_MASTER_SPS,
.src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ib = 0,
.ab = 0,
.ib = 0,
},
{
.src = MSM_BUS_MASTER_ADM_PORT1,
.dst = MSM_BUS_SLAVE_GSBI1_UART,
.ab = 0,
.ib = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
@ -1605,7 +1623,7 @@ static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
},
{
ARRAY_SIZE(qseecom_enable_dfab_vectors),
qseecom_enable_sfpb_vectors,
qseecom_enable_dfab_vectors,
},
{
ARRAY_SIZE(qseecom_enable_sfpb_vectors),

18
arch/arm/mach-msm/board-8930.c
View file

@ -969,6 +969,12 @@ static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,
@ -984,6 +990,12 @@ static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
.ib = (492 * 8) * 1000000UL,
.ab = (492 * 8) * 100000UL,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = (492 * 8) * 1000000UL,
.ab = (492 * 8) * 100000UL,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,
@ -999,6 +1011,12 @@ static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,

20
arch/arm/mach-msm/board-8960.c
View file

@ -1055,6 +1055,12 @@ static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,
@ -1070,6 +1076,12 @@ static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
.ib = (492 * 8) * 1000000UL,
.ab = (492 * 8) * 100000UL,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = (492 * 8) * 1000000UL,
.ab = (492 * 8) * 100000UL,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,
@ -1085,6 +1097,12 @@ static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ib = 0,
.ab = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
.dst = MSM_BUS_SLAVE_SPDM,
@ -1100,7 +1118,7 @@ static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
},
{
ARRAY_SIZE(qseecom_enable_dfab_vectors),
qseecom_enable_sfpb_vectors,
qseecom_enable_dfab_vectors,
},
{
ARRAY_SIZE(qseecom_enable_sfpb_vectors),

4
arch/arm/mach-msm/clock-8960.c
View file

@ -4718,7 +4718,6 @@ static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0);
static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0);
@ -5468,7 +5467,6 @@ static struct clk_lookup msm_clocks_8064[] = {
CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
@ -5823,7 +5821,6 @@ static struct clk_lookup msm_clocks_8960_common[] __initdata = {
CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
@ -6154,7 +6151,6 @@ static struct clk_lookup msm_clocks_8930[] = {
CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),

25
drivers/misc/qseecom.c
View file

@ -147,7 +147,6 @@ static DEFINE_MUTEX(app_access_lock);
static int qsee_bw_count;
static int qsee_sfpb_bw_count;
static struct clk *qseecom_bus_clk;
static uint32_t qsee_perf_client;
struct qseecom_registered_listener_list {
@ -1199,11 +1198,6 @@ static int qsee_vote_for_clock(int32_t clk_type)
switch (clk_type) {
case CLK_DFAB:
/* Check if the clk is valid */
if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
pr_warn("qseecom bus clock is null or error");
return -EINVAL;
}
mutex_lock(&qsee_bw_mutex);
if (!qsee_bw_count) {
ret = msm_bus_scale_client_update_request(
@ -1245,11 +1239,6 @@ static void qsee_disable_clock_vote(int32_t clk_type)
switch (clk_type) {
case CLK_DFAB:
/* Check if the DFAB clk is valid */
if (IS_ERR_OR_NULL(qseecom_bus_clk)) {
pr_warn("qseecom bus clock is null or error");
return;
}
mutex_lock(&qsee_bw_mutex);
if (qsee_bw_count > 0) {
if (qsee_bw_count-- == 1) {
@ -1731,7 +1720,6 @@ static int __devinit qseecom_probe(struct platform_device *pdev)
uint32_t system_call_id = QSEOS_CHECK_VERSION_CMD;
qsee_bw_count = 0;
qseecom_bus_clk = NULL;
qsee_perf_client = 0;
rc = alloc_chrdev_region(&qseecom_device_no, 0, 1, QSEECOM_DEV);
@ -1799,17 +1787,8 @@ static int __devinit qseecom_probe(struct platform_device *pdev)
qsee_perf_client = msm_bus_scale_register_client(
qseecom_platform_support);
if (!qsee_perf_client) {
if (!qsee_perf_client)
pr_err("Unable to register bus client\n");
} else {
qseecom_bus_clk = clk_get(class_dev, "bus_clk");
if (IS_ERR(qseecom_bus_clk)) {
qseecom_bus_clk = NULL;
} else if (qseecom_bus_clk != NULL) {
pr_debug("Enabled DFAB clock");
clk_set_rate(qseecom_bus_clk, 64000000);
}
}
}
return 0;
@ -1853,8 +1832,6 @@ static int __devinit qseecom_init(void)
static void __devexit qseecom_exit(void)
{
clk_put(qseecom_bus_clk);
device_destroy(driver_class, qseecom_device_no);
class_destroy(driver_class);
unregister_chrdev_region(qseecom_device_no, 1);