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x86: multi pci root bus with different io resource range, on 64-bit
scan AMD opteron io/mmio routing to make sure every pci root bus get correct resource range. Thus later pci scan could assign correct resource to device with unassigned resource. this can fix a system without _CRS for multi pci root bus. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
35ddd068fb
commit
30a18d6c3f
5 changed files with 372 additions and 59 deletions
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@ -13,5 +13,5 @@ obj-y += legacy.o irq.o common.o early.o
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# mmconfig has a 64bit special
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obj-$(CONFIG_PCI_MMCONFIG) += mmconfig_64.o direct.o mmconfig-shared.o
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obj-$(CONFIG_NUMA) += k8-bus_64.o
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obj-y += k8-bus_64.o
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@ -7,23 +7,29 @@
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/*
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* This discovers the pcibus <-> node mapping on AMD K8.
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*
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* RED-PEN need to call this again on PCI hotplug
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* RED-PEN empty cpus get reported wrong
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* also get peer root bus resource for io,mmio
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*/
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#define NODE_ID(dword) ((dword>>4) & 0x07)
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#define LDT_BUS_NUMBER_REGISTER_0 0xE0
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#define LDT_BUS_NUMBER_REGISTER_1 0xE4
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#define LDT_BUS_NUMBER_REGISTER_2 0xE8
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#define LDT_BUS_NUMBER_REGISTER_3 0xEC
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#define NR_LDT_BUS_NUMBER_REGISTERS 4
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#define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF)
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#define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 24) & 0xFF)
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#define PCI_DEVICE_ID_K8HTCONFIG 0x1100
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#define PCI_DEVICE_ID_K8_10H_HTCONFIG 0x1200
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#define PCI_DEVICE_ID_K8_11H_HTCONFIG 0x1300
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/*
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* sub bus (transparent) will use entres from 3 to store extra from root,
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* so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
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*/
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#define RES_NUM 16
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struct pci_root_info {
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char name[12];
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unsigned int res_num;
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struct resource res[RES_NUM];
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int bus_min;
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int bus_max;
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int node;
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int link;
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};
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/* 4 at this time, it may become to 32 */
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#define PCI_ROOT_NR 4
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static int pci_root_num;
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static struct pci_root_info pci_root_info[PCI_ROOT_NR];
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#ifdef CONFIG_NUMA
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@ -55,77 +61,375 @@ int get_mp_bus_to_node(int busnum)
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return node;
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}
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#endif
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void set_pci_bus_resources_arch_default(struct pci_bus *b)
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{
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int i;
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int j;
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struct pci_root_info *info;
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if (!pci_root_num)
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return;
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for (i = 0; i < pci_root_num; i++) {
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if (pci_root_info[i].bus_min == b->number)
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break;
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}
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if (i == pci_root_num)
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return;
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info = &pci_root_info[i];
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for (j = 0; j < info->res_num; j++) {
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struct resource *res;
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struct resource *root;
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res = &info->res[j];
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b->resource[j] = res;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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else
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root = &iomem_resource;
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insert_resource(root, res);
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}
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}
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#define RANGE_NUM 16
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struct res_range {
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size_t start;
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size_t end;
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};
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static void __init update_range(struct res_range *range, size_t start,
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size_t end)
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{
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int i;
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int j;
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for (j = 0; j < RANGE_NUM; j++) {
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if (!range[j].end)
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continue;
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if (start == range[j].start && end < range[j].end) {
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range[j].start = end + 1;
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break;
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} else if (start == range[j].start && end == range[j].end) {
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range[j].start = 0;
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range[j].end = 0;
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break;
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} else if (start > range[j].start && end == range[j].end) {
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range[j].end = start - 1;
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break;
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} else if (start > range[j].start && end < range[j].end) {
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/* find the new spare */
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for (i = 0; i < RANGE_NUM; i++) {
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if (range[i].end == 0)
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break;
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}
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if (i < RANGE_NUM) {
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range[i].end = range[j].end;
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range[i].start = end + 1;
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} else {
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printk(KERN_ERR "run of slot in ranges\n");
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}
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range[j].end = start - 1;
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break;
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}
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}
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}
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static void __init update_res(struct pci_root_info *info, size_t start,
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size_t end, unsigned long flags, int merge)
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{
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int i;
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struct resource *res;
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if (!merge)
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goto addit;
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/* try to merge it with old one */
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for (i = 0; i < info->res_num; i++) {
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res = &info->res[i];
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if (res->flags != flags)
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continue;
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if (res->end + 1 == start) {
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res->end = end;
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return;
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} else if (end + 1 == res->start) {
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res->start = start;
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return;
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}
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}
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addit:
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/* need to add that */
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if (info->res_num >= RES_NUM)
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return;
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res = &info->res[info->res_num];
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res->name = info->name;
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res->flags = flags;
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res->start = start;
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res->end = end;
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res->child = NULL;
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info->res_num++;
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}
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struct pci_hostbridge_probe {
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u32 bus;
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u32 slot;
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u32 vendor;
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u32 device;
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};
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static struct pci_hostbridge_probe pci_probes[] __initdata = {
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
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{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
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};
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/**
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* early_fill_mp_bus_to_node()
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* called before pcibios_scan_root and pci_scan_bus
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* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
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* Registers found in the K8 northbridge
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*/
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__init static int
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early_fill_mp_bus_to_node(void)
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static int __init early_fill_mp_bus_info(void)
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{
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#ifdef CONFIG_NUMA
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int i, j;
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int i;
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int j;
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unsigned bus;
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unsigned slot;
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u32 ldtbus;
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u32 id;
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int found;
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int node;
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u16 deviceid;
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u16 vendorid;
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int min_bus;
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int max_bus;
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static int lbnr[NR_LDT_BUS_NUMBER_REGISTERS] = {
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LDT_BUS_NUMBER_REGISTER_0,
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LDT_BUS_NUMBER_REGISTER_1,
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LDT_BUS_NUMBER_REGISTER_2,
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LDT_BUS_NUMBER_REGISTER_3
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};
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int link;
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int def_node;
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int def_link;
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struct pci_root_info *info;
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u32 reg;
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struct resource *res;
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size_t start;
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size_t end;
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struct res_range range[RANGE_NUM];
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u64 val;
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u32 address;
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#ifdef CONFIG_NUMA
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for (i = 0; i < BUS_NR; i++)
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mp_bus_to_node[i] = -1;
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#endif
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if (!early_pci_allowed())
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return -1;
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slot = 0x18;
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id = read_pci_config(0, slot, 0, PCI_VENDOR_ID);
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found = 0;
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for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
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u32 id;
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u16 device;
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u16 vendor;
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vendorid = id & 0xffff;
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if (vendorid != PCI_VENDOR_ID_AMD)
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goto out;
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bus = pci_probes[i].bus;
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slot = pci_probes[i].slot;
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id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
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deviceid = (id>>16) & 0xffff;
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if ((deviceid != PCI_DEVICE_ID_K8HTCONFIG) &&
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(deviceid != PCI_DEVICE_ID_K8_10H_HTCONFIG) &&
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(deviceid != PCI_DEVICE_ID_K8_11H_HTCONFIG))
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goto out;
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for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) {
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ldtbus = read_pci_config(0, slot, 1, lbnr[i]);
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/* Check if that register is enabled for bus range */
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if ((ldtbus & 7) != 3)
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continue;
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min_bus = SECONDARY_LDT_BUS_NUMBER(ldtbus);
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max_bus = SUBORDINATE_LDT_BUS_NUMBER(ldtbus);
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node = NODE_ID(ldtbus);
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for (j = min_bus; j <= max_bus; j++)
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mp_bus_to_node[j] = (unsigned char) node;
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vendor = id & 0xffff;
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device = (id>>16) & 0xffff;
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if (pci_probes[i].vendor == vendor &&
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pci_probes[i].device == device) {
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found = 1;
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break;
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}
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}
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out:
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if (!found)
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return 0;
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pci_root_num = 0;
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for (i = 0; i < 4; i++) {
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int min_bus;
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int max_bus;
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reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
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/* Check if that register is enabled for bus range */
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if ((reg & 7) != 3)
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continue;
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min_bus = (reg >> 16) & 0xff;
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max_bus = (reg >> 24) & 0xff;
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node = (reg >> 4) & 0x07;
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#ifdef CONFIG_NUMA
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for (j = min_bus; j <= max_bus; j++)
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mp_bus_to_node[j] = (unsigned char) node;
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#endif
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link = (reg >> 8) & 0x03;
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info = &pci_root_info[pci_root_num];
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info->bus_min = min_bus;
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info->bus_max = max_bus;
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info->node = node;
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info->link = link;
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sprintf(info->name, "PCI Bus #%02x", min_bus);
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pci_root_num++;
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}
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/* get the default node and link for left over res */
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reg = read_pci_config(bus, slot, 0, 0x60);
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def_node = (reg >> 8) & 0x07;
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reg = read_pci_config(bus, slot, 0, 0x64);
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def_link = (reg >> 8) & 0x03;
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memset(range, 0, sizeof(range));
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range[0].end = 0xffff;
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/* io port resource */
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for (i = 0; i < 4; i++) {
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reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
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if (!(reg & 3))
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continue;
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start = reg & 0xfff000;
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reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
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node = reg & 0x07;
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link = (reg >> 4) & 0x03;
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end = (reg & 0xfff000) | 0xfff;
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == node && info->link == link)
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break;
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}
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if (j == pci_root_num)
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continue; /* not found */
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info = &pci_root_info[j];
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update_res(info, start, end, IORESOURCE_IO, 0);
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update_range(range, start, end);
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}
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/* add left over io port range to def node/link, [0, 0xffff] */
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == def_node && info->link == def_link)
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break;
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}
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if (j < pci_root_num) {
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info = &pci_root_info[j];
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for (i = 0; i < RANGE_NUM; i++) {
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if (!range[i].end)
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continue;
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update_res(info, range[i].start, range[i].end,
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IORESOURCE_IO, 1);
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}
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}
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memset(range, 0, sizeof(range));
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/* 0xfd00000000-0xffffffffff for HT */
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/* 0xfc00000000-0xfcffffffff for Family 10h mmconfig*/
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range[0].end = 0xfbffffffffULL;
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/* need to take out [0, TOM) for RAM*/
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address = MSR_K8_TOP_MEM1;
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rdmsrl(address, val);
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end = (val & 0xffffff8000000ULL);
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printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
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if (end < (1ULL<<32))
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update_range(range, 0, end - 1);
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/* mmio resource */
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for (i = 0; i < 8; i++) {
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reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
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if (!(reg & 3))
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continue;
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start = reg & 0xffffff00; /* 39:16 on 31:8*/
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start <<= 8;
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reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
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node = reg & 0x07;
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link = (reg >> 4) & 0x03;
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end = (reg & 0xffffff00);
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end <<= 8;
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end |= 0xffff;
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == node && info->link == link)
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break;
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}
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if (j == pci_root_num)
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continue; /* not found */
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info = &pci_root_info[j];
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update_res(info, start, end, IORESOURCE_MEM, 0);
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update_range(range, start, end);
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}
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/* need to take out [4G, TOM2) for RAM*/
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/* SYS_CFG */
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address = MSR_K8_SYSCFG;
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rdmsrl(address, val);
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/* TOP_MEM2 is enabled? */
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if (val & (1<<21)) {
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/* TOP_MEM2 */
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address = MSR_K8_TOP_MEM2;
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rdmsrl(address, val);
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end = (val & 0xffffff8000000ULL);
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printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
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update_range(range, 1ULL<<32, end - 1);
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}
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/*
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* add left over mmio range to def node/link ?
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* that is tricky, just record range in from start_min to 4G
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*/
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == def_node && info->link == def_link)
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break;
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}
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if (j < pci_root_num) {
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info = &pci_root_info[j];
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for (i = 0; i < RANGE_NUM; i++) {
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if (!range[i].end)
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continue;
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update_res(info, range[i].start, range[i].end,
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IORESOURCE_MEM, 1);
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}
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}
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#ifdef CONFIG_NUMA
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for (i = 0; i < BUS_NR; i++) {
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node = mp_bus_to_node[i];
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if (node >= 0)
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printk(KERN_DEBUG "bus: %02x to node: %02x\n", i, node);
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}
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#endif
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for (i = 0; i < pci_root_num; i++) {
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int res_num;
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int busnum;
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info = &pci_root_info[i];
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res_num = info->res_num;
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busnum = info->bus_min;
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printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
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info->bus_min, info->bus_max, info->node, info->link);
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for (j = 0; j < res_num; j++) {
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res = &info->res[j];
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printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
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busnum, j,
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(res->flags & IORESOURCE_IO)?"io port":"mmio",
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res->start, res->end);
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}
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}
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return 0;
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}
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postcore_initcall(early_fill_mp_bus_to_node);
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||||
postcore_initcall(early_fill_mp_bus_info);
|
||||
|
|
|
|||
|
|
@ -1088,6 +1088,10 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
|
|||
return max;
|
||||
}
|
||||
|
||||
void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
|
||||
{
|
||||
}
|
||||
|
||||
struct pci_bus * pci_create_bus(struct device *parent,
|
||||
int bus, struct pci_ops *ops, void *sysdata)
|
||||
{
|
||||
|
|
@ -1147,6 +1151,8 @@ struct pci_bus * pci_create_bus(struct device *parent,
|
|||
b->resource[0] = &ioport_resource;
|
||||
b->resource[1] = &iomem_resource;
|
||||
|
||||
set_pci_bus_resources_arch_default(b);
|
||||
|
||||
return b;
|
||||
|
||||
dev_create_file_err:
|
||||
|
|
|
|||
|
|
@ -193,6 +193,9 @@ extern cpumask_t cpu_coregroup_map(int cpu);
|
|||
#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
|
||||
#endif
|
||||
|
||||
struct pci_bus;
|
||||
void set_pci_bus_resources_arch_default(struct pci_bus *b);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define mc_capable() (boot_cpu_data.x86_max_cores > 1)
|
||||
#define smt_capable() (smp_num_siblings > 1)
|
||||
|
|
|
|||
|
|
@ -254,7 +254,7 @@ static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
|
|||
#define PCI_NUM_RESOURCES 11
|
||||
|
||||
#ifndef PCI_BUS_NUM_RESOURCES
|
||||
#define PCI_BUS_NUM_RESOURCES 8
|
||||
#define PCI_BUS_NUM_RESOURCES 16
|
||||
#endif
|
||||
|
||||
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
|
||||
|
|
|
|||
Loading…
Reference in a new issue