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msm: pil-q6v5-mss: Add memory barrier after RMB_MBA_IMAGE write

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Ensure the write of the image address in the RMB_MBA_IMAGE RMB
register occurs before the writes to the QDSP6SS that releases
the Q6 processor from reset.

Change-Id: I7efbe4e0b81153cc2dc15d8ec60173008478b826
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
This commit is contained in:
Matt Wagantall 2012-07-27 15:47:59 -07:00 committed by Stephen Boyd
parent 985df205dc
commit 436be25a85
1 changed files with 5 additions and 2 deletions
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7
arch/arm/mach-msm/pil-q6v5-mss.c
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@ -155,11 +155,14 @@ static int pil_mss_reset(struct pil_desc *pil)
goto err_clks;
/* Program Image Address */
if (drv->self_auth)
if (drv->self_auth) {
writel_relaxed(drv->start_addr, drv->rmb_base + RMB_MBA_IMAGE);
else
/* Ensure write to RMB base occurs before reset is released. */
mb();
} else {
writel_relaxed((drv->start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
}
ret = pil_q6v5_reset(pil);
if (ret)