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msm: kgsl: Restructure performance counters
Restructure the performance counter mechanism by combining the two structures declared for it. The 2 structures can only refer to a single counter hence it is easier to manage by having them under a single structure. Change-Id: I19d13cf5aa619b85a332b383b464c2af65ad38c9 Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
This commit is contained in:
Shubhraprakash Das
Iliyan Malchev
parent
3f85725c9d
commit
589ae1ef24
3 changed files with 132 additions and 190 deletions
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@ -325,8 +325,7 @@ int adreno_perfcounter_read_group(struct adreno_device *adreno_dev,
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if (group->regs[i].countable == list[j].countable) {
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list[j].value =
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adreno_dev->gpudev->perfcounter_read(
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adreno_dev, list[j].groupid,
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i, group->regs[i].offset);
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adreno_dev, list[j].groupid, i);
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break;
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}
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}
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@ -207,12 +207,16 @@ enum adreno_device_flags {
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* @kernelcount: number of user space users of the register
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* @usercount: number of kernel users of the register
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* @offset: register hardware offset
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* @load_bit: The bit number in LOAD register which corresponds to this counter
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* @select: The countable register offset
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*/
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struct adreno_perfcount_register {
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unsigned int countable;
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unsigned int kernelcount;
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unsigned int usercount;
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unsigned int offset;
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int load_bit;
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unsigned int select;
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};
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/**
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@ -235,6 +239,9 @@ struct adreno_perfcounters {
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unsigned int group_count;
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};
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#define ADRENO_PERFCOUNTER_GROUP(core, name) { core##_perfcounters_##name, \
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ARRAY_SIZE(core##_perfcounters_##name) }
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/**
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* adreno_regs: List of registers that are used in kgsl driver for all
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* 3D devices. Each device type has different offset value for the same
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@ -361,8 +368,7 @@ struct adreno_gpudev {
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void (*perfcounter_enable)(struct adreno_device *, unsigned int group,
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unsigned int counter, unsigned int countable);
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uint64_t (*perfcounter_read)(struct adreno_device *adreno_dev,
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unsigned int group, unsigned int counter,
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unsigned int offset);
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unsigned int group, unsigned int counter);
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int (*coresight_enable) (struct kgsl_device *device);
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void (*coresight_disable) (struct kgsl_device *device);
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void (*coresight_config_debug_reg) (struct kgsl_device *device,
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@ -3147,117 +3147,6 @@ static void a3xx_cp_callback(struct adreno_device *adreno_dev, int irq)
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adreno_dispatcher_schedule(device);
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}
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/**
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* struct a3xx_perfcounter_register - Define a performance counter register
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* @load_bit: the bit to set in RBBM_LOAD_CMD0/RBBM_LOAD_CMD1 to force the RBBM
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* to load the reset value into the appropriate counter
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* @select: The dword offset of the register to write the selected
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* countable into
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*/
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struct a3xx_perfcounter_register {
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unsigned int load_bit;
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unsigned int select;
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_cp[] = {
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{ 0, A3XX_CP_PERFCOUNTER_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_rbbm[] = {
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{ 1, A3XX_RBBM_PERFCOUNTER0_SELECT },
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{ 2, A3XX_RBBM_PERFCOUNTER1_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_pc[] = {
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{ 3, A3XX_PC_PERFCOUNTER0_SELECT },
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{ 4, A3XX_PC_PERFCOUNTER1_SELECT },
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{ 5, A3XX_PC_PERFCOUNTER2_SELECT },
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{ 6, A3XX_PC_PERFCOUNTER3_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_vfd[] = {
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{ 7, A3XX_VFD_PERFCOUNTER0_SELECT },
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{ 8, A3XX_VFD_PERFCOUNTER1_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_hlsq[] = {
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{ 9, A3XX_HLSQ_PERFCOUNTER0_SELECT },
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{ 10, A3XX_HLSQ_PERFCOUNTER1_SELECT },
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{ 11, A3XX_HLSQ_PERFCOUNTER2_SELECT },
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{ 12, A3XX_HLSQ_PERFCOUNTER3_SELECT },
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{ 13, A3XX_HLSQ_PERFCOUNTER4_SELECT },
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{ 14, A3XX_HLSQ_PERFCOUNTER5_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_vpc[] = {
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{ 15, A3XX_VPC_PERFCOUNTER0_SELECT },
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{ 16, A3XX_VPC_PERFCOUNTER1_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_tse[] = {
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{ 17, A3XX_GRAS_PERFCOUNTER0_SELECT },
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{ 18, A3XX_GRAS_PERFCOUNTER1_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_ras[] = {
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{ 19, A3XX_GRAS_PERFCOUNTER2_SELECT },
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{ 20, A3XX_GRAS_PERFCOUNTER3_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_uche[] = {
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{ 21, A3XX_UCHE_PERFCOUNTER0_SELECT },
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{ 22, A3XX_UCHE_PERFCOUNTER1_SELECT },
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{ 23, A3XX_UCHE_PERFCOUNTER2_SELECT },
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{ 24, A3XX_UCHE_PERFCOUNTER3_SELECT },
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{ 25, A3XX_UCHE_PERFCOUNTER4_SELECT },
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{ 26, A3XX_UCHE_PERFCOUNTER5_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_tp[] = {
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{ 27, A3XX_TP_PERFCOUNTER0_SELECT },
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{ 28, A3XX_TP_PERFCOUNTER1_SELECT },
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{ 29, A3XX_TP_PERFCOUNTER2_SELECT },
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{ 30, A3XX_TP_PERFCOUNTER3_SELECT },
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{ 31, A3XX_TP_PERFCOUNTER4_SELECT },
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{ 32, A3XX_TP_PERFCOUNTER5_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_sp[] = {
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{ 33, A3XX_SP_PERFCOUNTER0_SELECT },
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{ 34, A3XX_SP_PERFCOUNTER1_SELECT },
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{ 35, A3XX_SP_PERFCOUNTER2_SELECT },
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{ 36, A3XX_SP_PERFCOUNTER3_SELECT },
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{ 37, A3XX_SP_PERFCOUNTER4_SELECT },
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{ 38, A3XX_SP_PERFCOUNTER5_SELECT },
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{ 39, A3XX_SP_PERFCOUNTER6_SELECT },
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{ 40, A3XX_SP_PERFCOUNTER7_SELECT },
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};
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static struct a3xx_perfcounter_register a3xx_perfcounter_reg_rb[] = {
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{ 41, A3XX_RB_PERFCOUNTER0_SELECT },
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{ 42, A3XX_RB_PERFCOUNTER1_SELECT },
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};
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#define REGCOUNTER_GROUP(_x) { (_x), ARRAY_SIZE((_x)) }
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static struct {
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struct a3xx_perfcounter_register *regs;
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int count;
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} a3xx_perfcounter_reglist[] = {
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_cp),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_rbbm),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_pc),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_vfd),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_hlsq),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_vpc),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_tse),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_ras),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_uche),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_tp),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_sp),
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REGCOUNTER_GROUP(a3xx_perfcounter_reg_rb),
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};
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static void a3xx_perfcounter_enable_pwr(struct kgsl_device *device,
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unsigned int countable)
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@ -3356,7 +3245,7 @@ static void a3xx_perfcounter_enable(struct adreno_device *adreno_dev,
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{
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struct kgsl_device *device = &adreno_dev->dev;
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unsigned int val = 0;
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struct a3xx_perfcounter_register *reg;
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struct adreno_perfcount_register *reg;
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/* Special cases */
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if (group == KGSL_PERFCOUNTER_GROUP_PWR)
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@ -3366,13 +3255,14 @@ static void a3xx_perfcounter_enable(struct adreno_device *adreno_dev,
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else if (group == KGSL_PERFCOUNTER_GROUP_VBIF_PWR)
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return a3xx_perfcounter_enable_vbif_pwr(device, countable);
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if (group >= ARRAY_SIZE(a3xx_perfcounter_reglist))
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if (group >= adreno_dev->gpudev->perfcounters->group_count)
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return;
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if (counter >= a3xx_perfcounter_reglist[group].count)
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if (counter >=
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adreno_dev->gpudev->perfcounters->groups[group].reg_count)
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return;
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reg = &(a3xx_perfcounter_reglist[group].regs[counter]);
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reg = &(adreno_dev->gpudev->perfcounters->groups[group].regs[counter]);
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/* Select the desired perfcounter */
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kgsl_regwrite(device, reg->select, countable);
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@ -3387,27 +3277,29 @@ static void a3xx_perfcounter_enable(struct adreno_device *adreno_dev,
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}
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static uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev,
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unsigned int group, unsigned int counter,
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unsigned int offset)
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unsigned int group, unsigned int counter)
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{
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struct kgsl_device *device = &adreno_dev->dev;
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struct a3xx_perfcounter_register *reg = NULL;
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struct adreno_perfcount_register *reg;
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unsigned int lo = 0, hi = 0;
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unsigned int val;
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unsigned int offset;
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if (group >= ARRAY_SIZE(a3xx_perfcounter_reglist))
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if (group >= adreno_dev->gpudev->perfcounters->group_count)
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return 0;
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if (counter >= a3xx_perfcounter_reglist[group].count)
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if (counter >=
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adreno_dev->gpudev->perfcounters->groups[group].reg_count)
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return 0;
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reg = &(a3xx_perfcounter_reglist[group].regs[counter]);
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reg = &(adreno_dev->gpudev->perfcounters->groups[group].regs[counter]);
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/* Freeze the counter */
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kgsl_regread(device, A3XX_RBBM_PERFCTR_CTL, &val);
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val &= ~reg->load_bit;
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
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offset = reg->offset;
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/* Read the values */
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kgsl_regread(device, offset, &lo);
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kgsl_regread(device, offset + 1, &hi);
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@ -3689,115 +3581,160 @@ const struct adreno_vbif_platform a3xx_vbif_platforms[] = {
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*/
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static struct adreno_perfcount_register a3xx_perfcounters_cp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO,
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0, A3XX_CP_PERFCOUNTER_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_rbbm[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO,
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1, A3XX_RBBM_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO,
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2, A3XX_RBBM_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_pc[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO,
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3, A3XX_PC_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO,
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4, A3XX_PC_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO,
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5, A3XX_PC_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO,
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6, A3XX_PC_PERFCOUNTER3_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_vfd[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO,
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7, A3XX_VFD_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO,
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8, A3XX_VFD_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_hlsq[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO,
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9, A3XX_HLSQ_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO,
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10, A3XX_HLSQ_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO,
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11, A3XX_HLSQ_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO,
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12, A3XX_HLSQ_PERFCOUNTER3_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO,
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13, A3XX_HLSQ_PERFCOUNTER4_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO,
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14, A3XX_HLSQ_PERFCOUNTER5_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_vpc[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO,
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15, A3XX_VPC_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO,
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16, A3XX_VPC_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_tse[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO,
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17, A3XX_GRAS_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO,
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18, A3XX_GRAS_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_ras[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO,
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19, A3XX_GRAS_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO,
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20, A3XX_GRAS_PERFCOUNTER3_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_uche[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO,
|
||||
21, A3XX_UCHE_PERFCOUNTER0_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO,
|
||||
22, A3XX_UCHE_PERFCOUNTER1_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO,
|
||||
23, A3XX_UCHE_PERFCOUNTER2_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO,
|
||||
24, A3XX_UCHE_PERFCOUNTER3_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO,
|
||||
25, A3XX_UCHE_PERFCOUNTER4_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO,
|
||||
26, A3XX_UCHE_PERFCOUNTER5_SELECT },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_tp[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO,
|
||||
27, A3XX_TP_PERFCOUNTER0_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO,
|
||||
28, A3XX_TP_PERFCOUNTER1_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO,
|
||||
29, A3XX_TP_PERFCOUNTER2_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO,
|
||||
30, A3XX_TP_PERFCOUNTER3_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO,
|
||||
31, A3XX_TP_PERFCOUNTER4_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO,
|
||||
32, A3XX_TP_PERFCOUNTER5_SELECT },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_sp[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO,
|
||||
33, A3XX_SP_PERFCOUNTER0_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO,
|
||||
34, A3XX_SP_PERFCOUNTER1_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO,
|
||||
35, A3XX_SP_PERFCOUNTER2_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO,
|
||||
36, A3XX_SP_PERFCOUNTER3_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO,
|
||||
37, A3XX_SP_PERFCOUNTER4_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO,
|
||||
38, A3XX_SP_PERFCOUNTER5_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO,
|
||||
39, A3XX_SP_PERFCOUNTER6_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO,
|
||||
40, A3XX_SP_PERFCOUNTER7_SELECT },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_rb[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO,
|
||||
41, A3XX_RB_PERFCOUNTER0_SELECT },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO,
|
||||
42, A3XX_RB_PERFCOUNTER1_SELECT },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_pwr[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO,
|
||||
-1, 0 },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_1_LO,
|
||||
-1, 0 },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_vbif[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT0_LO, -1, 0 },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT1_LO, -1, 0 },
|
||||
};
|
||||
static struct adreno_perfcount_register a3xx_perfcounters_vbif_pwr[] = {
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT0_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT1_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT0_LO, -1, 0 },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT1_LO, -1, 0 },
|
||||
{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO, -1, 0 },
|
||||
};
|
||||
|
||||
static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
|
||||
{ a3xx_perfcounters_cp, ARRAY_SIZE(a3xx_perfcounters_cp) },
|
||||
{ a3xx_perfcounters_rbbm, ARRAY_SIZE(a3xx_perfcounters_rbbm) },
|
||||
{ a3xx_perfcounters_pc, ARRAY_SIZE(a3xx_perfcounters_pc) },
|
||||
{ a3xx_perfcounters_vfd, ARRAY_SIZE(a3xx_perfcounters_vfd) },
|
||||
{ a3xx_perfcounters_hlsq, ARRAY_SIZE(a3xx_perfcounters_hlsq) },
|
||||
{ a3xx_perfcounters_vpc, ARRAY_SIZE(a3xx_perfcounters_vpc) },
|
||||
{ a3xx_perfcounters_tse, ARRAY_SIZE(a3xx_perfcounters_tse) },
|
||||
{ a3xx_perfcounters_ras, ARRAY_SIZE(a3xx_perfcounters_ras) },
|
||||
{ a3xx_perfcounters_uche, ARRAY_SIZE(a3xx_perfcounters_uche) },
|
||||
{ a3xx_perfcounters_tp, ARRAY_SIZE(a3xx_perfcounters_tp) },
|
||||
{ a3xx_perfcounters_sp, ARRAY_SIZE(a3xx_perfcounters_sp) },
|
||||
{ a3xx_perfcounters_rb, ARRAY_SIZE(a3xx_perfcounters_rb) },
|
||||
{ a3xx_perfcounters_pwr, ARRAY_SIZE(a3xx_perfcounters_pwr) },
|
||||
{ a3xx_perfcounters_vbif, ARRAY_SIZE(a3xx_perfcounters_vbif) },
|
||||
{ a3xx_perfcounters_vbif_pwr, ARRAY_SIZE(a3xx_perfcounters_vbif_pwr) },
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, cp),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, rbbm),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, pc),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, vfd),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, hlsq),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, vpc),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, tse),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, ras),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, uche),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, tp),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, sp),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, rb),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, pwr),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, vbif),
|
||||
ADRENO_PERFCOUNTER_GROUP(a3xx, vbif_pwr),
|
||||
};
|
||||
|
||||
static struct adreno_perfcounters a3xx_perfcounters = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue