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https://github.com/followmsi/android_kernel_google_msm.git
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[ARM] mtd: msm nand driver
Signed-off-by: Brian Swetland <swetland@google.com> Signed-off-by: Arve Hjønnevåg <arve@android.com>
This commit is contained in:
Arve Hjønnevåg
Stephen Boyd
parent
ead39d3f14
commit
58f5b3e6ae
5 changed files with 7342 additions and 1 deletions
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@ -50,6 +50,16 @@ config MTD_MS02NV
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say M here and read <file:Documentation/kbuild/modules.txt>.
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say M here and read <file:Documentation/kbuild/modules.txt>.
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The module will be called ms02-nv.
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The module will be called ms02-nv.
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config MTD_MSM_NAND
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tristate "MSM NAND Device Support"
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depends on MTD && ARCH_MSM
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select CRC16
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select BITREVERSE
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select MTD_NAND_IDS
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default y
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help
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Support for some NAND chips connected to the MSM NAND controller.
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config MTD_DATAFLASH
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config MTD_DATAFLASH
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tristate "Support for AT45xxx DataFlash"
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tristate "Support for AT45xxx DataFlash"
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depends on SPI_MASTER && EXPERIMENTAL
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depends on SPI_MASTER && EXPERIMENTAL
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@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_SLRAM) += slram.o
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obj-$(CONFIG_MTD_PHRAM) += phram.o
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obj-$(CONFIG_MTD_PHRAM) += phram.o
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obj-$(CONFIG_MTD_PMC551) += pmc551.o
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obj-$(CONFIG_MTD_PMC551) += pmc551.o
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obj-$(CONFIG_MTD_MS02NV) += ms02-nv.o
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obj-$(CONFIG_MTD_MS02NV) += ms02-nv.o
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obj-$(CONFIG_MTD_MSM_NAND) += msm_nand.o
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obj-$(CONFIG_MTD_MTDRAM) += mtdram.o
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obj-$(CONFIG_MTD_MTDRAM) += mtdram.o
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obj-$(CONFIG_MTD_LART) += lart.o
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obj-$(CONFIG_MTD_LART) += lart.o
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obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
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obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
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7138
drivers/mtd/devices/msm_nand.c
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7138
drivers/mtd/devices/msm_nand.c
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File diff suppressed because it is too large
Load diff
192
drivers/mtd/devices/msm_nand.h
Normal file
192
drivers/mtd/devices/msm_nand.h
Normal file
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@ -0,0 +1,192 @@
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/* drivers/mtd/devices/msm_nand.h
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*
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* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_MTD_DEVICES_MSM_NAND_H
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#define __DRIVERS_MTD_DEVICES_MSM_NAND_H
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#include <mach/msm_iomap.h>
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extern unsigned long msm_nand_phys;
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extern unsigned long msm_nandc01_phys;
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extern unsigned long msm_nandc10_phys;
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extern unsigned long msm_nandc11_phys;
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extern unsigned long ebi2_register_base;
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#define NC01(X) ((X) + msm_nandc01_phys - msm_nand_phys)
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#define NC10(X) ((X) + msm_nandc10_phys - msm_nand_phys)
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#define NC11(X) ((X) + msm_nandc11_phys - msm_nand_phys)
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#define MSM_NAND_REG(off) (msm_nand_phys + (off))
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#define MSM_NAND_FLASH_CMD MSM_NAND_REG(0x0000)
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#define MSM_NAND_ADDR0 MSM_NAND_REG(0x0004)
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#define MSM_NAND_ADDR1 MSM_NAND_REG(0x0008)
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#define MSM_NAND_FLASH_CHIP_SELECT MSM_NAND_REG(0x000C)
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#define MSM_NAND_EXEC_CMD MSM_NAND_REG(0x0010)
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#define MSM_NAND_FLASH_STATUS MSM_NAND_REG(0x0014)
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#define MSM_NAND_BUFFER_STATUS MSM_NAND_REG(0x0018)
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#define MSM_NAND_SFLASHC_STATUS MSM_NAND_REG(0x001C)
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#define MSM_NAND_DEV0_CFG0 MSM_NAND_REG(0x0020)
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#define MSM_NAND_DEV0_CFG1 MSM_NAND_REG(0x0024)
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#define MSM_NAND_DEV0_ECC_CFG MSM_NAND_REG(0x0028)
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#define MSM_NAND_DEV1_ECC_CFG MSM_NAND_REG(0x002C)
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#define MSM_NAND_DEV1_CFG0 MSM_NAND_REG(0x0030)
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#define MSM_NAND_DEV1_CFG1 MSM_NAND_REG(0x0034)
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#define MSM_NAND_SFLASHC_CMD MSM_NAND_REG(0x0038)
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#define MSM_NAND_SFLASHC_EXEC_CMD MSM_NAND_REG(0x003C)
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#define MSM_NAND_READ_ID MSM_NAND_REG(0x0040)
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#define MSM_NAND_READ_STATUS MSM_NAND_REG(0x0044)
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#define MSM_NAND_CONFIG_DATA MSM_NAND_REG(0x0050)
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#define MSM_NAND_CONFIG MSM_NAND_REG(0x0054)
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#define MSM_NAND_CONFIG_MODE MSM_NAND_REG(0x0058)
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#define MSM_NAND_CONFIG_STATUS MSM_NAND_REG(0x0060)
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#define MSM_NAND_MACRO1_REG MSM_NAND_REG(0x0064)
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#define MSM_NAND_XFR_STEP1 MSM_NAND_REG(0x0070)
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#define MSM_NAND_XFR_STEP2 MSM_NAND_REG(0x0074)
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#define MSM_NAND_XFR_STEP3 MSM_NAND_REG(0x0078)
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#define MSM_NAND_XFR_STEP4 MSM_NAND_REG(0x007C)
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#define MSM_NAND_XFR_STEP5 MSM_NAND_REG(0x0080)
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#define MSM_NAND_XFR_STEP6 MSM_NAND_REG(0x0084)
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#define MSM_NAND_XFR_STEP7 MSM_NAND_REG(0x0088)
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#define MSM_NAND_GENP_REG0 MSM_NAND_REG(0x0090)
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#define MSM_NAND_GENP_REG1 MSM_NAND_REG(0x0094)
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#define MSM_NAND_GENP_REG2 MSM_NAND_REG(0x0098)
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#define MSM_NAND_GENP_REG3 MSM_NAND_REG(0x009C)
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#define MSM_NAND_DEV_CMD0 MSM_NAND_REG(0x00A0)
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#define MSM_NAND_DEV_CMD1 MSM_NAND_REG(0x00A4)
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#define MSM_NAND_DEV_CMD2 MSM_NAND_REG(0x00A8)
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#define MSM_NAND_DEV_CMD_VLD MSM_NAND_REG(0x00AC)
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#define MSM_NAND_EBI2_MISR_SIG_REG MSM_NAND_REG(0x00B0)
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#define MSM_NAND_ADDR2 MSM_NAND_REG(0x00C0)
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#define MSM_NAND_ADDR3 MSM_NAND_REG(0x00C4)
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#define MSM_NAND_ADDR4 MSM_NAND_REG(0x00C8)
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#define MSM_NAND_ADDR5 MSM_NAND_REG(0x00CC)
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#define MSM_NAND_DEV_CMD3 MSM_NAND_REG(0x00D0)
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#define MSM_NAND_DEV_CMD4 MSM_NAND_REG(0x00D4)
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#define MSM_NAND_DEV_CMD5 MSM_NAND_REG(0x00D8)
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#define MSM_NAND_DEV_CMD6 MSM_NAND_REG(0x00DC)
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#define MSM_NAND_SFLASHC_BURST_CFG MSM_NAND_REG(0x00E0)
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#define MSM_NAND_ADDR6 MSM_NAND_REG(0x00E4)
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#define MSM_NAND_EBI2_ECC_BUF_CFG MSM_NAND_REG(0x00F0)
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#define MSM_NAND_HW_INFO MSM_NAND_REG(0x00FC)
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#define MSM_NAND_FLASH_BUFFER MSM_NAND_REG(0x0100)
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/* device commands */
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#define MSM_NAND_CMD_SOFT_RESET 0x01
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#define MSM_NAND_CMD_PAGE_READ 0x32
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#define MSM_NAND_CMD_PAGE_READ_ECC 0x33
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#define MSM_NAND_CMD_PAGE_READ_ALL 0x34
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#define MSM_NAND_CMD_SEQ_PAGE_READ 0x15
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#define MSM_NAND_CMD_PRG_PAGE 0x36
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#define MSM_NAND_CMD_PRG_PAGE_ECC 0x37
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#define MSM_NAND_CMD_PRG_PAGE_ALL 0x39
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#define MSM_NAND_CMD_BLOCK_ERASE 0x3A
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#define MSM_NAND_CMD_FETCH_ID 0x0B
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#define MSM_NAND_CMD_STATUS 0x0C
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#define MSM_NAND_CMD_RESET 0x0D
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/* Sflash Commands */
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#define MSM_NAND_SFCMD_DATXS 0x0
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#define MSM_NAND_SFCMD_CMDXS 0x1
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#define MSM_NAND_SFCMD_BURST 0x0
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#define MSM_NAND_SFCMD_ASYNC 0x1
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#define MSM_NAND_SFCMD_ABORT 0x1
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#define MSM_NAND_SFCMD_REGRD 0x2
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#define MSM_NAND_SFCMD_REGWR 0x3
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#define MSM_NAND_SFCMD_INTLO 0x4
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#define MSM_NAND_SFCMD_INTHI 0x5
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#define MSM_NAND_SFCMD_DATRD 0x6
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#define MSM_NAND_SFCMD_DATWR 0x7
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#define SFLASH_PREPCMD(numxfr, offval, delval, trnstp, mode, opcode) \
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((numxfr<<20)|(offval<<12)|(delval<<6)|(trnstp<<5)|(mode<<4)|opcode)
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#define SFLASH_BCFG 0x20100327
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/* Onenand addresses */
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#define ONENAND_MANUFACTURER_ID 0xF000
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#define ONENAND_DEVICE_ID 0xF001
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#define ONENAND_VERSION_ID 0xF002
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#define ONENAND_DATA_BUFFER_SIZE 0xF003
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#define ONENAND_BOOT_BUFFER_SIZE 0xF004
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#define ONENAND_AMOUNT_OF_BUFFERS 0xF005
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#define ONENAND_TECHNOLOGY 0xF006
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#define ONENAND_START_ADDRESS_1 0xF100
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#define ONENAND_START_ADDRESS_2 0xF101
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#define ONENAND_START_ADDRESS_3 0xF102
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#define ONENAND_START_ADDRESS_4 0xF103
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#define ONENAND_START_ADDRESS_5 0xF104
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#define ONENAND_START_ADDRESS_6 0xF105
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#define ONENAND_START_ADDRESS_7 0xF106
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#define ONENAND_START_ADDRESS_8 0xF107
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#define ONENAND_START_BUFFER 0xF200
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#define ONENAND_COMMAND 0xF220
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#define ONENAND_SYSTEM_CONFIG_1 0xF221
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#define ONENAND_SYSTEM_CONFIG_2 0xF222
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#define ONENAND_CONTROLLER_STATUS 0xF240
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#define ONENAND_INTERRUPT_STATUS 0xF241
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#define ONENAND_START_BLOCK_ADDRESS 0xF24C
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#define ONENAND_WRITE_PROT_STATUS 0xF24E
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#define ONENAND_ECC_STATUS 0xFF00
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#define ONENAND_ECC_ERRPOS_MAIN0 0xFF01
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#define ONENAND_ECC_ERRPOS_SPARE0 0xFF02
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#define ONENAND_ECC_ERRPOS_MAIN1 0xFF03
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#define ONENAND_ECC_ERRPOS_SPARE1 0xFF04
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#define ONENAND_ECC_ERRPOS_MAIN2 0xFF05
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#define ONENAND_ECC_ERRPOS_SPARE2 0xFF06
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#define ONENAND_ECC_ERRPOS_MAIN3 0xFF07
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#define ONENAND_ECC_ERRPOS_SPARE3 0xFF08
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/* Onenand commands */
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#define ONENAND_WP_US (1 << 2)
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#define ONENAND_WP_LS (1 << 1)
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#define ONENAND_CMDLOAD 0x0000
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#define ONENAND_CMDLOADSPARE 0x0013
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#define ONENAND_CMDPROG 0x0080
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#define ONENAND_CMDPROGSPARE 0x001A
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#define ONENAND_CMDERAS 0x0094
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#define ONENAND_CMD_UNLOCK 0x0023
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#define ONENAND_CMD_LOCK 0x002A
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#define ONENAND_SYSCFG1_ECCENA(mode) (0x40E0 | (mode ? 0 : 0x8002))
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#define ONENAND_SYSCFG1_ECCDIS(mode) (0x41E0 | (mode ? 0 : 0x8002))
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#define ONENAND_CLRINTR 0x0000
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#define ONENAND_STARTADDR1_RES 0x07FF
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#define ONENAND_STARTADDR3_RES 0x07FF
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#define DATARAM0_0 0x8
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#define DEVICE_FLASHCORE_0 (0 << 15)
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#define DEVICE_FLASHCORE_1 (1 << 15)
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#define DEVICE_BUFFERRAM_0 (0 << 15)
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#define DEVICE_BUFFERRAM_1 (1 << 15)
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#define ONENAND_DEVICE_IS_DDP (1 << 3)
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#define CLEAN_DATA_16 0xFFFF
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#define CLEAN_DATA_32 0xFFFFFFFF
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#define EBI2_REG(off) (ebi2_register_base + (off))
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#define EBI2_CHIP_SELECT_CFG0 EBI2_REG(0x0000)
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#define EBI2_CFG_REG EBI2_REG(0x0004)
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#define EBI2_NAND_ADM_MUX EBI2_REG(0x005C)
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extern struct flash_platform_data msm_nand_data;
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#endif
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@ -231,7 +231,7 @@ struct nand_oobfree {
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*/
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*/
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struct nand_ecclayout_user {
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struct nand_ecclayout_user {
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__u32 eccbytes;
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__u32 eccbytes;
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__u32 eccpos[MTD_MAX_ECCPOS_ENTRIES];
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__u32 eccpos[256];
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__u32 oobavail;
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__u32 oobavail;
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
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};
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};
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