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msm: kgsl: Watch SP_FS_FULL_ALU_INSTRUCTIONS for hang detection

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Some intensive shader operations can go for the full timeout
in the SP block without changes in th RBBM and CP registers
that we monitor for hang detection. Add the performance counter
SP_FS_FULL_ALU_INSTRUCTIONS to see if any full precision
instructions have been executed during the hang detection interval.

CRs-Fixed: 392730
Change-Id: Ic0dedbadd6e5bcd0b46aab4209430de2f74711f7
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
This commit is contained in:
Jordan Crouse 2012-10-03 09:38:41 -06:00 committed by Stephen Boyd
parent 2479fe88c0
commit 596e1d5efe
3 changed files with 31 additions and 0 deletions
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8
drivers/gpu/msm/a3xx_reg.h
View file

@ -65,13 +65,17 @@
#define A3XX_RBBM_INT_CLEAR_CMD 0x061
#define A3XX_RBBM_INT_0_MASK 0x063
#define A3XX_RBBM_INT_0_STATUS 0x064
#define A3XX_RBBM_PERFCTR_CTL 0x80
#define A3XX_RBBM_GPU_BUSY_MASKED 0x88
#define A3XX_RBBM_PERFCTR_SP_7_LO 0xE0
#define A3XX_RBBM_PERFCTR_SP_7_HI 0xE1
#define A3XX_RBBM_RBBM_CTL 0x100
#define A3XX_RBBM_RBBM_CTL 0x100
#define A3XX_RBBM_PERFCTR_PWR_1_LO 0x0EC
#define A3XX_RBBM_PERFCTR_PWR_1_HI 0x0ED
#define A3XX_RBBM_DEBUG_BUS_CTL 0x111
#define A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x112
/* Following two are same as on A2XX, just in a different place */
#define A3XX_CP_PFP_UCODE_ADDR 0x1C9
#define A3XX_CP_PFP_UCODE_DATA 0x1CA
@ -160,6 +164,7 @@
#define A3XX_VPC_VPC_DEBUG_RAM_READ 0xE62
#define A3XX_UCHE_CACHE_MODE_CONTROL_REG 0xE82
#define A3XX_UCHE_CACHE_INVALIDATE0_REG 0xEA0
#define A3XX_SP_PERFCOUNTER7_SELECT 0xECB
#define A3XX_GRAS_CL_CLIP_CNTL 0x2040
#define A3XX_GRAS_CL_GB_CLIP_ADJ 0x2044
#define A3XX_GRAS_CL_VPORT_XOFFSET 0x2048
@ -528,4 +533,7 @@
/* RBBM_CLOCK_CTL default value */
#define A3XX_RBBM_CLOCK_CTL_DEFAULT 0xBFFFFFFF
/* COUNTABLE FOR SP PERFCOUNTER */
#define SP_FS_FULL_ALU_INSTRUCTIONS 0x0E
#endif

12
drivers/gpu/msm/adreno.c
View file

@ -127,6 +127,8 @@ unsigned int hang_detect_regs[] = {
REG_CP_IB1_BUFSZ,
REG_CP_IB2_BASE,
REG_CP_IB2_BUFSZ,
0,
0
};
const unsigned int hang_detect_regs_count = ARRAY_SIZE(hang_detect_regs);
@ -1299,6 +1301,12 @@ static int adreno_start(struct kgsl_device *device, unsigned int init_ram)
*/
hang_detect_regs[0] = adreno_dev->gpudev->reg_rbbm_status;
/* Add A3XX specific registers for hang detection */
if (adreno_is_a3xx(adreno_dev)) {
hang_detect_regs[6] = A3XX_RBBM_PERFCTR_SP_7_LO;
hang_detect_regs[7] = A3XX_RBBM_PERFCTR_SP_7_HI;
}
status = kgsl_mmu_start(device);
if (status)
goto error_clk_off;
@ -2222,6 +2230,10 @@ unsigned int adreno_hang_detect(struct kgsl_device *device,
return 0;
for (i = 0; i < hang_detect_regs_count; i++) {
if (hang_detect_regs[i] == 0)
continue;
adreno_regread(device, hang_detect_regs[i],
&curr_reg_val[i]);
if (curr_reg_val[i] != prev_reg_val[i]) {

11
drivers/gpu/msm/adreno_a3xx.c
View file

@ -2831,6 +2831,17 @@ static void a3xx_start(struct adreno_device *adreno_dev)
adreno_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
(unsigned int)(adreno_dev->ocmem_base >> 14));
}
/* Turn on performance counters */
adreno_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);
/*
* Set SP perfcounter 7 to count SP_FS_FULL_ALU_INSTRUCTIONS
* we will use this to augment our hang detection
*/
adreno_regwrite(device, A3XX_SP_PERFCOUNTER7_SELECT,
SP_FS_FULL_ALU_INSTRUCTIONS);
}
/* Defined in adreno_a3xx_snapshot.c */