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Display: fine tune power on sequence

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3V3 is always high in spec, so we need to delay more time after 3V3 on

Change-Id: Iab0ecaecefb98cc6bae441381d233759b235e2ba
Reviewed-on: http://mcrd1-5.corpnet.asus/code-review/master/68839
Reviewed-by: Yetta Wu <Yetta_Wu@asus.com>
Tested-by: Yetta Wu <Yetta_Wu@asus.com>
Reviewed-by: Sam hblee <Sam_hblee@asus.com>
This commit is contained in:
yetta_wu 2013-02-08 18:43:33 +08:00 committed by Iliyan Malchev
parent 727f62401f
commit 6babf27f3d
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-msm/asustek/flo/board-flo-display.c
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@ -458,14 +458,14 @@ static int mipi_dsi_panel_power(int on)
}
gpio_set_value_cansleep(gpio_EN_VDD_BL, 1);
msleep(20);
msleep(210);
gpio_set_value_cansleep(gpio_LCD_BL_EN, 1);
msleep(20);
} else {
msleep(20);
gpio_set_value_cansleep(gpio_LCD_BL_EN, 0);
msleep(20);
msleep(210);
gpio_set_value_cansleep(gpio_EN_VDD_BL, 0);
rc = regulator_disable(reg_l17);