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https://github.com/followmsi/android_kernel_google_msm.git
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r8169: merge with version 6.001.00 of Realtek's r8169 driver
- new identifier for the 8110SCe - the PCI latency timer is set unconditionally. This part is identical in Realtek's r8168 (8.001.00) and r8101 (1.001.00) - initialization of the cache line size register is for the 8169s only - more magic in rtl_hw_start_8169 - it is not possible to factor out the setting of the the irq event mask with the 8168 and the 8101 any more. Pushed it into the hw_start handler. - rtl_set_rx_tx_config_registers() and write to the ChipCmd register are issued identically for the whole 8169/8110 family: the 8110SCd/8110SCe are handled the same way - work around for AMD platform. Some registers definitions in Realtek's driver are let aside for later. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
This commit is contained in:
Francois Romieu
Jeff Garzik
parent
ba6eb6ee85
commit
6dccd16b7c
1 changed files with 55 additions and 35 deletions
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@ -156,6 +156,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
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RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
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RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
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RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
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RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
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RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
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RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
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@ -185,6 +186,7 @@ static const struct {
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_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
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_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
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@ -328,6 +330,10 @@ enum RTL8169_register_content {
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/* Config1 register p.24 */
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PMEnable = (1 << 0), /* Power Management Enable */
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/* Config2 register p. 25 */
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PCI_Clock_66MHz = 0x01,
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PCI_Clock_33MHz = 0x00,
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/* Config3 register p.25 */
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MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
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LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
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@ -1169,6 +1175,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
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{ 0x34000000, RTL_GIGA_MAC_VER_13 },
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{ 0x30800000, RTL_GIGA_MAC_VER_14 },
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{ 0x30000000, RTL_GIGA_MAC_VER_11 },
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{ 0x98000000, RTL_GIGA_MAC_VER_06 },
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{ 0x18000000, RTL_GIGA_MAC_VER_05 },
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{ 0x10000000, RTL_GIGA_MAC_VER_04 },
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{ 0x04000000, RTL_GIGA_MAC_VER_03 },
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@ -1177,7 +1184,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
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}, *p = mac_info;
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u32 reg;
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reg = RTL_R32(TxConfig) & 0x7c800000;
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reg = RTL_R32(TxConfig) & 0xfc800000;
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while ((reg & p->mask) != p->mask)
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p++;
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tp->mac_version = p->mac_version;
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@ -1425,10 +1432,10 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
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dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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RTL_W8(0x82, 0x01);
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if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
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dprintk("Set PCI Latency=0x40\n");
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pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
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}
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pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
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if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
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pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
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if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
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dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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@ -1844,9 +1851,6 @@ static void rtl_hw_start(struct net_device *dev)
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tp->hw_start(dev);
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/* Enable all known interrupts by setting the interrupt mask. */
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RTL_W16(IntrMask, rtl8169_intr_mask);
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netif_start_queue(dev);
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}
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@ -1880,31 +1884,41 @@ static void rtl_set_rx_max_size(void __iomem *ioaddr)
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RTL_W16(RxMaxSize, 16383);
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}
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static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
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{
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struct {
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u32 mac_version;
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u32 clk;
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u32 val;
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} cfg2_info [] = {
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{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
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{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
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{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
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{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
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}, *p = cfg2_info;
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unsigned int i;
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u32 clk;
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clk = RTL_R8(Config2) & PCI_Clock_66MHz;
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for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
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if ((p->mac_version == mac_version) && (p->clk == clk)) {
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RTL_W32(0x7c, p->val);
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break;
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}
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}
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}
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static void rtl_hw_start_8169(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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void __iomem *ioaddr = tp->mmio_addr;
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struct pci_dev *pdev = tp->pci_dev;
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u16 cmd;
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if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
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RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
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}
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/* Undocumented stuff. */
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if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
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/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
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if ((RTL_R8(Config2) & 0x07) & 0x01)
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RTL_W32(0x7c, 0x0007ffff);
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RTL_W32(0x7c, 0x0007ff00);
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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cmd = cmd & 0xef;
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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RTL_W8(Cfg9346, Cfg9346_Unlock);
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if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_02) ||
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@ -1916,11 +1930,7 @@ static void rtl_hw_start_8169(struct net_device *dev)
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rtl_set_rx_max_size(ioaddr);
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if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_02) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_03) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_04))
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rtl_set_rx_tx_config_registers(tp);
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rtl_set_rx_tx_config_registers(tp);
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tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
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@ -1933,6 +1943,8 @@ static void rtl_hw_start_8169(struct net_device *dev)
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RTL_W16(CPlusCmd, tp->cp_cmd);
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rtl8169_set_magic_reg(ioaddr, tp->mac_version);
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/*
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* Undocumented corner. Supposedly:
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* (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
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@ -1941,14 +1953,6 @@ static void rtl_hw_start_8169(struct net_device *dev)
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rtl_set_rx_tx_desc_registers(tp, ioaddr);
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if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_02) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_03) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_04)) {
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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rtl_set_rx_tx_config_registers(tp);
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}
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RTL_W8(Cfg9346, Cfg9346_Lock);
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/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
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@ -1960,6 +1964,11 @@ static void rtl_hw_start_8169(struct net_device *dev)
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/* no early-rx interrupts */
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RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
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/* Enable all known interrupts by setting the interrupt mask. */
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RTL_W16(IntrMask, rtl8169_intr_mask);
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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@ -1993,6 +2002,8 @@ static void rtl_hw_start_8168(struct net_device *dev)
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rtl_set_rx_mode(dev);
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RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
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RTL_W16(IntrMask, rtl8169_intr_mask);
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}
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static void rtl_hw_start_8101(struct net_device *dev)
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@ -2032,6 +2043,8 @@ static void rtl_hw_start_8101(struct net_device *dev)
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rtl_set_rx_mode(dev);
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RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
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RTL_W16(IntrMask, rtl8169_intr_mask);
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}
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static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
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@ -2689,6 +2702,13 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
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tp->stats.rx_bytes += pkt_size;
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tp->stats.rx_packets++;
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}
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/* Work around for AMD plateform. */
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if ((desc->opts2 & 0xfffe000) &&
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(tp->mac_version == RTL_GIGA_MAC_VER_05)) {
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desc->opts2 = 0;
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cur_rx++;
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}
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}
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count = cur_rx - tp->cur_rx;
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