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msm_fb: display: Fix Toshiba WSVGA panel porch and timing settings

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Fix the porch and timing settings for DSI Toshiba WSVGA panel
to enable writeback mode switch efficiently.

Signed-off-by: Ravishangar Kalyanam <rkalya@codeaurora.org>
Change-Id: Ib768d13617470f75ae027970c6ca4779d6b5a367
This commit is contained in:
Ravishangar Kalyanam 2012-06-22 18:46:33 -07:00 committed by Stephen Boyd
parent 06ca4a6eb4
commit 700b3607ce
1 changed files with 7 additions and 8 deletions
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15
drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
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@ -22,14 +22,14 @@ static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* regulator */
{0x09, 0x08, 0x05, 0x00, 0x20},
/* timing */
{0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
0x0c, 0x03, 0x04, 0xa0},
{0x73, 0x2e, 0x11, 0x00, 0x3c, 0x46, 0x14, 0x31,
0x1c, 0x03, 0x04, 0xa0},
/* phy ctrl */
{0x5f, 0x00, 0x00, 0x10},
/* strength */
{0xff, 0x00, 0x06, 0x00},
/* pll control */
{0x0, 0x7f, 0x31, 0xda, 0x00, 0x50, 0x48, 0x63,
{0x0, 0x49, 0x30, 0xc4, 0x00, 0x20, 0x07, 0x62,
0x41, 0x0f, 0x01,
0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 },
};
@ -59,8 +59,8 @@ static int __init mipi_video_toshiba_wsvga_pt_init(void)
pinfo.lcdc.h_back_porch = 16;
pinfo.lcdc.h_front_porch = 23;
pinfo.lcdc.h_pulse_width = 8;
pinfo.lcdc.v_back_porch = 2;
pinfo.lcdc.v_front_porch = 7;
pinfo.lcdc.v_back_porch = 3;
pinfo.lcdc.v_front_porch = 45;
pinfo.lcdc.v_pulse_width = 2;
pinfo.lcdc.border_clr = 0; /* blk */
pinfo.lcdc.underflow_clr = 0xff; /* blue */
@ -68,7 +68,6 @@ static int __init mipi_video_toshiba_wsvga_pt_init(void)
pinfo.bl_max = MIPI_TOSHIBA_PWM_LEVEL;
pinfo.bl_min = 1;
pinfo.fb_num = 2;
pinfo.clk_rate = 384000000;
pinfo.mipi.mode = DSI_VIDEO_MODE;
pinfo.mipi.pulse_mode_hsa_he = FALSE;
@ -84,8 +83,8 @@ static int __init mipi_video_toshiba_wsvga_pt_init(void)
pinfo.mipi.data_lane0 = TRUE;
pinfo.mipi.data_lane1 = TRUE;
pinfo.mipi.data_lane2 = TRUE;
pinfo.mipi.t_clk_post = 0x20;
pinfo.mipi.t_clk_pre = 0x2d;
pinfo.mipi.t_clk_post = 0x04;
pinfo.mipi.t_clk_pre = 0x1a;
pinfo.mipi.esc_byte_ratio = 4;
pinfo.mipi.stream = 0; /* dma_p */
pinfo.mipi.mdp_trigger = 0;