Piteball/android_kernel_google_msm
1
0
Fork 0
mirror of https://github.com/followmsi/android_kernel_google_msm.git synced 2024-11-06 23:17:41 +00:00
Code Issues Projects Releases Wiki Activity

gpio: msm-v3: Clear the reset state before configuring a gpio interrupt

Browse source 
The reset state for the INTR_CFG register is 0xE2. We need
the upper nibble to specify the target processor for the
gpio interrupt (Value 0x4 for APPS). But we were ORing
0x4 with 0xE still keeps it as 0xE. Get rid of the
incorrect read, modify, write cycle. Make sure the
reset state is wiped off before setting the interrupt
configuration bits.

Change-Id: I3deee9fcebe9eec78f89635313c5f3d0923fede5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
This commit is contained in:
Rohit Vaswani 2012-08-13 21:09:22 -07:00 committed by Stephen Boyd
parent 59135e2bf0
commit 76aa02ebad
1 changed files with 1 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/gpio/gpio-msm-v3.c
View file

@ -167,15 +167,12 @@ void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type)
{
unsigned cfg;
cfg = __raw_readl(GPIO_INTR_CFG(gpio));
/* RAW_STATUS_EN is left on for all gpio irqs. Due to the
* internal circuitry of TLMM, toggling the RAW_STATUS
* could cause the INTR_STATUS to be set for EDGE interrupts.
*/
cfg |= (INTR_RAW_STATUS_EN | INTR_TARGET_PROC_APPS);
cfg = INTR_RAW_STATUS_EN | INTR_TARGET_PROC_APPS;
__raw_writel(cfg, GPIO_INTR_CFG(gpio));
cfg = __raw_readl(GPIO_INTR_CFG(gpio));
cfg &= ~INTR_DECT_CTL_MASK;
if (type == IRQ_TYPE_EDGE_RISING)
cfg |= INTR_DECT_CTL_POS_EDGE;