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ARM: cleanups of io includes 

Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes,
 moving some of the oft-repeated macros to a common location and removing a bunch of
 boiler plate. This is another step closer to a common zImage for multiple platforms.
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Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull "ARM: cleanups of io includes" from Olof Johansson:
 "Rob Herring has done a sweeping change cleaning up all of the
  mach/io.h includes, moving some of the oft-repeated macros to a common
  location and removing a bunch of boiler plate.  This is another step
  closer to a common zImage for multiple platforms."

Fix up various fairly trivial conflicts (<mach/io.h> removal vs changes
around it, tegra localtimer.o is *still* gone, yadda-yadda).

* tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits)
  ARM: tegra: Include assembler.h in sleep.S to fix build break
  ARM: pxa: use common IOMEM definition
  ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
  ARM: __io abuse cleanup
  ARM: create a common IOMEM definition
  ARM: iop13xx: fix missing declaration of iop13xx_init_early
  ARM: fix ioremap/iounmap for !CONFIG_MMU
  ARM: kill off __mem_pci
  ARM: remove bunch of now unused mach/io.h files
  ARM: make mach/io.h include optional
  ARM: clps711x: remove unneeded include of mach/io.h
  ARM: dove: add explicit include of dove.h to addr-map.c
  ARM: at91: add explicit include of hardware.h to uncompressor
  ARM: ep93xx: clean-up mach/io.h
  ARM: tegra: clean-up mach/io.h
  ARM: orion5x: clean-up mach/io.h
  ARM: davinci: remove unneeded mach/io.h include
  [media] davinci: remove includes of mach/io.h
  ARM: OMAP: Remove remaining includes for mach/io.h
  ARM: msm: clean-up mach/io.h
  ...
This commit is contained in:
Linus Torvalds 2012-03-29 18:02:10 -07:00
parent 6268b325c3 88b48684fe
commit 820d41cf0c
162 changed files with 336 additions and 1365 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/Kconfig
View File

@ -179,6 +179,9 @@ config ZONE_DMA
config NEED_DMA_MAP_STATE
def_bool y
config ARCH_HAS_DMA_SET_COHERENT_MASK
bool
config GENERIC_ISA_DMA
bool
@ -216,6 +219,13 @@ config ARM_PATCH_PHYS_VIRT
this feature (eg, building a kernel for a single machine) and
you need to shrink the kernel to the minimal size.
config NEED_MACH_IO_H
bool
help
Select this when mach/io.h is required to provide special
definitions for this platform. The need for mach/io.h should
be avoided when possible.
config NEED_MACH_MEMORY_H
bool
help
@ -267,6 +277,7 @@ config ARCH_INTEGRATOR
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
select PLAT_VERSATILE_FPGA_IRQ
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
help
@ -406,6 +417,7 @@ config ARCH_EBSA110
select ISA
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
This is an evaluation board for the StrongARM processor available
@ -432,6 +444,7 @@ config ARCH_FOOTBRIDGE
select FOOTBRIDGE
select GENERIC_CLOCKEVENTS
select HAVE_IDE
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
Support for systems based on the DC21285 companion chip
@ -483,6 +496,7 @@ config ARCH_IOP13XX
select PCI
select ARCH_SUPPORTS_MSI
select VMSPLIT_1G
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select NEED_RET_TO_USER
help
@ -492,6 +506,7 @@ config ARCH_IOP32X
bool "IOP32x-based"
depends on MMU
select CPU_XSCALE
select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
@ -504,6 +519,7 @@ config ARCH_IOP33X
bool "IOP33x-based"
depends on MMU
select CPU_XSCALE
select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
@ -517,6 +533,7 @@ config ARCH_IXP23XX
select CPU_XSC3
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
Support for Intel's IXP23xx (XScale) family of processors.
@ -527,6 +544,7 @@ config ARCH_IXP2000
select CPU_XSCALE
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
Support for Intel's IXP2400/2800 (XScale) family of processors.
@ -534,11 +552,13 @@ config ARCH_IXP2000
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
select ARCH_HAS_DMA_SET_COHERENT_MASK
select CLKSRC_MMIO
select CPU_XSCALE
select GENERIC_GPIO
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select NEED_MACH_IO_H
select DMABOUNCE if PCI
help
Support for Intel's IXP4XX (XScale) family of processors.
@ -549,6 +569,7 @@ config ARCH_DOVE
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the Marvell Dove SoC 88AP510
@ -559,6 +580,7 @@ config ARCH_KIRKWOOD
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the following Marvell Kirkwood series SoCs:
@ -583,6 +605,7 @@ config ARCH_MV78XX0
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the following Marvell MV78xx0 series SoCs:
@ -650,6 +673,7 @@ config ARCH_TEGRA
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select NEED_MACH_IO_H if PCI
select ARCH_HAS_CPUFREQ
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
@ -741,6 +765,7 @@ config ARCH_RPC
select ARCH_SPARSEMEM_ENABLE
select ARCH_USES_GETTIMEOFFSET
select HAVE_IDE
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
@ -775,6 +800,7 @@ config ARCH_S3C24XX
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select NEED_MACH_IO_H
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@ -876,6 +902,7 @@ config ARCH_SHARK
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
select NEED_MACH_IO_H
help
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).

2
arch/arm/include/asm/assembler.h
View File

@ -23,6 +23,8 @@
#include <asm/ptrace.h>
#include <asm/domain.h>
#define IOMEM(x) (x)
/*
* Endian independent macros for shifting bytes within registers.
*/

71
arch/arm/include/asm/io.h
View File

@ -82,6 +82,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
extern void __iounmap(volatile void __iomem *addr);
extern void __arm_iounmap(volatile void __iomem *addr);
extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
unsigned int, void *);
extern void (*arch_iounmap)(volatile void __iomem *);
/*
* Bad read/write accesses...
@ -96,6 +101,8 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
return (void __iomem *)addr;
}
#define IOMEM(x) ((void __force __iomem *)(x))
/* IO barriers */
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
#include <asm/barrier.h>
@ -109,7 +116,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
/*
* Now, pick up the machine-defined IO definitions
*/
#ifdef CONFIG_NEED_MACH_IO_H
#include <mach/io.h>
#else
#define __io(a) ({ (void)(a); __typesafe_io(0); })
#endif
/*
* This is the limit of PC card/PCI/ISA IO space, which is by default
@ -211,18 +222,18 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
* Again, this are defined to perform little endian accesses. See the
* IO port primitives for more information.
*/
#ifdef __mem_pci
#define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; })
#ifndef readl
#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
__raw_readw(__mem_pci(c))); __r; })
__raw_readw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
__raw_readl(__mem_pci(c))); __r; })
__raw_readl(c)); __r; })
#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c)))
#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
cpu_to_le16(v),__mem_pci(c)))
cpu_to_le16(v),c))
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
cpu_to_le32(v),__mem_pci(c)))
cpu_to_le32(v),c))
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
@ -232,30 +243,19 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
#define readsb(p,d,l) __raw_readsb(p,d,l)
#define readsw(p,d,l) __raw_readsw(p,d,l)
#define readsl(p,d,l) __raw_readsl(p,d,l)
#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
#define writesb(p,d,l) __raw_writesb(p,d,l)
#define writesw(p,d,l) __raw_writesw(p,d,l)
#define writesl(p,d,l) __raw_writesl(p,d,l)
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
#define memset_io(c,v,l) _memset_io(c,(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
#elif !defined(readb)
#define readb(c) (__readwrite_bug("readb"),0)
#define readw(c) (__readwrite_bug("readw"),0)
#define readl(c) (__readwrite_bug("readl"),0)
#define writeb(v,c) __readwrite_bug("writeb")
#define writew(v,c) __readwrite_bug("writew")
#define writel(v,c) __readwrite_bug("writel")
#define check_signature(io,sig,len) (0)
#endif /* __mem_pci */
#endif /* readl */
/*
* ioremap and friends.
@ -264,16 +264,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
* Documentation/io-mapping.txt.
*
*/
#ifndef __arch_ioremap
#define __arch_ioremap __arm_ioremap
#define __arch_iounmap __iounmap
#endif
#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
#define iounmap __arch_iounmap
#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
#define iounmap __arm_iounmap
/*
* io{read,write}{8,16,32} macros

1
arch/arm/kernel/debug.S
View File

@ -10,6 +10,7 @@
* 32-bit debugging code
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text

1
arch/arm/kernel/entry-armv.S
View File

@ -15,6 +15,7 @@
* that causes it to save wrong values... Be aware!
*/
#include <asm/assembler.h>
#include <asm/memory.h>
#include <asm/glue-df.h>
#include <asm/glue-pf.h>

31
arch/arm/mach-at91/include/mach/io.h
View File

@ -1,31 +0,0 @@
/*
* arch/arm/mach-at91/include/mach/io.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-at91/include/mach/uncompress.h
View File

@ -23,6 +23,7 @@
#include <linux/io.h>
#include <linux/atmel_serial.h>
#include <mach/hardware.h>
#if defined(CONFIG_AT91_EARLY_DBGU0)
#define UART_OFFSET AT91_BASE_DBGU0

33
arch/arm/mach-bcmring/include/mach/io.h
View File

@ -1,33 +0,0 @@
/*
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

36
arch/arm/mach-clps711x/include/mach/io.h
View File

@ -1,36 +0,0 @@
/*
* arch/arm/mach-clps711x/include/mach/io.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
/*
* We don't support ins[lb]/outs[lb]. Make them fault.
*/
#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0)
#endif

1
arch/arm/mach-clps711x/include/mach/uncompress.h
View File

@ -17,7 +17,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <mach/io.h>
#include <mach/hardware.h>
#include <asm/hardware/clps7111.h>

8
arch/arm/mach-cns3xxx/core.c
View File

@ -72,13 +72,13 @@ void __init cns3xxx_map_io(void)
/* used by entry-macro.S */
void __init cns3xxx_init_irq(void)
{
gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
__io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
}
void cns3xxx_power_off(void)
{
u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
u32 clkctrl;
printk(KERN_INFO "powering system down...\n");
@ -237,7 +237,7 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
static void __init cns3xxx_timer_init(void)
{
cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
}

2
arch/arm/mach-cns3xxx/devices.c
View File

@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sdhci_pdev = {
void __init cns3xxx_sdhci_init(void)
{
u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */

17
arch/arm/mach-cns3xxx/include/mach/io.h
View File

@ -1,17 +0,0 @@
/*
* Copyright 2008 Cavium Networks
* Copyright 2003 ARM Limited
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_IO_H
#define __MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-davinci/include/mach/entry-macro.S
View File

@ -8,7 +8,6 @@
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <mach/io.h>
#include <mach/irqs.h>
.macro get_irqnr_preamble, base, tmp

6
arch/arm/mach-davinci/include/mach/hardware.h
View File

@ -30,10 +30,4 @@
#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
#ifdef __ASSEMBLER__
#define IOMEM(x) x
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#endif /* __ASM_ARCH_HARDWARE_H */

24
arch/arm/mach-davinci/include/mach/io.h
View File

@ -1,24 +0,0 @@
/*
* DaVinci IO address definitions
*
* Copied from include/asm/arm/arch-omap/io.h
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif /* __ASM_ARCH_IO_H */

2
arch/arm/mach-davinci/include/mach/uncompress.h
View File

@ -25,6 +25,8 @@
#include <mach/serial.h>
#define IOMEM(x) ((void __force __iomem *)(x))
u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */

1
arch/arm/mach-dove/addr-map.c
View File

@ -14,6 +14,7 @@
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
#include <mach/dove.h>
#include <plat/addr-map.h>
#include "common.h"

1
arch/arm/mach-dove/include/mach/io.h
View File

@ -15,6 +15,5 @@
#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
DOVE_PCIE0_IO_VIRT_BASE))
#define __mem_pci(a) (a)
#endif

15
arch/arm/mach-ebsa110/core.c
View File

@ -116,6 +116,20 @@ static void __init ebsa110_map_io(void)
iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
}
static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
unsigned int flags, void *caller)
{
return (void __iomem *)cookie;
}
static void ebsa110_iounmap(volatile void __iomem *io_addr)
{}
static void __init ebsa110_init_early(void)
{
arch_ioremap_caller = ebsa110_ioremap_caller;
arch_iounmap = ebsa110_iounmap;
}
#define PIT_CTRL (PIT_BASE + 0x0d)
#define PIT_T2 (PIT_BASE + 0x09)
@ -312,6 +326,7 @@ MACHINE_START(EBSA110, "EBSA110")
.reserve_lp2 = 1,
.restart_mode = 's',
.map_io = ebsa110_map_io,
.init_early = ebsa110_init_early,
.init_irq = ebsa110_init_irq,
.timer = &ebsa110_timer,
.restart = ebsa110_restart,

9
arch/arm/mach-ebsa110/include/mach/io.h
View File

@ -62,15 +62,6 @@ void __writel(u32 val, void __iomem *addr);
#define writew(v,b) __writew(v,b)
#define writel(v,b) __writel(v,b)
static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
unsigned int flags)
{
return (void __iomem *)cookie;
}
#define __arch_ioremap __arch_ioremap
#define __arch_iounmap(cookie) do { } while (0)
extern void insb(unsigned int port, void *buf, int sz);
extern void insw(unsigned int port, void *buf, int sz);
extern void insl(unsigned int port, void *buf, int sz);

22
arch/arm/mach-ep93xx/include/mach/io.h
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-ep93xx/include/mach/io.h
*/
#ifndef __ASM_MACH_IO_H
#define __ASM_MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) __typesafe_io(p)
#define __mem_pci(p) (p)
/*
* A typesafe __io() variation for variable initialisers
*/
#ifdef __ASSEMBLER__
#define IOMEM(p) p
#else
#define IOMEM(p) ((void __iomem __force *)(p))
#endif
#endif /* __ASM_MACH_IO_H */

26
arch/arm/mach-exynos/include/mach/io.h
View File

@ -1,26 +0,0 @@
/* linux/arch/arm/mach-exynos4/include/mach/io.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
*
* Based on arch/arm/mach-s5p6442/include/mach/io.h
*
* Default IO routines for EXYNOS4
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H __FILE__
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif /* __ASM_ARM_ARCH_IO_H */

13
arch/arm/mach-footbridge/include/mach/io.h
View File

@ -27,18 +27,5 @@
* Translation of various region addresses to virtual addresses
*/
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#if 1
#define __mem_pci(a) (a)
#else
static inline void __iomem *___mem_pci(void __iomem *p)
{
unsigned long a = (unsigned long)p;
BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
return p;
}
#define __mem_pci(a) ___mem_pci(a)
#endif
#endif

18
arch/arm/mach-gemini/include/mach/io.h
View File

@ -1,18 +0,0 @@
/*
* Copyright (C) 2001-2006 Storlink, Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __MACH_IO_H
#define __MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif /* __MACH_IO_H */

22
arch/arm/mach-h720x/include/mach/io.h
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-h720x/include/mach/io.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
*
* 09-19-2001 JJKIM
* Created from arch/arm/mach-l7200/include/mach/io.h
*
* 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>:
* re-unified header files for h720x
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

7
arch/arm/mach-highbank/include/mach/io.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_IO_H
#define __MACH_IO_H
#define __io(a) ({ (void)(a); __typesafe_io(0); })
#define __mem_pci(a) (a)
#endif

10
arch/arm/mach-imx/mm-imx3.c
View File

@ -61,8 +61,8 @@ static void imx3_idle(void)
: "=r" (reg));
}
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
unsigned int mtype)
static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
unsigned int mtype, void *caller)
{
if (mtype == MT_DEVICE) {
/*
@ -75,7 +75,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap(phys_addr, size, mtype);
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
void __init imx3_init_l2x0(void)
@ -134,7 +134,7 @@ void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
imx_ioremap = imx3_ioremap;
arch_ioremap_caller = imx3_ioremap_caller;
arm_pm_idle = imx3_idle;
}
@ -208,7 +208,7 @@ void __init imx35_init_early(void)
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
arm_pm_idle = imx3_idle;
imx_ioremap = imx3_ioremap;
arch_ioremap_caller = imx3_ioremap_caller;
}
void __init mx35_init_irq(void)

1
arch/arm/mach-integrator/include/mach/io.h
View File

@ -29,6 +29,5 @@
#define PCI_IO_VADDR 0xee000000
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_pci(a) (a)
#endif

13
arch/arm/mach-iop13xx/include/mach/io.h
View File

@ -22,20 +22,7 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __iop13xx_io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
extern void __iomem * __iop13xx_io(unsigned long io_addr);
extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
unsigned int mtype);
extern void __iop13xx_iounmap(void __iomem *addr);
extern u32 iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
#define __arch_ioremap __iop13xx_ioremap
#define __arch_iounmap __iop13xx_iounmap
#endif

1
arch/arm/mach-iop13xx/include/mach/iop13xx.h
View File

@ -5,6 +5,7 @@
/* The ATU offsets can change based on the strapping */
extern u32 iop13xx_atux_pmmr_offset;
extern u32 iop13xx_atue_pmmr_offset;
void iop13xx_init_early(void);
void iop13xx_init_irq(void);
void iop13xx_map_io(void);
void iop13xx_platform_init(void);

20
arch/arm/mach-iop13xx/io.c
View File

@ -21,6 +21,8 @@
#include <linux/io.h>
#include <mach/hardware.h>
#include "pci.h"
void * __iomem __iop13xx_io(unsigned long io_addr)
{
void __iomem * io_virt;
@ -40,8 +42,8 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
}
EXPORT_SYMBOL(__iop13xx_io);
void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
unsigned int mtype)
static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
size_t size, unsigned int mtype, void *caller)
{
void __iomem * retval;
@ -76,17 +78,14 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
break;
default:
retval = __arm_ioremap_caller(cookie, size, mtype,
__builtin_return_address(0));
caller);
}
return retval;
}
EXPORT_SYMBOL(__iop13xx_ioremap);
void __iop13xx_iounmap(void __iomem *addr)
static void __iop13xx_iounmap(volatile void __iomem *addr)
{
extern void __iounmap(volatile void __iomem *addr);
if (iop13xx_atue_mem_base)
if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
addr < (void __iomem *) (iop13xx_atue_mem_base +
@ -110,4 +109,9 @@ void __iop13xx_iounmap(void __iomem *addr)
skip:
return;
}
EXPORT_SYMBOL(__iop13xx_iounmap);
void __init iop13xx_init_early(void)
{
arch_ioremap_caller = __iop13xx_ioremap_caller;
arch_iounmap = __iop13xx_iounmap;
}

1
arch/arm/mach-iop13xx/iq81340mc.c
View File

@ -92,6 +92,7 @@ static struct sys_timer iq81340mc_timer = {
MACHINE_START(IQ81340MC, "Intel IQ81340MC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.atag_offset = 0x100,
.init_early = iop13xx_init_early,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.timer = &iq81340mc_timer,

1
arch/arm/mach-iop13xx/iq81340sc.c
View File

@ -94,6 +94,7 @@ static struct sys_timer iq81340sc_timer = {
MACHINE_START(IQ81340SC, "Intel IQ81340SC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.atag_offset = 0x100,
.init_early = iop13xx_init_early,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.timer = &iq81340sc_timer,

6
arch/arm/mach-iop13xx/pci.h Normal file
View File

@ -0,0 +1,6 @@
#include <linux/types.h>
extern u32 iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;

1
arch/arm/mach-iop32x/include/mach/io.h
View File

@ -15,6 +15,5 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-iop33x/include/mach/io.h
View File

@ -15,6 +15,5 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-ixp2000/include/mach/io.h
View File

@ -18,7 +18,6 @@
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) (a)
/*
* The A? revisions of the IXP2000s assert byte lanes for PCI I/O

1
arch/arm/mach-ixp23xx/include/mach/io.h
View File

@ -18,6 +18,5 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
#define __mem_pci(a) (a)
#endif

2
arch/arm/mach-ixp4xx/avila-setup.c
View File

@ -165,6 +165,7 @@ static void __init avila_init(void)
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
/* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,
@ -184,6 +185,7 @@ MACHINE_END
MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
/* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

33
arch/arm/mach-ixp4xx/common.c
View File

@ -31,6 +31,7 @@
#include <mach/udc.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/page.h>
@ -517,3 +518,35 @@ void ixp4xx_restart(char mode, const char *cmd)
*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
}
}
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
/*
* In the case of using indirect PCI, we simply return the actual PCI
* address and our read/write implementation use that to drive the
* access registers. If something outside of PCI is ioremap'd, we
* fallback to the default.
*/
static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
unsigned int mtype, void *caller)
{
if (!is_pci_memory(addr))
return __arm_ioremap_caller(addr, size, mtype, caller);
return (void __iomem *)addr;
}
static void ixp4xx_iounmap(void __iomem *addr)
{
if (!is_pci_memory((__force u32)addr))
__iounmap(addr);
}
void __init ixp4xx_init_early(void)
{
arch_ioremap_caller = ixp4xx_ioremap_caller;
arch_iounmap = ixp4xx_iounmap;
}
#else
void __init ixp4xx_init_early(void) {}
#endif

2
arch/arm/mach-ixp4xx/coyote-setup.c
View File

@ -110,6 +110,7 @@ static void __init coyote_init(void)
MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,
@ -129,6 +130,7 @@ MACHINE_END
MACHINE_START(IXDPG425, "Intel IXDPG425")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/dsmg600-setup.c
View File

@ -280,6 +280,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &dsmg600_timer,
.init_machine = dsmg600_init,

1
arch/arm/mach-ixp4xx/fsg-setup.c
View File

@ -270,6 +270,7 @@ static void __init fsg_init(void)
MACHINE_START(FSG, "Freecom FSG-3")
/* Maintainer: www.nslu2-linux.org */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/gateway7001-setup.c
View File

@ -97,6 +97,7 @@ static void __init gateway7001_init(void)
MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/goramo_mlr.c
View File

@ -496,6 +496,7 @@ subsys_initcall(gmlr_pci_init);
MACHINE_START(GORAMO_MLR, "MultiLink")
/* Maintainer: Krzysztof Halasa */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/gtwx5715-setup.c
View File

@ -165,6 +165,7 @@ static void __init gtwx5715_init(void)
MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
/* Maintainer: George Joseph */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

2
arch/arm/mach-ixp4xx/include/mach/hardware.h
View File

@ -23,8 +23,6 @@
#define PCIBIOS_MAX_MEM 0x4BFFFFFF
#endif
#define ARCH_HAS_DMA_SET_COHERENT_MASK
/* Register locations and bits */
#include "ixp4xx-regs.h"

24
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -39,11 +39,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* but in some cases the performance hit is acceptable. In addition, you
* cannot mmap() PCI devices in this case.
*/
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
#define __mem_pci(a) (a)
#else
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
/*
* In the case of using indirect PCI, we simply return the actual PCI
@ -57,24 +53,6 @@ static inline int is_pci_memory(u32 addr)
return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
}
static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
unsigned int mtype)
{
if (!is_pci_memory(addr))
return __arm_ioremap(addr, size, mtype);
return (void __iomem *)addr;
}
static inline void __indirect_iounmap(void __iomem *addr)
{
if (!is_pci_memory((__force u32)addr))
__iounmap(addr);
}
#define __arch_ioremap __indirect_ioremap
#define __arch_iounmap __indirect_iounmap
#define writeb(v, p) __indirect_writeb(v, p)
#define writew(v, p) __indirect_writew(v, p)
#define writel(v, p) __indirect_writel(v, p)

1
arch/arm/mach-ixp4xx/include/mach/platform.h
View File

@ -121,6 +121,7 @@ extern unsigned long ixp4xx_timer_freq;
* Functions used by platform-level setup code
*/
extern void ixp4xx_map_io(void);
extern void ixp4xx_init_early(void);
extern void ixp4xx_init_irq(void);
extern void ixp4xx_sys_init(void);
extern void ixp4xx_timer_init(void);

4
arch/arm/mach-ixp4xx/ixdp425-setup.c
View File

@ -254,6 +254,7 @@ static void __init ixdp425_init(void)
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,
@ -269,6 +270,7 @@ MACHINE_END
MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,
@ -283,6 +285,7 @@ MACHINE_END
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,
@ -297,6 +300,7 @@ MACHINE_END
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/nas100d-setup.c
View File

@ -315,6 +315,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.init_machine = nas100d_init,

1
arch/arm/mach-ixp4xx/nslu2-setup.c
View File

@ -301,6 +301,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
/* Maintainer: www.nslu2-linux.org */
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &nslu2_timer,
.init_machine = nslu2_init,

3
arch/arm/mach-ixp4xx/omixp-setup.c
View File

@ -243,6 +243,7 @@ static void __init omixp_init(void)
MACHINE_START(DEVIXP, "Omicron DEVIXP")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.init_machine = omixp_init,
@ -254,6 +255,7 @@ MACHINE_END
MACHINE_START(MICCPT, "Omicron MICCPT")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.init_machine = omixp_init,
@ -268,6 +270,7 @@ MACHINE_END
MACHINE_START(MIC256, "Omicron MIC256")
.atag_offset = 0x100,
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.init_machine = omixp_init,

1
arch/arm/mach-ixp4xx/vulcan-setup.c
View File

@ -237,6 +237,7 @@ static void __init vulcan_init(void)
MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
/* Maintainer: Marc Zyngier <maz@misterjones.org> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

1
arch/arm/mach-ixp4xx/wg302v2-setup.c
View File

@ -98,6 +98,7 @@ static void __init wg302v2_init(void)
MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.atag_offset = 0x100,

2
arch/arm/mach-kirkwood/include/mach/io.h
View File

@ -20,7 +20,5 @@ static inline void __iomem *__io(unsigned long addr)
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

19
arch/arm/mach-ks8695/include/mach/io.h
View File

@ -1,19 +0,0 @@
/*
* arch/arm/mach-ks8695/include/mach/io.h
*
* Copyright (C) 2006 Andrew Victor
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

27
arch/arm/mach-lpc32xx/include/mach/io.h
View File

@ -1,27 +0,0 @@
/*
* arch/arm/mach-lpc32xx/include/mach/io.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

6
arch/arm/mach-mmp/include/mach/addr-map.h
View File

@ -11,12 +11,6 @@
#ifndef __ASM_MACH_ADDR_MAP_H
#define __ASM_MACH_ADDR_MAP_H
#ifndef __ASSEMBLER__
#define IOMEM(x) ((void __iomem *)(x))
#else
#define IOMEM(x) (x)
#endif
/* APB - Application Subsystem Peripheral Bus
*
* NOTE: the DMA controller registers are actually on the AXI fabric #1

21
arch/arm/mach-mmp/include/mach/io.h
View File

@ -1,21 +0,0 @@
/*
* linux/arch/arm/mach-mmp/include/mach/io.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_MACH_IO_H
#define __ASM_MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif /* __ASM_MACH_IO_H */

6
arch/arm/mach-msm/board-halibut.c
View File

@ -68,6 +68,11 @@ static struct platform_device *devices[] __initdata = {
extern struct sys_timer msm_timer;
static void __init halibut_init_early(void)
{
arch_ioremap_caller = __msm_ioremap_caller;
}
static void __init halibut_init_irq(void)
{
msm_init_irq();
@ -96,6 +101,7 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
.atag_offset = 0x100,
.fixup = halibut_fixup,
.map_io = halibut_map_io,
.init_early = halibut_init_early,
.init_irq = halibut_init_irq,
.init_machine = halibut_init,
.timer = &msm_timer,

6
arch/arm/mach-msm/board-trout.c
View File

@ -43,6 +43,11 @@ static struct platform_device *devices[] __initdata = {
extern struct sys_timer msm_timer;
static void __init trout_init_early(void)
{
arch_ioremap_caller = __msm_ioremap_caller;
}
static void __init trout_init_irq(void)
{
msm_init_irq();
@ -96,6 +101,7 @@ MACHINE_START(TROUT, "HTC Dream")
.atag_offset = 0x100,
.fixup = trout_fixup,
.map_io = trout_map_io,
.init_early = trout_init_early,
.init_irq = trout_init_irq,
.init_machine = trout_init,
.timer = &msm_timer,

36
arch/arm/mach-msm/include/mach/io.h
View File

@ -1,36 +0,0 @@
/* arch/arm/mach-msm/include/mach/io.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __arch_ioremap __msm_ioremap
#define __arch_iounmap __iounmap
void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
void msm_map_qsd8x50_io(void);
void msm_map_msm7x30_io(void);
void msm_map_msm8x60_io(void);
void msm_map_msm8960_io(void);
extern unsigned int msm_shared_ram_phys;
#endif

12
arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
View File

@ -38,12 +38,6 @@
*
*/
#ifdef __ASSEMBLY__
#define IOMEM(x) x
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xC0000000
#define MSM_VIC_SIZE SZ_4K
@ -111,5 +105,11 @@
#define MSM_AD5_PHYS 0xAC000000
#define MSM_AD5_SIZE (SZ_1M*13)
#ifndef __ASSEMBLY__
extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
unsigned int mtype, void *caller);
#endif
#endif

4
arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
View File

@ -100,4 +100,8 @@
#define MSM_HSUSB_PHYS 0xA3600000
#define MSM_HSUSB_SIZE SZ_1K
#ifndef __ASSEMBLY__
extern void msm_map_msm7x30_io(void);
#endif
#endif

4
arch/arm/mach-msm/include/mach/msm_iomap-8960.h
View File

@ -50,4 +50,8 @@
#define MSM_DEBUG_UART_PHYS 0x16440000
#endif
#ifndef __ASSEMBLY__
extern void msm_map_msm8960_io(void);
#endif
#endif

4
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
View File

@ -122,4 +122,8 @@
#define MSM_SDC4_PHYS 0xA0600000
#define MSM_SDC4_SIZE SZ_4K
#ifndef __ASSEMBLY__
extern void msm_map_qsd8x50_io(void);
#endif
#endif

4
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
View File

@ -67,4 +67,8 @@
#define MSM_DEBUG_UART_PHYS 0x19C40000
#endif
#ifndef __ASSEMBLY__
extern void msm_map_msm8x60_io(void);
#endif
#endif

6
arch/arm/mach-msm/include/mach/msm_iomap.h
View File

@ -37,12 +37,6 @@
*
*/
#ifdef __ASSEMBLY__
#define IOMEM(x) x
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#if defined(CONFIG_ARCH_MSM7X30)
#include "msm_iomap-7x30.h"
#elif defined(CONFIG_ARCH_QSD8X50)

8
arch/arm/mach-msm/io.c
View File

@ -172,8 +172,8 @@ void __init msm_map_msm7x30_io(void)
}
#endif /* CONFIG_ARCH_MSM7X30 */
void __iomem *
__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
unsigned int mtype, void *caller)
{
if (mtype == MT_DEVICE) {
/* The peripherals in the 88000000 - D0000000 range
@ -184,7 +184,5 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap_caller(phys_addr, size, mtype,
__builtin_return_address(0));
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
EXPORT_SYMBOL(__msm_ioremap);

2
arch/arm/mach-mv78xx0/include/mach/io.h
View File

@ -20,7 +20,5 @@ static inline void __iomem *__io(unsigned long addr)
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

6
arch/arm/mach-mxs/include/mach/hardware.h
View File

@ -20,10 +20,4 @@
#ifndef __MACH_MXS_HARDWARE_H__
#define __MACH_MXS_HARDWARE_H__
#ifdef __ASSEMBLER__
#define IOMEM(addr) (addr)
#else
#define IOMEM(addr) ((void __force __iomem *)(addr))
#endif
#endif /* __MACH_MXS_HARDWARE_H__ */

22
arch/arm/mach-mxs/include/mach/io.h
View File

@ -1,22 +0,0 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_MXS_IO_H__
#define __MACH_MXS_IO_H__
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
/* io address mapping macro */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif /* __MACH_MXS_IO_H__ */

2
arch/arm/mach-netx/generic.c
View File

@ -168,7 +168,7 @@ void __init netx_init_irq(void)
{
int irq;
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0);
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
irq_set_chip_and_handler(irq, &netx_hif_chip,

2
arch/arm/mach-netx/include/mach/hardware.h
View File

@ -33,7 +33,7 @@
#define XMAC_MEM_SIZE 0x1000
#define SRAM_MEM_SIZE 0x8000
#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
#endif

28
arch/arm/mach-netx/include/mach/io.h
View File

@ -1,28 +0,0 @@
/*
* arch/arm/mach-netx/include/mach/io.h
*
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

16
arch/arm/mach-netx/include/mach/netx-regs.h
View File

@ -115,7 +115,7 @@
*********************************/
/* Registers */
#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs))
#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
@ -185,7 +185,7 @@
*******************************/
/* Registers */
#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs))
#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
@ -230,7 +230,7 @@
*******************************/
/* Registers */
#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs))
#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
@ -240,7 +240,7 @@
*******************************/
/* Registers */
#define NETX_MIIMU __io(NETX_VA_MIIMU)
#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
/* Bits */
#define MIIMU_SNRDY (1<<0)
@ -317,7 +317,7 @@
*******************************/
/* Registers */
#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs))
#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
@ -334,7 +334,7 @@
*******************************/
/* Registers */
#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs))
#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
@ -355,7 +355,7 @@
*******************************/
/* Registers */
#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs))
#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
@ -425,7 +425,7 @@
/*******************************
* I2C *
*******************************/
#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs))
#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
#define NETX_I2C_DATA NETX_I2C_REG(0x4)

22
arch/arm/mach-nomadik/include/mach/io.h
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-nomadik/include/mach/io.h (copied from mach-sa1100)
*
* Copyright (C) 1997-1999 Russell King
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-omap1/ams-delta-fiq-handler.S
View File

@ -14,6 +14,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <plat/board-ams-delta.h>

1
arch/arm/mach-omap1/include/mach/entry-macro.S
View File

@ -11,7 +11,6 @@
*/
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/irqs.h>
#include "../../iomap.h"

46
arch/arm/mach-omap1/include/mach/io.h
View File

@ -1,46 +0,0 @@
/*
* arch/arm/mach-omap1/include/mach/io.h
*
* IO definitions for TI OMAP processors and boards
*
* Copied from arch/arm/mach-sa1100/include/mach/io.h
* Copyright (C) 1997-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

6
arch/arm/mach-omap1/iomap.h
View File

@ -22,12 +22,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifdef __ASSEMBLER__
#define IOMEM(x) (x)
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)

2
arch/arm/mach-omap1/sleep.S
View File

@ -36,8 +36,6 @@
#include <asm/assembler.h>
#include <mach/io.h>
#include "iomap.h"
#include "pm.h"

1
arch/arm/mach-omap1/sram.S
View File

@ -12,7 +12,6 @@
#include <asm/assembler.h>
#include <mach/io.h>
#include <mach/hardware.h>
#include "iomap.h"

1
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/list.h>
#include <linux/io.h>
#include <plat/hardware.h>
#include <plat/clkdev_omap.h>

1
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -26,6 +26,7 @@
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <plat/hardware.h>
#include <plat/clkdev_omap.h>

49
arch/arm/mach-omap2/include/mach/io.h
View File

@ -1,49 +0,0 @@
/*
* arch/arm/mach-omap2/include/mach/io.h
*
* IO definitions for TI OMAP processors and boards
*
* Copied from arch/arm/mach-sa1100/include/mach/io.h
* Copyright (C) 1997-1999 Russell King
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

6
arch/arm/mach-omap2/iomap.h
View File

@ -22,12 +22,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifdef __ASSEMBLER__
#define IOMEM(x) (x)
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#define OMAP2_L3_IO_OFFSET 0x90000000
#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */

9
arch/arm/mach-orion5x/common.h
View File

@ -57,5 +57,14 @@ struct meminfo;
struct tag;
extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
/*****************************************************************************
* Helpers to access Orion registers
****************************************************************************/
/*
* These are not preempt-safe. Locks, if needed, must be taken
* care of by the caller.
*/
#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
#endif

33
arch/arm/mach-orion5x/include/mach/io.h
View File

@ -1,33 +0,0 @@
/*
* arch/arm/mach-orion5x/include/mach/io.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "orion5x.h"
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
/*****************************************************************************
* Helpers to access Orion registers
****************************************************************************/
/*
* These are not preempt-safe. Locks, if needed, must be taken
* care of by the caller.
*/
#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
#endif

1
arch/arm/mach-orion5x/pci.c
View File

@ -19,6 +19,7 @@
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
#include <mach/orion5x.h>
#include "common.h"
/*****************************************************************************

1
arch/arm/mach-orion5x/tsx09-common.c
View File

@ -15,6 +15,7 @@
#include <linux/mv643xx_eth.h>
#include <linux/timex.h>
#include <linux/serial_reg.h>
#include <mach/orion5x.h>
#include "tsx09-common.h"
#include "common.h"

22
arch/arm/mach-picoxcell/include/mach/io.h
View File

@ -1,22 +0,0 @@
/*
* Copyright (c) 2011 Picochip Ltd., Jamie Iles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No ioports, but needed for driver compatibility. */
#define __io(a) __typesafe_io(a)
/* No PCI possible on picoxcell. */
#define __mem_pci(a) (a)
#endif /* __ASM_ARM_ARCH_IO_H */

21
arch/arm/mach-pnx4008/include/mach/io.h
View File

@ -1,21 +0,0 @@
/*
* arch/arm/mach-pnx4008/include/mach/io.h
*
* Author: Dmitry Chigirev <chigirev@ru.mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

16
arch/arm/mach-prima2/include/mach/io.h
View File

@ -1,16 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/io.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __MACH_PRIMA2_IO_H
#define __MACH_PRIMA2_IO_H
#define IO_SPACE_LIMIT ((resource_size_t)0)
#define __mem_pci(a) (a)
#endif

1
arch/arm/mach-pxa/Kconfig
View File

@ -108,6 +108,7 @@ config CSB726_CSB701
config MACH_ARMCORE
bool "CompuLab CM-X255/CM-X270 modules"
select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI
select PXA27x
select IWMMXT
select PXA25x

1
arch/arm/mach-pxa/clock-pxa2xx.c
View File

@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <mach/pxa2xx-regs.h>

1
arch/arm/mach-pxa/corgi_pm.c
View File

@ -19,6 +19,7 @@
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/apm-emulation.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

1
arch/arm/mach-pxa/cpufreq-pxa3xx.c
View File

@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <mach/pxa3xx-regs.h>

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