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msm: kgsl: Disable HLSQ register reads from snapshot

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Reading the A3XX HLSQ registers during a GPU hang recovery might cause
the device to hang.  Disable the the HLSQ register reads that would
cause recovery to fail until the failures are better understood.

Change-Id: I1553025fbd824bfacf91f062372d5731cd905cc4
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
This commit is contained in:
Carter Cooper 2012-11-26 10:45:53 -07:00 committed by Stephen Boyd
parent 3aa6127300
commit 8d67af8cc3
3 changed files with 62 additions and 16 deletions
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3
drivers/gpu/msm/adreno.h
View file

@ -167,6 +167,9 @@ extern const unsigned int a225_registers_count;
extern const unsigned int a3xx_registers[];
extern const unsigned int a3xx_registers_count;
extern const unsigned int a3xx_hlsq_registers[];
extern const unsigned int a3xx_hlsq_registers_count;
extern const unsigned int a330_registers[];
extern const unsigned int a330_registers_count;

20
drivers/gpu/msm/adreno_a3xx.c
View file

@ -40,8 +40,8 @@ const unsigned int a3xx_registers[] = {
0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5, 0x0e00, 0x0e05,
0x0e0c, 0x0e0c, 0x0e22, 0x0e23, 0x0e41, 0x0e45, 0x0e64, 0x0e65,
0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5,
0x0e41, 0x0e45, 0x0e64, 0x0e65,
0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
@ -49,7 +49,7 @@ const unsigned int a3xx_registers[] = {
0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a, 0x2240, 0x227e,
0x2240, 0x227e,
0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
0x22ff, 0x22ff, 0x2340, 0x2343, 0x2348, 0x2349, 0x2350, 0x2356,
@ -58,7 +58,7 @@ const unsigned int a3xx_registers[] = {
0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3, 0x24e4, 0x24ef,
0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e, 0x2510, 0x2511,
0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea, 0x25ec, 0x25ed,
0x25f0, 0x25f0, 0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
0x25f0, 0x25f0,
0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0, 0x26c4, 0x26ce,
0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9, 0x26ec, 0x26ec,
0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743, 0x2748, 0x2749,
@ -69,6 +69,18 @@ const unsigned int a3xx_registers[] = {
const unsigned int a3xx_registers_count = ARRAY_SIZE(a3xx_registers) / 2;
/* Removed the following HLSQ register ranges from being read during
* recovery since reading the registers may cause the device to hang:
*/
const unsigned int a3xx_hlsq_registers[] = {
0x0e00, 0x0e05, 0x0e0c, 0x0e0c, 0x0e22, 0x0e23,
0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a,
0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
};
const unsigned int a3xx_hlsq_registers_count =
ARRAY_SIZE(a3xx_hlsq_registers) / 2;
/* The set of additional registers to be dumped for A330 */
const unsigned int a330_registers[] = {

55
drivers/gpu/msm/adreno_a3xx_snapshot.c
View file

@ -297,6 +297,41 @@ static void *a3xx_snapshot_debugbus(struct kgsl_device *device,
return snapshot;
}
static void _snapshot_a3xx_regs(struct kgsl_snapshot_registers *regs,
struct kgsl_snapshot_registers_list *list)
{
regs[list->count].regs = (unsigned int *) a3xx_registers;
regs[list->count].count = a3xx_registers_count;
list->count++;
}
static void _snapshot_hlsq_regs(struct kgsl_snapshot_registers *regs,
struct kgsl_snapshot_registers_list *list,
struct adreno_device *adreno_dev)
{
/* HLSQ specific registers */
/*
* Don't dump any a3xx HLSQ registers just yet. Reading the HLSQ
* registers can cause the device to hang if the HLSQ block is
* busy. Add specific checks for each a3xx core as the requirements
* are discovered. Disable by default for now.
*/
if (!adreno_is_a3xx(adreno_dev)) {
regs[list->count].regs = (unsigned int *) a3xx_hlsq_registers;
regs[list->count].count = a3xx_hlsq_registers_count;
list->count++;
}
}
static void _snapshot_a330_regs(struct kgsl_snapshot_registers *regs,
struct kgsl_snapshot_registers_list *list)
{
/* For A330, append the additional list of new registers to grab */
regs[list->count].regs = (unsigned int *) a330_registers;
regs[list->count].count = a330_registers_count;
list->count++;
}
/* A3XX GPU snapshot function - this is where all of the A3XX specific
* bits and pieces are grabbed into the snapshot memory
*/
@ -306,24 +341,20 @@ void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
{
struct kgsl_device *device = &adreno_dev->dev;
struct kgsl_snapshot_registers_list list;
struct kgsl_snapshot_registers regs[2];
regs[0].regs = (unsigned int *) a3xx_registers;
regs[0].count = a3xx_registers_count;
struct kgsl_snapshot_registers regs[5];
list.registers = regs;
list.count = 1;
/* For A330, append the additional list of new registers to grab */
if (adreno_is_a330(adreno_dev)) {
regs[1].regs = (unsigned int *) a330_registers;
regs[1].count = a330_registers_count;
list.count++;
}
list.count = 0;
/* Disable Clock gating temporarily for the debug bus to work */
adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00);
/* Store relevant registers in list to snapshot */
_snapshot_a3xx_regs(regs, &list);
_snapshot_hlsq_regs(regs, &list, adreno_dev);
if (adreno_is_a330(adreno_dev))
_snapshot_a330_regs(regs, &list);
/* Master set of (non debug) registers */
snapshot = kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain,