Piteball/android_kernel_google_msm
1
0
Fork 0
mirror of https://github.com/followmsi/android_kernel_google_msm.git synced 2024-11-06 23:17:41 +00:00
Code Issues Projects Releases Wiki Activity

msm: iommu: Fix SMR NSCFG configuration

Browse source 
When setting the NSCFG field, the S2CR register being
written needs to be indexed by the stream matching group,
not by the value of the SID being configured. Additionally,
there is no need to set CBACR for every SMR that is
programmed.

Change-Id: Ib79771a3bd87e4bd3b353bd5c6de9247138ca43e
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit c51f77cf28c2deba250444b51e88d87339890915)

Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
(cherry picked from commit b8cda0f34f2fc7369dddd833e41edcdbe75642c2)
This commit is contained in:
Stepan Moskovchenko 2012-08-21 20:50:01 -07:00 committed by Stephen Boyd
parent fc0b14eeae
commit 8ef15fd553
1 changed files with 7 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
drivers/iommu/msm_iommu-v2.c
View file

@ -260,15 +260,15 @@ static void __program_context(void __iomem *base, int ctx, int ncb,
SET_S2CR_N(base, num, 0);
SET_S2CR_CBNDX(base, num, ctx);
/* Set security bit override to be Non-secure */
SET_S2CR_NSCFG(base, sids[i], 3);
SET_CBAR_N(base, ctx, 0);
/* Stage 1 Context with Stage 2 bypass */
SET_CBAR_TYPE(base, ctx, 1);
/* Route page faults to the non-secure interrupt */
SET_CBAR_IRPTNDX(base, ctx, 1);
SET_S2CR_NSCFG(base, num, 3);
}
SET_CBAR_N(base, ctx, 0);
/* Stage 1 Context with Stage 2 bypass */
SET_CBAR_TYPE(base, ctx, 1);
/* Route page faults to the non-secure interrupt */
SET_CBAR_IRPTNDX(base, ctx, 1);
/* Find if this page table is used elsewhere, and re-use ASID */
found = 0;
for (i = 0; i < ncb; i++)