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ASoC: wm8955: Fix setting wrong register for WM8955_K_8_0_MASK bits
commit 12c350050538c7dc779c083b7342bfd20f74949c upstream. WM8955_K_8_0_MASK bits is controlled by WM8955_PLL_CONTROL_3 rather than WM8955_PLL_CONTROL_2. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Zefan Li <lizefan@huawei.com>
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@ -298,7 +298,7 @@ static int wm8955_configure_clocking(struct snd_soc_codec *codec)
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
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WM8955_K_17_9_MASK,
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(pll.k >> 9) & WM8955_K_17_9_MASK);
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_3,
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WM8955_K_8_0_MASK,
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pll.k & WM8955_K_8_0_MASK);
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if (pll.k)
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