mirror of
https://github.com/followmsi/android_kernel_google_msm.git
synced 2024-11-06 23:17:41 +00:00
msm: kgsl: Use a standard function for register access
There were dual functions for reading and writing registers for adreno devices. Stop the use of one of these dual functions as it makes the code more uniform. Change-Id: I703d27d1674a85a6c2d7a9fe6dc49f13005a3410 Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
This commit is contained in:
Carter Cooper
Iliyan Malchev
parent
94cb03cf46
commit
b30b6596a3
9 changed files with 168 additions and 169 deletions
|
|
@ -1022,9 +1022,9 @@ a2xx_getchipid(struct kgsl_device *device)
|
|||
if (pdata->chipid != 0)
|
||||
return pdata->chipid;
|
||||
|
||||
adreno_regread(device, REG_RBBM_PERIPHID1, &coreid);
|
||||
adreno_regread(device, REG_RBBM_PERIPHID2, &majorid);
|
||||
adreno_regread(device, REG_RBBM_PATCH_RELEASE, &revid);
|
||||
kgsl_regread(device, REG_RBBM_PERIPHID1, &coreid);
|
||||
kgsl_regread(device, REG_RBBM_PERIPHID2, &majorid);
|
||||
kgsl_regread(device, REG_RBBM_PATCH_RELEASE, &revid);
|
||||
|
||||
/*
|
||||
* adreno 22x gpus are indicated by coreid 2,
|
||||
|
|
@ -2039,7 +2039,7 @@ static bool adreno_hw_isidle(struct kgsl_device *device)
|
|||
return false;
|
||||
|
||||
/* Read the correct RBBM status for the GPU type */
|
||||
adreno_regread(device, ADRENO_REG_RBBM_STATUS,
|
||||
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS,
|
||||
®_rbbm_status);
|
||||
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
|
|
@ -2221,6 +2221,7 @@ uint8_t *adreno_convertaddr(struct kgsl_device *device, phys_addr_t pt_base,
|
|||
return memdesc ? kgsl_gpuaddr_to_vaddr(memdesc, gpuaddr) : NULL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* adreno_read - General read function to read adreno device memory
|
||||
* @device - Pointer to the GPU device struct (for adreno device)
|
||||
|
|
@ -2253,7 +2254,7 @@ static void adreno_read(struct kgsl_device *device, void *base,
|
|||
* @offsetwords - Word (4 Bytes) offset to the register to be read
|
||||
* @value - Value read from device register
|
||||
*/
|
||||
void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
|
||||
static void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
|
||||
unsigned int *value)
|
||||
{
|
||||
adreno_read(device, device->reg_virt, offsetwords, value,
|
||||
|
|
@ -2273,7 +2274,8 @@ void adreno_shadermem_regread(struct kgsl_device *device,
|
|||
device->shader_mem_len);
|
||||
}
|
||||
|
||||
void adreno_regwrite(struct kgsl_device *device, unsigned int offsetwords,
|
||||
static void adreno_regwrite(struct kgsl_device *device,
|
||||
unsigned int offsetwords,
|
||||
unsigned int value)
|
||||
{
|
||||
unsigned int *reg;
|
||||
|
|
|
|||
|
|
@ -376,10 +376,6 @@ void adreno_coresight_remove(struct platform_device *pdev);
|
|||
int adreno_coresight_init(struct platform_device *pdev);
|
||||
|
||||
int adreno_idle(struct kgsl_device *device);
|
||||
void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
|
||||
unsigned int *value);
|
||||
void adreno_regwrite(struct kgsl_device *device, unsigned int offsetwords,
|
||||
unsigned int value);
|
||||
|
||||
void adreno_shadermem_regread(struct kgsl_device *device,
|
||||
unsigned int offsetwords,
|
||||
|
|
@ -692,7 +688,7 @@ static inline void adreno_readreg(struct adreno_device *adreno_dev,
|
|||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
if (adreno_checkreg_off(adreno_dev, offset_name))
|
||||
adreno_regread(device,
|
||||
kgsl_regread(device,
|
||||
adreno_dev->gpudev->reg_offsets->offsets[offset_name],
|
||||
val);
|
||||
}
|
||||
|
|
@ -709,7 +705,7 @@ static inline void adreno_writereg(struct adreno_device *adreno_dev,
|
|||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
if (adreno_checkreg_off(adreno_dev, offset_name))
|
||||
adreno_regwrite(device,
|
||||
kgsl_regwrite(device,
|
||||
adreno_dev->gpudev->reg_offsets->offsets[offset_name], val);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1746,11 +1746,11 @@ static void a2xx_cp_intrcallback(struct kgsl_device *device)
|
|||
struct adreno_ringbuffer *rb = &adreno_dev->ringbuffer;
|
||||
int i;
|
||||
|
||||
adreno_regread(device, REG_MASTER_INT_SIGNAL, &master_status);
|
||||
kgsl_regread(device, REG_MASTER_INT_SIGNAL, &master_status);
|
||||
while (!status && (num_reads < VALID_STATUS_COUNT_MAX) &&
|
||||
(master_status & MASTER_INT_SIGNAL__CP_INT_STAT)) {
|
||||
adreno_regread(device, REG_CP_INT_STATUS, &status);
|
||||
adreno_regread(device, REG_MASTER_INT_SIGNAL,
|
||||
kgsl_regread(device, REG_CP_INT_STATUS, &status);
|
||||
kgsl_regread(device, REG_MASTER_INT_SIGNAL,
|
||||
&master_status);
|
||||
num_reads++;
|
||||
}
|
||||
|
|
@ -1792,7 +1792,7 @@ static void a2xx_cp_intrcallback(struct kgsl_device *device)
|
|||
|
||||
/* only ack bits we understand */
|
||||
status &= CP_INT_MASK;
|
||||
adreno_regwrite(device, REG_CP_INT_ACK, status);
|
||||
kgsl_regwrite(device, REG_CP_INT_ACK, status);
|
||||
|
||||
if (status & (CP_INT_CNTL__IB1_INT_MASK | CP_INT_CNTL__RB_INT_MASK)) {
|
||||
queue_work(device->work_queue, &device->ts_expired_ws);
|
||||
|
|
@ -1807,10 +1807,10 @@ static void a2xx_rbbm_intrcallback(struct kgsl_device *device)
|
|||
unsigned int addr = 0;
|
||||
const char *source;
|
||||
|
||||
adreno_regread(device, REG_RBBM_INT_STATUS, &status);
|
||||
kgsl_regread(device, REG_RBBM_INT_STATUS, &status);
|
||||
|
||||
if (status & RBBM_INT_CNTL__RDERR_INT_MASK) {
|
||||
adreno_regread(device, REG_RBBM_READ_ERROR, &rderr);
|
||||
kgsl_regread(device, REG_RBBM_READ_ERROR, &rderr);
|
||||
source = (rderr & RBBM_READ_ERROR_REQUESTER)
|
||||
? "host" : "cp";
|
||||
/* convert to dword address */
|
||||
|
|
@ -1834,7 +1834,7 @@ static void a2xx_rbbm_intrcallback(struct kgsl_device *device)
|
|||
}
|
||||
|
||||
status &= RBBM_INT_MASK;
|
||||
adreno_regwrite(device, REG_RBBM_INT_ACK, status);
|
||||
kgsl_regwrite(device, REG_RBBM_INT_ACK, status);
|
||||
}
|
||||
|
||||
irqreturn_t a2xx_irq_handler(struct adreno_device *adreno_dev)
|
||||
|
|
@ -1843,7 +1843,7 @@ irqreturn_t a2xx_irq_handler(struct adreno_device *adreno_dev)
|
|||
irqreturn_t result = IRQ_NONE;
|
||||
unsigned int status;
|
||||
|
||||
adreno_regread(device, REG_MASTER_INT_SIGNAL, &status);
|
||||
kgsl_regread(device, REG_MASTER_INT_SIGNAL, &status);
|
||||
|
||||
if (status & MASTER_INT_SIGNAL__MH_INT_STAT) {
|
||||
kgsl_mh_intrcallback(device);
|
||||
|
|
@ -1868,14 +1868,14 @@ static void a2xx_irq_control(struct adreno_device *adreno_dev, int state)
|
|||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
|
||||
if (state) {
|
||||
adreno_regwrite(device, REG_RBBM_INT_CNTL, RBBM_INT_MASK);
|
||||
adreno_regwrite(device, REG_CP_INT_CNTL, CP_INT_MASK);
|
||||
adreno_regwrite(device, MH_INTERRUPT_MASK,
|
||||
kgsl_regwrite(device, REG_RBBM_INT_CNTL, RBBM_INT_MASK);
|
||||
kgsl_regwrite(device, REG_CP_INT_CNTL, CP_INT_MASK);
|
||||
kgsl_regwrite(device, MH_INTERRUPT_MASK,
|
||||
kgsl_mmu_get_int_mask());
|
||||
} else {
|
||||
adreno_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
adreno_regwrite(device, MH_INTERRUPT_MASK, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
kgsl_regwrite(device, MH_INTERRUPT_MASK, 0);
|
||||
}
|
||||
|
||||
/* Force the writes to post before touching the IRQ line */
|
||||
|
|
@ -1887,7 +1887,7 @@ static unsigned int a2xx_irq_pending(struct adreno_device *adreno_dev)
|
|||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
unsigned int status;
|
||||
|
||||
adreno_regread(device, REG_MASTER_INT_SIGNAL, &status);
|
||||
kgsl_regread(device, REG_MASTER_INT_SIGNAL, &status);
|
||||
|
||||
return (status &
|
||||
(MASTER_INT_SIGNAL__MH_INT_STAT |
|
||||
|
|
@ -1969,21 +1969,21 @@ static unsigned int a2xx_busy_cycles(struct adreno_device *adreno_dev)
|
|||
unsigned int reg, val;
|
||||
|
||||
/* Freeze the counter */
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_FREEZE);
|
||||
|
||||
/* Get the value */
|
||||
adreno_regread(device, REG_RBBM_PERFCOUNTER1_LO, &val);
|
||||
kgsl_regread(device, REG_RBBM_PERFCOUNTER1_LO, &val);
|
||||
|
||||
/* Reset the counter */
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_RESET);
|
||||
|
||||
/* Re-Enable the performance monitors */
|
||||
adreno_regread(device, REG_RBBM_PM_OVERRIDE2, ®);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, (reg | 0x40));
|
||||
adreno_regwrite(device, REG_RBBM_PERFCOUNTER1_SELECT, 0x1);
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
kgsl_regread(device, REG_RBBM_PM_OVERRIDE2, ®);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, (reg | 0x40));
|
||||
kgsl_regwrite(device, REG_RBBM_PERFCOUNTER1_SELECT, 0x1);
|
||||
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_ENABLE);
|
||||
|
||||
return val;
|
||||
|
|
@ -2009,7 +2009,7 @@ static void a2xx_gmeminit(struct adreno_device *adreno_dev)
|
|||
/* must be aligned to size */
|
||||
rb_edram_info.f.edram_range = (adreno_dev->gmem_base >> 14);
|
||||
|
||||
adreno_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val);
|
||||
kgsl_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val);
|
||||
}
|
||||
|
||||
static void a2xx_start(struct adreno_device *adreno_dev)
|
||||
|
|
@ -2021,8 +2021,8 @@ static void a2xx_start(struct adreno_device *adreno_dev)
|
|||
* before issuing a soft reset. The overrides will then be
|
||||
* turned off (set to 0)
|
||||
*/
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0xfffffffe);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xffffffff);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0xfffffffe);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xffffffff);
|
||||
|
||||
/*
|
||||
* Only reset CP block if all blocks have previously been
|
||||
|
|
@ -2030,11 +2030,11 @@ static void a2xx_start(struct adreno_device *adreno_dev)
|
|||
*/
|
||||
if (!(device->flags & KGSL_FLAGS_SOFT_RESET) ||
|
||||
!adreno_is_a22x(adreno_dev)) {
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
kgsl_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
0xFFFFFFFF);
|
||||
device->flags |= KGSL_FLAGS_SOFT_RESET;
|
||||
} else {
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
kgsl_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
0x00000001);
|
||||
}
|
||||
/*
|
||||
|
|
@ -2043,11 +2043,11 @@ static void a2xx_start(struct adreno_device *adreno_dev)
|
|||
*/
|
||||
msleep(30);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000000);
|
||||
kgsl_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000000);
|
||||
|
||||
if (adreno_is_a225(adreno_dev)) {
|
||||
/* Enable large instruction store for A225 */
|
||||
adreno_regwrite(device, REG_SQ_FLOW_CONTROL,
|
||||
kgsl_regwrite(device, REG_SQ_FLOW_CONTROL,
|
||||
0x18000000);
|
||||
}
|
||||
|
||||
|
|
@ -2055,29 +2055,29 @@ static void a2xx_start(struct adreno_device *adreno_dev)
|
|||
/* For A20X based targets increase number of clocks
|
||||
* that RBBM will wait before de-asserting Register
|
||||
* Clock Active signal */
|
||||
adreno_regwrite(device, REG_RBBM_CNTL, 0x0000FFFF);
|
||||
kgsl_regwrite(device, REG_RBBM_CNTL, 0x0000FFFF);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_CNTL, 0x00004442);
|
||||
kgsl_regwrite(device, REG_RBBM_CNTL, 0x00004442);
|
||||
|
||||
adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
|
||||
adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
|
||||
kgsl_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
|
||||
kgsl_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
|
||||
|
||||
if (cpu_is_msm8960())
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0x200);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0x200);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
|
||||
|
||||
if (!adreno_is_a22x(adreno_dev))
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG, 0x00080000);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG, 0x00080000);
|
||||
|
||||
/* Make sure interrupts are disabled */
|
||||
adreno_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_SQ_INT_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_SQ_INT_CNTL, 0);
|
||||
|
||||
a2xx_gmeminit(adreno_dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
|
@ -38,11 +38,11 @@ static int a2xx_snapshot_sxdebug(struct kgsl_device *device, void *snapshot,
|
|||
header->size = SXDEBUG_COUNT;
|
||||
|
||||
for (i = 0; i < SXDEBUG_COUNT; i++) {
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1B00 | i);
|
||||
adreno_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1B00 | i);
|
||||
kgsl_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
}
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
|
||||
return DEBUG_SECTION_SZ(SXDEBUG_COUNT);
|
||||
}
|
||||
|
|
@ -65,11 +65,11 @@ static int a2xx_snapshot_cpdebug(struct kgsl_device *device, void *snapshot,
|
|||
header->size = CPDEBUG_COUNT;
|
||||
|
||||
for (i = 0; i < CPDEBUG_COUNT; i++) {
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1628);
|
||||
adreno_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1628);
|
||||
kgsl_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
}
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
|
||||
return DEBUG_SECTION_SZ(CPDEBUG_COUNT);
|
||||
}
|
||||
|
|
@ -82,7 +82,8 @@ static int a2xx_snapshot_cpdebug(struct kgsl_device *device, void *snapshot,
|
|||
|
||||
#define SQ_DEBUG_WRITE(_device, _reg, _data, _offset) \
|
||||
do { _data[(_offset)++] = (_reg); \
|
||||
adreno_regread(_device, (_reg), &_data[(_offset)++]); } while (0)
|
||||
kgsl_regread(_device, (_reg), &_data[(_offset)++]); \
|
||||
} while (0)
|
||||
|
||||
#define SQ_DEBUG_BANK_SIZE 23
|
||||
|
||||
|
|
@ -175,7 +176,7 @@ static int a2xx_snapshot_sqthreaddebug(struct kgsl_device *device,
|
|||
header->size = size;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
adreno_regwrite(device, REG_SQ_DEBUG_TB_STATUS_SEL,
|
||||
kgsl_regwrite(device, REG_SQ_DEBUG_TB_STATUS_SEL,
|
||||
i | (6<<4) | (i<<7) | (1<<11) | (1<<12)
|
||||
| (i<<16) | (6<<20) | (i<<23));
|
||||
SQ_DEBUG_WRITE(device, REG_SQ_DEBUG_VTX_TB_STATE_MEM,
|
||||
|
|
@ -215,11 +216,11 @@ static int a2xx_snapshot_miudebug(struct kgsl_device *device, void *snapshot,
|
|||
header->size = MIUDEBUG_COUNT;
|
||||
|
||||
for (i = 0; i < MIUDEBUG_COUNT; i++) {
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1600 | i);
|
||||
adreno_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0x1600 | i);
|
||||
kgsl_regread(device, REG_RBBM_DEBUG_OUT, &data[i]);
|
||||
}
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
kgsl_regwrite(device, REG_RBBM_DEBUG_CNTL, 0);
|
||||
|
||||
return DEBUG_SECTION_SZ(MIUDEBUG_COUNT);
|
||||
}
|
||||
|
|
@ -297,8 +298,8 @@ void *a2xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
|
|||
* work
|
||||
*/
|
||||
|
||||
adreno_regread(device, REG_RBBM_PM_OVERRIDE2, &pmoverride);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xFF);
|
||||
kgsl_regread(device, REG_RBBM_PM_OVERRIDE2, &pmoverride);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xFF);
|
||||
|
||||
/* SX debug registers */
|
||||
snapshot = kgsl_snapshot_add_section(device,
|
||||
|
|
@ -376,7 +377,7 @@ void *a2xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
|
|||
|
||||
|
||||
/* Reset the clock gating */
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, pmoverride);
|
||||
kgsl_regwrite(device, REG_RBBM_PM_OVERRIDE2, pmoverride);
|
||||
|
||||
return snapshot;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2581,7 +2581,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit)
|
|||
case A3XX_INT_RBBM_AHB_ERROR: {
|
||||
unsigned int reg;
|
||||
|
||||
adreno_regread(device, A3XX_RBBM_AHB_ERROR_STATUS, ®);
|
||||
kgsl_regread(device, A3XX_RBBM_AHB_ERROR_STATUS, ®);
|
||||
|
||||
/*
|
||||
* Return the word address of the erroring register so that it
|
||||
|
|
@ -2595,7 +2595,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit)
|
|||
(reg >> 24) & 0x3);
|
||||
|
||||
/* Clear the error */
|
||||
adreno_regwrite(device, A3XX_RBBM_AHB_CMD, (1 << 3));
|
||||
kgsl_regwrite(device, A3XX_RBBM_AHB_CMD, (1 << 3));
|
||||
|
||||
/* Trigger a fault in the interrupt handler */
|
||||
adreno_dispatcher_irq_fault(device);
|
||||
|
|
@ -2781,21 +2781,21 @@ static void a3xx_perfcounter_enable_pwr(struct kgsl_device *device,
|
|||
if (countable > 1)
|
||||
return;
|
||||
|
||||
adreno_regread(device, A3XX_RBBM_RBBM_CTL, &in);
|
||||
kgsl_regread(device, A3XX_RBBM_RBBM_CTL, &in);
|
||||
|
||||
if (countable == 0)
|
||||
out = in | RBBM_RBBM_CTL_RESET_PWR_CTR0;
|
||||
else
|
||||
out = in | RBBM_RBBM_CTL_RESET_PWR_CTR1;
|
||||
|
||||
adreno_regwrite(device, A3XX_RBBM_RBBM_CTL, out);
|
||||
kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, out);
|
||||
|
||||
if (countable == 0)
|
||||
out = in | RBBM_RBBM_CTL_ENABLE_PWR_CTR0;
|
||||
else
|
||||
out = in | RBBM_RBBM_CTL_ENABLE_PWR_CTR1;
|
||||
|
||||
adreno_regwrite(device, A3XX_RBBM_RBBM_CTL, out);
|
||||
kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, out);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -2809,8 +2809,8 @@ static void a3xx_perfcounter_enable_vbif(struct kgsl_device *device,
|
|||
if (counter > 1 || countable > 0x7f)
|
||||
return;
|
||||
|
||||
adreno_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
|
||||
adreno_regread(device, A3XX_VBIF_PERF_CNT_SEL, &sel);
|
||||
kgsl_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
|
||||
kgsl_regread(device, A3XX_VBIF_PERF_CNT_SEL, &sel);
|
||||
|
||||
if (counter == 0) {
|
||||
bit = VBIF_PERF_CNT_0;
|
||||
|
|
@ -2823,12 +2823,12 @@ static void a3xx_perfcounter_enable_vbif(struct kgsl_device *device,
|
|||
|
||||
out = in | bit;
|
||||
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_SEL, sel);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_SEL, sel);
|
||||
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, bit);
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, 0);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, bit);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, 0);
|
||||
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_EN, out);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_EN, out);
|
||||
}
|
||||
|
||||
static void a3xx_perfcounter_enable_vbif_pwr(struct kgsl_device *device,
|
||||
|
|
@ -2839,7 +2839,7 @@ static void a3xx_perfcounter_enable_vbif_pwr(struct kgsl_device *device,
|
|||
if (countable > 2)
|
||||
return;
|
||||
|
||||
adreno_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
|
||||
kgsl_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
|
||||
if (countable == 0)
|
||||
bit = VBIF_PERF_PWR_CNT_0;
|
||||
else if (countable == 1)
|
||||
|
|
@ -2849,10 +2849,10 @@ static void a3xx_perfcounter_enable_vbif_pwr(struct kgsl_device *device,
|
|||
|
||||
out = in | bit;
|
||||
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, bit);
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, 0);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, bit);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_CLR, 0);
|
||||
|
||||
adreno_regwrite(device, A3XX_VBIF_PERF_CNT_EN, out);
|
||||
kgsl_regwrite(device, A3XX_VBIF_PERF_CNT_EN, out);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2889,14 +2889,14 @@ static void a3xx_perfcounter_enable(struct adreno_device *adreno_dev,
|
|||
reg = &(a3xx_perfcounter_reglist[group].regs[counter]);
|
||||
|
||||
/* Select the desired perfcounter */
|
||||
adreno_regwrite(device, reg->select, countable);
|
||||
kgsl_regwrite(device, reg->select, countable);
|
||||
|
||||
if (reg->load_bit < 32) {
|
||||
val = 1 << reg->load_bit;
|
||||
adreno_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, val);
|
||||
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, val);
|
||||
} else {
|
||||
val = 1 << (reg->load_bit - 32);
|
||||
adreno_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, val);
|
||||
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, val);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2918,17 +2918,17 @@ static uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev,
|
|||
reg = &(a3xx_perfcounter_reglist[group].regs[counter]);
|
||||
|
||||
/* Freeze the counter */
|
||||
adreno_regread(device, A3XX_RBBM_PERFCTR_CTL, &val);
|
||||
kgsl_regread(device, A3XX_RBBM_PERFCTR_CTL, &val);
|
||||
val &= ~reg->load_bit;
|
||||
adreno_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
|
||||
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
|
||||
|
||||
/* Read the values */
|
||||
adreno_regread(device, offset, &lo);
|
||||
adreno_regread(device, offset + 1, &hi);
|
||||
kgsl_regread(device, offset, &lo);
|
||||
kgsl_regread(device, offset + 1, &hi);
|
||||
|
||||
/* Re-Enable the counter */
|
||||
val |= reg->load_bit;
|
||||
adreno_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
|
||||
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
|
||||
|
||||
return (((uint64_t) hi) << 32) | lo;
|
||||
}
|
||||
|
|
@ -2988,7 +2988,7 @@ static irqreturn_t a3xx_irq_handler(struct adreno_device *adreno_dev)
|
|||
unsigned int status, tmp;
|
||||
int i;
|
||||
|
||||
adreno_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
|
||||
kgsl_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
|
||||
|
||||
for (tmp = status, i = 0; tmp && i < ARRAY_SIZE(a3xx_irq_funcs); i++) {
|
||||
if (tmp & 1) {
|
||||
|
|
@ -3007,7 +3007,7 @@ static irqreturn_t a3xx_irq_handler(struct adreno_device *adreno_dev)
|
|||
trace_kgsl_a3xx_irq_status(device, status);
|
||||
|
||||
if (status)
|
||||
adreno_regwrite(&adreno_dev->dev, A3XX_RBBM_INT_CLEAR_CMD,
|
||||
kgsl_regwrite(&adreno_dev->dev, A3XX_RBBM_INT_CLEAR_CMD,
|
||||
status);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -3017,16 +3017,16 @@ static void a3xx_irq_control(struct adreno_device *adreno_dev, int state)
|
|||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
|
||||
if (state)
|
||||
adreno_regwrite(device, A3XX_RBBM_INT_0_MASK, A3XX_INT_MASK);
|
||||
kgsl_regwrite(device, A3XX_RBBM_INT_0_MASK, A3XX_INT_MASK);
|
||||
else
|
||||
adreno_regwrite(device, A3XX_RBBM_INT_0_MASK, 0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_INT_0_MASK, 0);
|
||||
}
|
||||
|
||||
static unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev)
|
||||
{
|
||||
unsigned int status;
|
||||
|
||||
adreno_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
|
||||
kgsl_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
|
||||
|
||||
return (status & A3XX_INT_MASK) ? 1 : 0;
|
||||
}
|
||||
|
|
@ -3038,7 +3038,7 @@ static unsigned int a3xx_busy_cycles(struct adreno_device *adreno_dev)
|
|||
unsigned int ret = 0;
|
||||
|
||||
/* Read the value */
|
||||
adreno_regread(device, A3XX_RBBM_PERFCTR_PWR_1_LO, &val);
|
||||
kgsl_regread(device, A3XX_RBBM_PERFCTR_PWR_1_LO, &val);
|
||||
|
||||
/* Return 0 for the first read */
|
||||
if (adreno_dev->gpu_cycles != 0) {
|
||||
|
|
@ -3355,57 +3355,57 @@ static void a3xx_start(struct adreno_device *adreno_dev)
|
|||
BUG_ON(vbif == NULL);
|
||||
|
||||
while (vbif->reg != 0) {
|
||||
adreno_regwrite(device, vbif->reg, vbif->val);
|
||||
kgsl_regwrite(device, vbif->reg, vbif->val);
|
||||
vbif++;
|
||||
}
|
||||
|
||||
/* Make all blocks contribute to the GPU BUSY perf counter */
|
||||
adreno_regwrite(device, A3XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);
|
||||
kgsl_regwrite(device, A3XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);
|
||||
|
||||
/* Tune the hystersis counters for SP and CP idle detection */
|
||||
adreno_regwrite(device, A3XX_RBBM_SP_HYST_CNT, 0x10);
|
||||
adreno_regwrite(device, A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
|
||||
kgsl_regwrite(device, A3XX_RBBM_SP_HYST_CNT, 0x10);
|
||||
kgsl_regwrite(device, A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
|
||||
|
||||
/* Enable the RBBM error reporting bits. This lets us get
|
||||
useful information on failure */
|
||||
|
||||
adreno_regwrite(device, A3XX_RBBM_AHB_CTL0, 0x00000001);
|
||||
kgsl_regwrite(device, A3XX_RBBM_AHB_CTL0, 0x00000001);
|
||||
|
||||
/* Enable AHB error reporting */
|
||||
adreno_regwrite(device, A3XX_RBBM_AHB_CTL1, 0xA6FFFFFF);
|
||||
kgsl_regwrite(device, A3XX_RBBM_AHB_CTL1, 0xA6FFFFFF);
|
||||
|
||||
/* Turn on the power counters */
|
||||
adreno_regwrite(device, A3XX_RBBM_RBBM_CTL, 0x00030000);
|
||||
kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, 0x00030000);
|
||||
|
||||
/* Turn on hang detection - this spews a lot of useful information
|
||||
* into the RBBM registers on a hang */
|
||||
|
||||
adreno_regwrite(device, A3XX_RBBM_INTERFACE_HANG_INT_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_INTERFACE_HANG_INT_CTL,
|
||||
(1 << 16) | 0xFFF);
|
||||
|
||||
/* Enable 64-byte cacheline size. HW Default is 32-byte (0x000000E0). */
|
||||
adreno_regwrite(device, A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
|
||||
kgsl_regwrite(device, A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
|
||||
|
||||
/* Enable Clock gating */
|
||||
adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL,
|
||||
adreno_a3xx_rbbm_clock_ctl_default(adreno_dev));
|
||||
|
||||
if (adreno_is_a330v2(adreno_dev))
|
||||
adreno_regwrite(device, A3XX_RBBM_GPR0_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
|
||||
A330v2_RBBM_GPR0_CTL_DEFAULT);
|
||||
else if (adreno_is_a330(adreno_dev))
|
||||
adreno_regwrite(device, A3XX_RBBM_GPR0_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
|
||||
A330_RBBM_GPR0_CTL_DEFAULT);
|
||||
|
||||
/* Set the OCMEM base address for A330 */
|
||||
if (adreno_is_a330(adreno_dev) ||
|
||||
adreno_is_a305b(adreno_dev)) {
|
||||
adreno_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
|
||||
kgsl_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
|
||||
(unsigned int)(adreno_dev->ocmem_base >> 14));
|
||||
}
|
||||
|
||||
/* Turn on performance counters */
|
||||
adreno_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);
|
||||
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);
|
||||
|
||||
/* Turn on the GPU busy counter and let it run free */
|
||||
|
||||
|
|
@ -3421,22 +3421,22 @@ int a3xx_coresight_enable(struct kgsl_device *device)
|
|||
{
|
||||
mutex_lock(&device->mutex);
|
||||
if (!kgsl_active_count_get(device)) {
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0001093F);
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0,
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0001093F);
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0,
|
||||
0x00000000);
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1,
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1,
|
||||
0xFFFFFFFE);
|
||||
adreno_regwrite(device, A3XX_RBBM_INT_TRACE_BUS_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_INT_TRACE_BUS_CTL,
|
||||
0x00201111);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_BUS_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_BUS_CTL,
|
||||
0x89100010);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_STOP_CNT,
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_STOP_CNT,
|
||||
0x00017fff);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_START_CNT,
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_START_CNT,
|
||||
0x0001000f);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_PERIOD_CNT ,
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_PERIOD_CNT ,
|
||||
0x0001ffff);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_CMD,
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_CMD,
|
||||
0x00000001);
|
||||
kgsl_active_count_put(device);
|
||||
}
|
||||
|
|
@ -3453,15 +3453,15 @@ void a3xx_coresight_disable(struct kgsl_device *device)
|
|||
{
|
||||
mutex_lock(&device->mutex);
|
||||
if (!kgsl_active_count_get(device)) {
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_INT_TRACE_BUS_CTL, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_BUS_CTL, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_STOP_CNT, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_START_CNT, 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_PERIOD_CNT , 0x0);
|
||||
adreno_regwrite(device, A3XX_RBBM_EXT_TRACE_CMD, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_INT_TRACE_BUS_CTL, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_BUS_CTL, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_STOP_CNT, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_START_CNT, 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_PERIOD_CNT , 0x0);
|
||||
kgsl_regwrite(device, A3XX_RBBM_EXT_TRACE_CMD, 0x0);
|
||||
kgsl_active_count_put(device);
|
||||
}
|
||||
mutex_unlock(&device->mutex);
|
||||
|
|
@ -3472,7 +3472,7 @@ static void a3xx_coresight_write_reg(struct kgsl_device *device,
|
|||
{
|
||||
mutex_lock(&device->mutex);
|
||||
if (!kgsl_active_count_get(device)) {
|
||||
adreno_regwrite(device, wordoffset, val);
|
||||
kgsl_regwrite(device, wordoffset, val);
|
||||
kgsl_active_count_put(device);
|
||||
}
|
||||
mutex_unlock(&device->mutex);
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@ static void _rbbm_debug_bus_read(struct kgsl_device *device,
|
|||
unsigned int block_id, unsigned int index, unsigned int *val)
|
||||
{
|
||||
unsigned int block = (block_id << 8) | 1 << 16;
|
||||
adreno_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, block | index);
|
||||
adreno_regread(device, A3XX_RBBM_DEBUG_BUS_DATA_STATUS, val);
|
||||
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, block | index);
|
||||
kgsl_regread(device, A3XX_RBBM_DEBUG_BUS_DATA_STATUS, val);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -108,9 +108,9 @@ static int a3xx_snapshot_vpc_memory(struct kgsl_device *device, void *snapshot,
|
|||
for (bank = 0; bank < VPC_MEMORY_BANKS; bank++) {
|
||||
for (addr = 0; addr < VPC_MEMORY_SIZE; addr++) {
|
||||
unsigned int val = bank | (addr << 4);
|
||||
adreno_regwrite(device,
|
||||
kgsl_regwrite(device,
|
||||
A3XX_VPC_VPC_DEBUG_RAM_SEL, val);
|
||||
adreno_regread(device,
|
||||
kgsl_regread(device,
|
||||
A3XX_VPC_VPC_DEBUG_RAM_READ, &data[i++]);
|
||||
}
|
||||
}
|
||||
|
|
@ -134,9 +134,9 @@ static int a3xx_snapshot_cp_meq(struct kgsl_device *device, void *snapshot,
|
|||
header->type = SNAPSHOT_DEBUG_CP_MEQ;
|
||||
header->size = CP_MEQ_SIZE;
|
||||
|
||||
adreno_regwrite(device, A3XX_CP_MEQ_ADDR, 0x0);
|
||||
kgsl_regwrite(device, A3XX_CP_MEQ_ADDR, 0x0);
|
||||
for (i = 0; i < CP_MEQ_SIZE; i++)
|
||||
adreno_regread(device, A3XX_CP_MEQ_DATA, &data[i]);
|
||||
kgsl_regread(device, A3XX_CP_MEQ_DATA, &data[i]);
|
||||
|
||||
return DEBUG_SECTION_SZ(CP_MEQ_SIZE);
|
||||
}
|
||||
|
|
@ -164,9 +164,9 @@ static int a3xx_snapshot_cp_pm4_ram(struct kgsl_device *device, void *snapshot,
|
|||
* maintain always changing hardcoded constants
|
||||
*/
|
||||
|
||||
adreno_regwrite(device, REG_CP_ME_RAM_RADDR, 0x0);
|
||||
kgsl_regwrite(device, REG_CP_ME_RAM_RADDR, 0x0);
|
||||
for (i = 0; i < size; i++)
|
||||
adreno_regread(device, REG_CP_ME_RAM_DATA, &data[i]);
|
||||
kgsl_regread(device, REG_CP_ME_RAM_DATA, &data[i]);
|
||||
|
||||
return DEBUG_SECTION_SZ(size);
|
||||
}
|
||||
|
|
@ -195,7 +195,7 @@ static int a3xx_snapshot_cp_pfp_ram(struct kgsl_device *device, void *snapshot,
|
|||
*/
|
||||
kgsl_regwrite(device, A3XX_CP_PFP_UCODE_ADDR, 0x0);
|
||||
for (i = 0; i < size; i++)
|
||||
adreno_regread(device, A3XX_CP_PFP_UCODE_DATA, &data[i]);
|
||||
kgsl_regread(device, A3XX_CP_PFP_UCODE_DATA, &data[i]);
|
||||
|
||||
return DEBUG_SECTION_SZ(size);
|
||||
}
|
||||
|
|
@ -226,9 +226,9 @@ static int a3xx_snapshot_cp_roq(struct kgsl_device *device, void *snapshot,
|
|||
header->type = SNAPSHOT_DEBUG_CP_ROQ;
|
||||
header->size = size;
|
||||
|
||||
adreno_regwrite(device, A3XX_CP_ROQ_ADDR, 0x0);
|
||||
kgsl_regwrite(device, A3XX_CP_ROQ_ADDR, 0x0);
|
||||
for (i = 0; i < size; i++)
|
||||
adreno_regread(device, A3XX_CP_ROQ_DATA, &data[i]);
|
||||
kgsl_regread(device, A3XX_CP_ROQ_DATA, &data[i]);
|
||||
|
||||
return DEBUG_SECTION_SZ(size);
|
||||
}
|
||||
|
|
@ -253,12 +253,12 @@ static int a330_snapshot_cp_merciu(struct kgsl_device *device, void *snapshot,
|
|||
header->type = SNAPSHOT_DEBUG_CP_MERCIU;
|
||||
header->size = size;
|
||||
|
||||
adreno_regwrite(device, A3XX_CP_MERCIU_ADDR, 0x0);
|
||||
kgsl_regwrite(device, A3XX_CP_MERCIU_ADDR, 0x0);
|
||||
|
||||
for (i = 0; i < A330_CP_MERCIU_QUEUE_SIZE; i++) {
|
||||
adreno_regread(device, A3XX_CP_MERCIU_DATA,
|
||||
kgsl_regread(device, A3XX_CP_MERCIU_DATA,
|
||||
&data[(i * 2)]);
|
||||
adreno_regread(device, A3XX_CP_MERCIU_DATA2,
|
||||
kgsl_regread(device, A3XX_CP_MERCIU_DATA2,
|
||||
&data[(i * 2) + 1]);
|
||||
}
|
||||
|
||||
|
|
@ -447,7 +447,7 @@ void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
|
|||
list.count = 0;
|
||||
|
||||
/* Disable Clock gating temporarily for the debug bus to work */
|
||||
adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00);
|
||||
kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00);
|
||||
|
||||
/* Store relevant registers in list to snapshot */
|
||||
_snapshot_a3xx_regs(regs, &list);
|
||||
|
|
@ -519,7 +519,7 @@ void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
|
|||
snapshot = a3xx_snapshot_debugbus(device, snapshot, remain);
|
||||
|
||||
/* Enable Clock gating */
|
||||
adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL,
|
||||
kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL,
|
||||
adreno_a3xx_rbbm_clock_ctl_default(adreno_dev));
|
||||
|
||||
return snapshot;
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@ static ssize_t coresight_read_reg(struct kgsl_device *device,
|
|||
|
||||
mutex_lock(&device->mutex);
|
||||
if (!kgsl_active_count_get(device)) {
|
||||
adreno_regread(device, offset, ®val);
|
||||
kgsl_regread(device, offset, ®val);
|
||||
kgsl_active_count_put(device);
|
||||
}
|
||||
mutex_unlock(&device->mutex);
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static void fault_detect_read(struct kgsl_device *device)
|
|||
for (i = 0; i < FT_DETECT_REGS_COUNT; i++) {
|
||||
if (ft_detect_regs[i] == 0)
|
||||
continue;
|
||||
adreno_regread(device, ft_detect_regs[i],
|
||||
kgsl_regread(device, ft_detect_regs[i],
|
||||
&fault_detect_regs[i]);
|
||||
}
|
||||
}
|
||||
|
|
@ -89,7 +89,7 @@ static int fault_detect_read_compare(struct kgsl_device *device)
|
|||
|
||||
if (ft_detect_regs[i] == 0)
|
||||
continue;
|
||||
adreno_regread(device, ft_detect_regs[i], &val);
|
||||
kgsl_regread(device, ft_detect_regs[i], &val);
|
||||
if (val != fault_detect_regs[i])
|
||||
ret = 1;
|
||||
fault_detect_regs[i] = val;
|
||||
|
|
|
|||
|
|
@ -308,12 +308,12 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb)
|
|||
(rb->sizedwords << 2));
|
||||
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
adreno_regwrite(device, REG_CP_RB_WPTR_BASE,
|
||||
kgsl_regwrite(device, REG_CP_RB_WPTR_BASE,
|
||||
(rb->memptrs_desc.gpuaddr
|
||||
+ GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
|
||||
|
||||
/* setup WPTR delay */
|
||||
adreno_regwrite(device, REG_CP_RB_WPTR_DELAY,
|
||||
kgsl_regwrite(device, REG_CP_RB_WPTR_DELAY,
|
||||
0 /*0x70000010 */);
|
||||
}
|
||||
|
||||
|
|
@ -353,33 +353,33 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb)
|
|||
|
||||
if (adreno_is_a3xx(adreno_dev)) {
|
||||
/* enable access protection to privileged registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
|
||||
|
||||
/* RBBM registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_0, 0x63000040);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_1, 0x62000080);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_2, 0x600000CC);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_3, 0x60000108);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_4, 0x64000140);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_5, 0x66000400);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_0, 0x63000040);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_1, 0x62000080);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_2, 0x600000CC);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_3, 0x60000108);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_4, 0x64000140);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_5, 0x66000400);
|
||||
|
||||
/* CP registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_6, 0x65000700);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_7, 0x610007D8);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_8, 0x620007E0);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_9, 0x61001178);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_A, 0x64001180);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_6, 0x65000700);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_7, 0x610007D8);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_8, 0x620007E0);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_9, 0x61001178);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_A, 0x64001180);
|
||||
|
||||
/* RB registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_B, 0x60003300);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_B, 0x60003300);
|
||||
|
||||
/* VBIF registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_C, 0x6B00C000);
|
||||
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_C, 0x6B00C000);
|
||||
}
|
||||
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
/* explicitly clear all cp interrupts */
|
||||
adreno_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF);
|
||||
kgsl_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
/* setup scratch/timestamp */
|
||||
|
|
@ -404,9 +404,9 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb)
|
|||
/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
|
||||
if (adreno_is_a305(adreno_dev) || adreno_is_a305c(adreno_dev) ||
|
||||
adreno_is_a320(adreno_dev))
|
||||
adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000E0602);
|
||||
kgsl_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000E0602);
|
||||
else if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev))
|
||||
adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x003E2008);
|
||||
kgsl_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x003E2008);
|
||||
|
||||
rb->wptr = 0;
|
||||
|
||||
|
|
@ -434,7 +434,7 @@ void adreno_ringbuffer_stop(struct adreno_ringbuffer *rb)
|
|||
|
||||
if (rb->flags & KGSL_FLAGS_STARTED) {
|
||||
if (adreno_is_a200(adreno_dev))
|
||||
adreno_regwrite(rb->device, REG_CP_ME_CNTL, 0x10000000);
|
||||
kgsl_regwrite(rb->device, REG_CP_ME_CNTL, 0x10000000);
|
||||
|
||||
rb->flags &= ~KGSL_FLAGS_STARTED;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue