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msm: cpr: Enable CPR support for 8625
CPR (Core Power Reduction) helps save CPU power by reducing the chip voltage whenever possible Change-Id: Ifa32967046b4bb7f5b4f756feb9cefabe8f5bea4 Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org> (cherry picked from commit c0e5d6768038efbe5fb98fcd935f01c8ce611e08) Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org> (cherry picked from commit 7c8192db2ee5a7edbf8ac9707e3d044efd213da3)
This commit is contained in:
Kaushal Kumar
Stephen Boyd
parent
b2c67334b8
commit
b80e0d6446
3 changed files with 190 additions and 1 deletions
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@ -39,6 +39,8 @@
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#include "mpm-8625.h"
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#include "irq.h"
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#include "pm.h"
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#include "msm_cpr.h"
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#include "msm_smem_iface.h"
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/* Address of GSBI blocks */
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#define MSM_GSBI0_PHYS 0xA1200000
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@ -48,6 +50,12 @@
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#define MSM_GSBI0_QUP_PHYS (MSM_GSBI0_PHYS + 0x80000)
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#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
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#define A11S_TEST_BUS_SEL_ADDR (MSM_CSR_BASE + 0x518)
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#define RBCPR_CLK_MUX_SEL (1 << 13)
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/* Reset Address of RBCPR (Active Low)*/
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#define RBCPR_SW_RESET_N (MSM_CSR_BASE + 0x64)
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static struct resource gsbi0_qup_i2c_resources[] = {
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{
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.name = "qup_phys_addr",
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@ -1592,6 +1600,176 @@ struct platform_device msm8625_kgsl_3d0 = {
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},
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};
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static struct resource cpr_resources[] = {
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{
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.start = MSM8625_INT_CPR_IRQ0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MSM8625_CPR_PHYS,
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.end = MSM8625_CPR_PHYS + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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/**
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* These are various Vdd levels supported by PMIC
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*/
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static uint32_t msm_c2_pmic_mv[] __initdata = {
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1300, 12875 / 10, 1275, 12625 / 10, 1250,
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12375 / 10, 1225, 12125 / 10, 1200, 11875 / 10,
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1175, 11625 / 10, 1150, 11375 / 10, 1125,
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11125 / 10, 1100, 10875 / 10, 1075, 10625 / 10,
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1050, 10375 / 10, 1025, 10125 / 10, 0, 0, 0, 0,
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0, 0, 0, 1000,
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};
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/**
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* This data will be based on CPR mode of operation
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*/
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static struct msm_cpr_mode msm_cpr_mode_data[] = {
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[NORMAL_MODE] = {
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.ring_osc_data = {
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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},
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.ring_osc = 0,
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.step_quot = ~0,
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.tgt_volt_offset = 1,
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.Vmax = 1200,
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.Vmin = 1000,
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.calibrated_mV = 1100,
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},
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[TURBO_MODE] = {
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.ring_osc_data = {
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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{0, },
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},
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.ring_osc = 0,
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.step_quot = ~0,
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.tgt_volt_offset = 1,
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.Vmax = 1350,
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.Vmin = 1250,
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.calibrated_mV = 1300,
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},
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};
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struct msm_cpr_vp_data vp_data = {
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.min_volt = 1000,
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.max_volt = 1350,
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.default_volt = 1300,
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.step_size = (12500 / 1000),
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};
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static struct msm_cpr_config msm_cpr_pdata = {
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.ref_clk_khz = 19200,
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.delay_us = 10000,
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.irq_line = 0,
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.cpr_mode_data = msm_cpr_mode_data,
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.tgt_count_div_N = 1,
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.floor = 0,
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.ceiling = 40,
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.sw_vlevel = 20,
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.up_threshold = 1,
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.dn_threshold = 2,
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.up_margin = 0,
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.dn_margin = 0,
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.nom_freq_limit = 1008000,
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.vp_data = &vp_data,
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};
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static struct platform_device msm8625_device_cpr = {
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.name = "msm-cpr",
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.id = -1,
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.num_resources = ARRAY_SIZE(cpr_resources),
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.resource = cpr_resources,
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.dev = {
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.platform_data = &msm_cpr_pdata,
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},
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};
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static struct platform_device msm8625_vp_device = {
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.name = "vp-regulator",
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.id = -1,
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};
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static void __init msm_cpr_init(void)
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{
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struct cpr_info_type *cpr_info = NULL;
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uint8_t ring_osc = 0;
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uint32_t reg_val;
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cpr_info = kzalloc(sizeof(struct cpr_info_type), GFP_KERNEL);
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if (!cpr_info) {
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pr_err("%s: Out of memory %d\n", __func__, -ENOMEM);
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return;
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}
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msm_smem_get_cpr_info(cpr_info);
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/**
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* Set the ring_osc based on efuse BIT(0)
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* CPR_fuse[0] = 0 selects 2nd RO (010)
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* CPR_fuse[0] = 1 select 3rd RO (011)
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*/
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if (cpr_info->ring_osc == 0x0)
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ring_osc = 0x2;
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else if (cpr_info->ring_osc == 0x1)
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ring_osc = 0x3;
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msm_cpr_mode_data[TURBO_MODE].ring_osc = ring_osc;
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msm_cpr_mode_data[NORMAL_MODE].ring_osc = ring_osc;
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/* GCNT = 1000 nsec/52nsec (@TCX0=19.2Mhz) = 19.2 */
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msm_cpr_mode_data[TURBO_MODE].ring_osc_data[ring_osc].gcnt = 19;
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msm_cpr_mode_data[NORMAL_MODE].ring_osc_data[ring_osc].gcnt = 19;
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/* The multiplier and offset are as per PTE data */
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msm_cpr_mode_data[TURBO_MODE].ring_osc_data[ring_osc].target_count =
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cpr_info->turbo_quot * 10 + 440;
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msm_cpr_mode_data[NORMAL_MODE].ring_osc_data[ring_osc].target_count =
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cpr_info->turbo_quot / msm_cpr_pdata.tgt_count_div_N;
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/**
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* Bits 4:0 of pvs_fuse provide mapping to the safe boot up voltage.
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* Boot up mode is by default Turbo.
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*/
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msm_cpr_mode_data[TURBO_MODE].calibrated_mV =
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msm_c2_pmic_mv[cpr_info->pvs_fuse & 0x1F];
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/* TODO: Store the tgt_volt_offset values for the modes from PTE */
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pr_debug("%s: cpr: ring_osc: 0x%x\n", __func__,
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msm_cpr_mode_data[TURBO_MODE].ring_osc);
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pr_debug("%s: cpr: turbo_quot: 0x%x\n", __func__, cpr_info->turbo_quot);
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pr_debug("%s: cpr: pvs_fuse: 0x%x\n", __func__, cpr_info->pvs_fuse);
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kfree(cpr_info);
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/* Select TCXO (19.2MHz) as clock source */
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reg_val = readl_relaxed(A11S_TEST_BUS_SEL_ADDR);
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reg_val |= RBCPR_CLK_MUX_SEL;
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writel_relaxed(reg_val, A11S_TEST_BUS_SEL_ADDR);
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/* Get CPR out of reset */
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writel_relaxed(0x1, RBCPR_SW_RESET_N);
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platform_device_register(&msm8625_vp_device);
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platform_device_register(&msm8625_device_cpr);
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}
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static struct clk_lookup msm_clock_8625_dummy[] = {
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CLK_DUMMY("core_clk", adm_clk.c, "msm_dmov", 0),
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CLK_DUMMY("adsp_clk", adsp_clk.c, NULL, 0),
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@ -1658,7 +1836,6 @@ struct clock_init_data msm8625_dummy_clock_init_data __initdata = {
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.table = msm_clock_8625_dummy,
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.size = ARRAY_SIZE(msm_clock_8625_dummy),
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};
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enum {
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MSM8625,
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MSM8625A,
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@ -1704,6 +1881,7 @@ int __init msm7x2x_misc_init(void)
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{
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if (machine_is_msm8625_rumi3()) {
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msm_clock_init(&msm8625_dummy_clock_init_data);
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msm_cpr_init();
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return 0;
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}
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@ -1720,6 +1898,11 @@ int __init msm7x2x_misc_init(void)
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} else {
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platform_device_register(&msm7x27a_device_acpuclk);
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}
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if (cpu_is_msm8625() &&
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(SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2))
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msm_cpr_init();
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return 0;
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}
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@ -84,6 +84,9 @@
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#define MSM8625_INT_L2CC_EM (GIC_SPI_START + 32 + 22)
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#define MSM8625_INT_L2CC_INTR (GIC_SPI_START + 32 + 23)
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#define MSM8625_INT_CE_IRQ (GIC_SPI_START + 32 + 24)
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#define MSM8625_INT_CPR_IRQ0 (GIC_SPI_START + 32 + 25)
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#define MSM8625_INT_CPR_IRQ1 (GIC_SPI_START + 32 + 26)
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#define MSM8625_INT_CPR_IRQ2 (GIC_SPI_START + 32 + 27)
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#define MSM8625_INT_ADSP_A11_SMSM MSM8625_INT_ADSP_A11
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#endif
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@ -57,4 +57,7 @@
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#define MSM8625_CFG_CTL_PHYS 0xA9800000
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#define MSM8625_CFG_CTL_SIZE SZ_4K
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#define MSM8625_CPR_PHYS 0xC0900000
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#define MSM8625_CPR_SIZE SZ_4K
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#endif
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