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msm: iommu: Split rotator/mdp iommu domains

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Finer granularity is needed when mapping into the IOMMU's for
rotator and mdp for secure playback. During secure playback
HLOS will only have access to map into one context bank. The
other context bank is secured and programmed by TrustZone.

Divide DISPLAY_DOMAIN into DISPLAY_WRITE_DOMAIN and
DISPLAY_READ_DOMAIN. Divide ROTATOR_DOMAIN into ROTATOR_SRC_DOMAIN
and ROTATOR_DST_DOMAIN.

Change-Id: If3e556171645e8ea02deb12ca543df36233db5f2
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
This commit is contained in:
Olav Haugan 2012-05-15 09:50:30 -07:00 committed by Stephen Boyd
parent d673e17729
commit c2243eff90
10 changed files with 172 additions and 74 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

54
arch/arm/mach-msm/devices-8064.c
View file

@ -2586,15 +2586,15 @@ struct msm_iommu_domain_name apq8064_iommu_ctx_names[] = {
.name = "jpegd_dst", .name = "jpegd_dst",
.domain = CAMERA_DOMAIN, .domain = CAMERA_DOMAIN,
}, },
/* Rotator */ /* Rotator src*/
{ {
.name = "rot_src", .name = "rot_src",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_SRC_DOMAIN,
}, },
/* Rotator */ /* Rotator dst */
{ {
.name = "rot_dst", .name = "rot_dst",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_DST_DOMAIN,
}, },
/* Video */ /* Video */
{ {
@ -2650,18 +2650,36 @@ static struct mem_pool apq8064_camera_pools[] = {
}, },
}; };
static struct mem_pool apq8064_display_pools[] = { static struct mem_pool apq8064_display_read_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for display */ /* One address space for display reads */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
}, },
}; };
static struct mem_pool apq8064_rotator_pools[] = { static struct mem_pool apq8064_display_write_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for rotator */ /* One address space for display writes */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool apq8064_rotator_src_pools[] = {
[GEN_POOL] =
/* One address space for rotator src */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool apq8064_rotator_dst_pools[] = {
[GEN_POOL] =
/* One address space for rotator dst */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
@ -2677,13 +2695,21 @@ static struct msm_iommu_domain apq8064_iommu_domains[] = {
.iova_pools = apq8064_camera_pools, .iova_pools = apq8064_camera_pools,
.npools = ARRAY_SIZE(apq8064_camera_pools), .npools = ARRAY_SIZE(apq8064_camera_pools),
}, },
[DISPLAY_DOMAIN] = { [DISPLAY_READ_DOMAIN] = {
.iova_pools = apq8064_display_pools, .iova_pools = apq8064_display_read_pools,
.npools = ARRAY_SIZE(apq8064_display_pools), .npools = ARRAY_SIZE(apq8064_display_read_pools),
}, },
[ROTATOR_DOMAIN] = { [DISPLAY_WRITE_DOMAIN] = {
.iova_pools = apq8064_rotator_pools, .iova_pools = apq8064_display_write_pools,
.npools = ARRAY_SIZE(apq8064_rotator_pools), .npools = ARRAY_SIZE(apq8064_display_write_pools),
},
[ROTATOR_SRC_DOMAIN] = {
.iova_pools = apq8064_rotator_src_pools,
.npools = ARRAY_SIZE(apq8064_rotator_src_pools),
},
[ROTATOR_DST_DOMAIN] = {
.iova_pools = apq8064_rotator_dst_pools,
.npools = ARRAY_SIZE(apq8064_rotator_dst_pools),
}, },
}; };

50
arch/arm/mach-msm/devices-8930.c
View file

@ -765,12 +765,12 @@ struct msm_iommu_domain_name msm8930_iommu_ctx_names[] = {
/* Rotator */ /* Rotator */
{ {
.name = "rot_src", .name = "rot_src",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_SRC_DOMAIN,
}, },
/* Rotator */ /* Rotator */
{ {
.name = "rot_dst", .name = "rot_dst",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_DST_DOMAIN,
}, },
/* Video */ /* Video */
{ {
@ -826,18 +826,36 @@ static struct mem_pool msm8930_camera_pools[] = {
}, },
}; };
static struct mem_pool msm8930_display_pools[] = { static struct mem_pool msm8930_display_read_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for display */ /* One address space for display reads */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
}, },
}; };
static struct mem_pool msm8930_rotator_pools[] = { static struct mem_pool msm8930_display_write_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for rotator */ /* One address space for display writes */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool msm8930_rotator_src_pools[] = {
[GEN_POOL] =
/* One address space for rotator src */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool msm8930_rotator_dst_pools[] = {
[GEN_POOL] =
/* One address space for rotator dst */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
@ -853,13 +871,21 @@ static struct msm_iommu_domain msm8930_iommu_domains[] = {
.iova_pools = msm8930_camera_pools, .iova_pools = msm8930_camera_pools,
.npools = ARRAY_SIZE(msm8930_camera_pools), .npools = ARRAY_SIZE(msm8930_camera_pools),
}, },
[DISPLAY_DOMAIN] = { [DISPLAY_READ_DOMAIN] = {
.iova_pools = msm8930_display_pools, .iova_pools = msm8930_display_read_pools,
.npools = ARRAY_SIZE(msm8930_display_pools), .npools = ARRAY_SIZE(msm8930_display_read_pools),
}, },
[ROTATOR_DOMAIN] = { [DISPLAY_WRITE_DOMAIN] = {
.iova_pools = msm8930_rotator_pools, .iova_pools = msm8930_display_write_pools,
.npools = ARRAY_SIZE(msm8930_rotator_pools), .npools = ARRAY_SIZE(msm8930_display_write_pools),
},
[ROTATOR_SRC_DOMAIN] = {
.iova_pools = msm8930_rotator_src_pools,
.npools = ARRAY_SIZE(msm8930_rotator_src_pools),
},
[ROTATOR_DST_DOMAIN] = {
.iova_pools = msm8930_rotator_dst_pools,
.npools = ARRAY_SIZE(msm8930_rotator_dst_pools),
}, },
}; };

54
arch/arm/mach-msm/devices-8960.c
View file

@ -3639,15 +3639,15 @@ struct msm_iommu_domain_name msm8960_iommu_ctx_names[] = {
.name = "jpegd_dst", .name = "jpegd_dst",
.domain = CAMERA_DOMAIN, .domain = CAMERA_DOMAIN,
}, },
/* Rotator */ /* Rotator src*/
{ {
.name = "rot_src", .name = "rot_src",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_SRC_DOMAIN,
}, },
/* Rotator */ /* Rotator dst */
{ {
.name = "rot_dst", .name = "rot_dst",
.domain = ROTATOR_DOMAIN, .domain = ROTATOR_DST_DOMAIN,
}, },
/* Video */ /* Video */
{ {
@ -3703,18 +3703,36 @@ static struct mem_pool msm8960_camera_pools[] = {
}, },
}; };
static struct mem_pool msm8960_display_pools[] = { static struct mem_pool msm8960_display_read_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for display */ /* One address space for display reads */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
}, },
}; };
static struct mem_pool msm8960_rotator_pools[] = { static struct mem_pool msm8960_display_write_pools[] = {
[GEN_POOL] = [GEN_POOL] =
/* One address space for rotator */ /* One address space for display writes */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool msm8960_rotator_src_pools[] = {
[GEN_POOL] =
/* One address space for rotator src */
{
.paddr = SZ_128K,
.size = SZ_2G - SZ_128K,
},
};
static struct mem_pool msm8960_rotator_dst_pools[] = {
[GEN_POOL] =
/* One address space for rotator dst */
{ {
.paddr = SZ_128K, .paddr = SZ_128K,
.size = SZ_2G - SZ_128K, .size = SZ_2G - SZ_128K,
@ -3730,13 +3748,21 @@ static struct msm_iommu_domain msm8960_iommu_domains[] = {
.iova_pools = msm8960_camera_pools, .iova_pools = msm8960_camera_pools,
.npools = ARRAY_SIZE(msm8960_camera_pools), .npools = ARRAY_SIZE(msm8960_camera_pools),
}, },
[DISPLAY_DOMAIN] = { [DISPLAY_READ_DOMAIN] = {
.iova_pools = msm8960_display_pools, .iova_pools = msm8960_display_read_pools,
.npools = ARRAY_SIZE(msm8960_display_pools), .npools = ARRAY_SIZE(msm8960_display_read_pools),
}, },
[ROTATOR_DOMAIN] = { [DISPLAY_WRITE_DOMAIN] = {
.iova_pools = msm8960_rotator_pools, .iova_pools = msm8960_display_write_pools,
.npools = ARRAY_SIZE(msm8960_rotator_pools), .npools = ARRAY_SIZE(msm8960_display_write_pools),
},
[ROTATOR_SRC_DOMAIN] = {
.iova_pools = msm8960_rotator_src_pools,
.npools = ARRAY_SIZE(msm8960_rotator_src_pools),
},
[ROTATOR_DST_DOMAIN] = {
.iova_pools = msm8960_rotator_dst_pools,
.npools = ARRAY_SIZE(msm8960_rotator_dst_pools),
}, },
}; };

6
arch/arm/mach-msm/include/mach/iommu_domains.h
View file

@ -18,8 +18,10 @@
enum { enum {
VIDEO_DOMAIN, VIDEO_DOMAIN,
CAMERA_DOMAIN, CAMERA_DOMAIN,
DISPLAY_DOMAIN, DISPLAY_READ_DOMAIN,
ROTATOR_DOMAIN, DISPLAY_WRITE_DOMAIN,
ROTATOR_SRC_DOMAIN,
ROTATOR_DST_DOMAIN,
MAX_DOMAINS MAX_DOMAINS
}; };

6
arch/arm/mach-msm/subsystem_map.c
View file

@ -38,8 +38,10 @@ static unsigned long subsystem_to_domain_tbl[] = {
VIDEO_DOMAIN, VIDEO_DOMAIN,
VIDEO_DOMAIN, VIDEO_DOMAIN,
CAMERA_DOMAIN, CAMERA_DOMAIN,
DISPLAY_DOMAIN, DISPLAY_READ_DOMAIN,
ROTATOR_DOMAIN, DISPLAY_WRITE_DOMAIN,
ROTATOR_SRC_DOMAIN,
ROTATOR_DST_DOMAIN,
0xFFFFFFFF 0xFFFFFFFF
}; };

20
drivers/char/msm_rotator.c
View file

@ -174,6 +174,7 @@ int msm_rotator_iommu_map_buf(int mem_id, unsigned char src,
unsigned long *start, unsigned long *len, unsigned long *start, unsigned long *len,
struct ion_handle **pihdl) struct ion_handle **pihdl)
{ {
int domain;
if (!msm_rotator_dev->client) if (!msm_rotator_dev->client)
return -EINVAL; return -EINVAL;
@ -185,8 +186,9 @@ int msm_rotator_iommu_map_buf(int mem_id, unsigned char src,
pr_debug("%s(): ion_hdl %p, ion_buf %p\n", __func__, *pihdl, pr_debug("%s(): ion_hdl %p, ion_buf %p\n", __func__, *pihdl,
ion_share(msm_rotator_dev->client, *pihdl)); ion_share(msm_rotator_dev->client, *pihdl));
domain = src ? ROTATOR_SRC_DOMAIN : ROTATOR_DST_DOMAIN;
if (ion_map_iommu(msm_rotator_dev->client, if (ion_map_iommu(msm_rotator_dev->client,
*pihdl, ROTATOR_DOMAIN, GEN_POOL, *pihdl, domain, GEN_POOL,
SZ_4K, 0, start, len, 0, ION_IOMMU_UNMAP_DELAYED)) { SZ_4K, 0, start, len, 0, ION_IOMMU_UNMAP_DELAYED)) {
pr_err("ion_map_iommu() failed\n"); pr_err("ion_map_iommu() failed\n");
return -EINVAL; return -EINVAL;
@ -862,17 +864,21 @@ static int get_img(struct msmfb_data *fbd, unsigned char src,
} }
static void put_img(struct file *p_file, struct ion_handle *p_ihdl) static void put_img(struct file *p_file, struct ion_handle *p_ihdl,
unsigned char src)
{ {
#ifdef CONFIG_ANDROID_PMEM #ifdef CONFIG_ANDROID_PMEM
if (p_file != NULL) if (p_file != NULL)
put_pmem_file(p_file); put_pmem_file(p_file);
#endif #endif
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION #ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
if (!IS_ERR_OR_NULL(p_ihdl)) { if (!IS_ERR_OR_NULL(p_ihdl)) {
int domain = src ? ROTATOR_SRC_DOMAIN : \
ROTATOR_DST_DOMAIN;
pr_debug("%s(): p_ihdl %p\n", __func__, p_ihdl); pr_debug("%s(): p_ihdl %p\n", __func__, p_ihdl);
ion_unmap_iommu(msm_rotator_dev->client, ion_unmap_iommu(msm_rotator_dev->client,
p_ihdl, ROTATOR_DOMAIN, GEN_POOL); p_ihdl, domain, GEN_POOL);
ion_free(msm_rotator_dev->client, p_ihdl); ion_free(msm_rotator_dev->client, p_ihdl);
} }
@ -1162,15 +1168,15 @@ do_rotate_exit:
#endif #endif
schedule_delayed_work(&msm_rotator_dev->rot_clk_work, HZ); schedule_delayed_work(&msm_rotator_dev->rot_clk_work, HZ);
do_rotate_unlock_mutex: do_rotate_unlock_mutex:
put_img(dstp1_file, dstp1_ihdl); put_img(dstp1_file, dstp1_ihdl, 0);
put_img(srcp1_file, srcp1_ihdl); put_img(srcp1_file, srcp1_ihdl, 1);
put_img(dstp0_file, dstp0_ihdl); put_img(dstp0_file, dstp0_ihdl, 0);
/* only source may use frame buffer */ /* only source may use frame buffer */
if (info.src.flags & MDP_MEMORY_ID_TYPE_FB) if (info.src.flags & MDP_MEMORY_ID_TYPE_FB)
fput_light(srcp0_file, ps0_need); fput_light(srcp0_file, ps0_need);
else else
put_img(srcp0_file, srcp0_ihdl); put_img(srcp0_file, srcp0_ihdl, 1);
mutex_unlock(&msm_rotator_dev->rotator_lock); mutex_unlock(&msm_rotator_dev->rotator_lock);
dev_dbg(msm_rotator_dev->device, "%s() returning rc = %d\n", dev_dbg(msm_rotator_dev->device, "%s() returning rc = %d\n",
__func__, rc); __func__, rc);

4
drivers/media/video/msm/wfd/wfd-ioctl.c
View file

@ -288,7 +288,7 @@ int wfd_allocate_input_buffers(struct wfd_device *wfd_dev,
mdp_mregion->ion_handle = enc_mregion->ion_handle; mdp_mregion->ion_handle = enc_mregion->ion_handle;
rc = ion_map_iommu(wfd_dev->ion_client, mdp_mregion->ion_handle, rc = ion_map_iommu(wfd_dev->ion_client, mdp_mregion->ion_handle,
DISPLAY_DOMAIN, GEN_POOL, SZ_4K, DISPLAY_WRITE_DOMAIN, GEN_POOL, SZ_4K,
0, (unsigned long *)&mdp_mregion->paddr, 0, (unsigned long *)&mdp_mregion->paddr,
(unsigned long *)&mdp_mregion->size, 0, 0); (unsigned long *)&mdp_mregion->size, 0, 0);
if (rc) { if (rc) {
@ -363,7 +363,7 @@ void wfd_free_input_buffers(struct wfd_device *wfd_dev,
if (mpair->mdp->paddr) if (mpair->mdp->paddr)
ion_unmap_iommu(wfd_dev->ion_client, ion_unmap_iommu(wfd_dev->ion_client,
mpair->mdp->ion_handle, mpair->mdp->ion_handle,
DISPLAY_DOMAIN, GEN_POOL); DISPLAY_WRITE_DOMAIN, GEN_POOL);
if (mpair->enc->paddr) if (mpair->enc->paddr)
ion_unmap_iommu(wfd_dev->ion_client, ion_unmap_iommu(wfd_dev->ion_client,

24
drivers/video/msm/mdp4_overlay.c
View file

@ -126,7 +126,7 @@ int mdp4_overlay_iommu_map_buf(int mem_id,
pr_debug("mixer %u, pipe %u, plane %u\n", pipe->mixer_num, pr_debug("mixer %u, pipe %u, plane %u\n", pipe->mixer_num,
pipe->pipe_ndx, plane); pipe->pipe_ndx, plane);
if (ion_map_iommu(display_iclient, *srcp_ihdl, if (ion_map_iommu(display_iclient, *srcp_ihdl,
DISPLAY_DOMAIN, GEN_POOL, SZ_4K, 0, start, DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K, 0, start,
len, 0, ION_IOMMU_UNMAP_DELAYED)) { len, 0, ION_IOMMU_UNMAP_DELAYED)) {
ion_free(display_iclient, *srcp_ihdl); ion_free(display_iclient, *srcp_ihdl);
pr_err("ion_map_iommu() failed\n"); pr_err("ion_map_iommu() failed\n");
@ -140,7 +140,7 @@ int mdp4_overlay_iommu_map_buf(int mem_id,
if (iom_pipe_info->prev_ihdl[plane]) { if (iom_pipe_info->prev_ihdl[plane]) {
ion_unmap_iommu(display_iclient, ion_unmap_iommu(display_iclient,
iom_pipe_info->prev_ihdl[plane], iom_pipe_info->prev_ihdl[plane],
DISPLAY_DOMAIN, GEN_POOL); DISPLAY_READ_DOMAIN, GEN_POOL);
ion_free(display_iclient, ion_free(display_iclient,
iom_pipe_info->prev_ihdl[plane]); iom_pipe_info->prev_ihdl[plane]);
pr_debug("Previous: mixer %u, pipe %u, plane %u, " pr_debug("Previous: mixer %u, pipe %u, plane %u, "
@ -175,7 +175,7 @@ void mdp4_iommu_unmap(struct mdp4_overlay_pipe *pipe)
iom_pipe_info->prev_ihdl[i]); iom_pipe_info->prev_ihdl[i]);
ion_unmap_iommu(display_iclient, ion_unmap_iommu(display_iclient,
iom_pipe_info->prev_ihdl[i], iom_pipe_info->prev_ihdl[i],
DISPLAY_DOMAIN, GEN_POOL); DISPLAY_READ_DOMAIN, GEN_POOL);
ion_free(display_iclient, ion_free(display_iclient,
iom_pipe_info->prev_ihdl[i]); iom_pipe_info->prev_ihdl[i]);
iom_pipe_info->prev_ihdl[i] = NULL; iom_pipe_info->prev_ihdl[i] = NULL;
@ -191,7 +191,7 @@ void mdp4_iommu_unmap(struct mdp4_overlay_pipe *pipe)
iom_pipe_info->ihdl[i]); iom_pipe_info->ihdl[i]);
ion_unmap_iommu(display_iclient, ion_unmap_iommu(display_iclient,
iom_pipe_info->ihdl[i], iom_pipe_info->ihdl[i],
DISPLAY_DOMAIN, GEN_POOL); DISPLAY_READ_DOMAIN, GEN_POOL);
ion_free(display_iclient, ion_free(display_iclient,
iom_pipe_info->ihdl[i]); iom_pipe_info->ihdl[i]);
iom_pipe_info->ihdl[i] = NULL; iom_pipe_info->ihdl[i] = NULL;
@ -3180,25 +3180,25 @@ static struct {
char *name; char *name;
int domain; int domain;
} msm_iommu_ctx_names[] = { } msm_iommu_ctx_names[] = {
/* Display */ /* Display read*/
{ {
.name = "mdp_port0_cb0", .name = "mdp_port0_cb0",
.domain = DISPLAY_DOMAIN, .domain = DISPLAY_READ_DOMAIN,
}, },
/* Display */ /* Display read*/
{ {
.name = "mdp_port0_cb1", .name = "mdp_port0_cb1",
.domain = DISPLAY_DOMAIN, .domain = DISPLAY_WRITE_DOMAIN,
}, },
/* Display */ /* Display write */
{ {
.name = "mdp_port1_cb0", .name = "mdp_port1_cb0",
.domain = DISPLAY_DOMAIN, .domain = DISPLAY_READ_DOMAIN,
}, },
/* Display */ /* Display write */
{ {
.name = "mdp_port1_cb1", .name = "mdp_port1_cb1",
.domain = DISPLAY_DOMAIN, .domain = DISPLAY_WRITE_DOMAIN,
}, },
}; };

24
drivers/video/msm/mdp4_util.c
View file

@ -2591,11 +2591,20 @@ u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
buf->ihdl = ion_alloc(mfd->iclient, buffer_size, SZ_4K, buf->ihdl = ion_alloc(mfd->iclient, buffer_size, SZ_4K,
mfd->mem_hid); mfd->mem_hid);
if (!IS_ERR_OR_NULL(buf->ihdl)) { if (!IS_ERR_OR_NULL(buf->ihdl)) {
if (ion_map_iommu(mfd->iclient, buf->ihdl, if (mfd->mem_hid & ION_SECURE) {
DISPLAY_DOMAIN, GEN_POOL, SZ_4K, 0, &addr, if (ion_phys(mfd->iclient, buf->ihdl,
&len, 0, 0)) { &addr, (unsigned *)&len)) {
pr_err("ion_map_iommu() failed\n"); pr_err("%s:%d: ion_phys map failed\n",
return -ENOMEM; __func__, __LINE__);
return -ENOMEM;
}
} else {
if (ion_map_iommu(mfd->iclient, buf->ihdl,
DISPLAY_WRITE_DOMAIN, GEN_POOL, SZ_4K,
0, &addr, &len, 0, 0)) {
pr_err("ion_map_iommu() failed\n");
return -ENOMEM;
}
} }
} else { } else {
pr_err("%s:%d: ion_alloc failed\n", __func__, pr_err("%s:%d: ion_alloc failed\n", __func__,
@ -2629,8 +2638,9 @@ void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
if (!IS_ERR_OR_NULL(mfd->iclient)) { if (!IS_ERR_OR_NULL(mfd->iclient)) {
if (!IS_ERR_OR_NULL(buf->ihdl)) { if (!IS_ERR_OR_NULL(buf->ihdl)) {
ion_unmap_iommu(mfd->iclient, buf->ihdl, if (!(mfd->mem_hid & ION_SECURE))
DISPLAY_DOMAIN, GEN_POOL); ion_unmap_iommu(mfd->iclient, buf->ihdl,
DISPLAY_WRITE_DOMAIN, GEN_POOL);
ion_free(mfd->iclient, buf->ihdl); ion_free(mfd->iclient, buf->ihdl);
pr_debug("%s:%d free writeback imem\n", __func__, pr_debug("%s:%d free writeback imem\n", __func__,
__LINE__); __LINE__);

4
drivers/video/msm/msm_fb.c
View file

@ -1326,7 +1326,7 @@ static int msm_fb_register(struct msm_fb_data_type *mfd)
fbi->fix.smem_start = (unsigned long)fbram_phys; fbi->fix.smem_start = (unsigned long)fbram_phys;
msm_iommu_map_contig_buffer(fbi->fix.smem_start, msm_iommu_map_contig_buffer(fbi->fix.smem_start,
DISPLAY_DOMAIN, DISPLAY_READ_DOMAIN,
GEN_POOL, GEN_POOL,
fbi->fix.smem_len, fbi->fix.smem_len,
SZ_4K, SZ_4K,
@ -1334,7 +1334,7 @@ static int msm_fb_register(struct msm_fb_data_type *mfd)
&(mfd->display_iova)); &(mfd->display_iova));
msm_iommu_map_contig_buffer(fbi->fix.smem_start, msm_iommu_map_contig_buffer(fbi->fix.smem_start,
ROTATOR_DOMAIN, ROTATOR_SRC_DOMAIN,
GEN_POOL, GEN_POOL,
fbi->fix.smem_len, fbi->fix.smem_len,
SZ_4K, SZ_4K,