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ARM: i.MX27 clk: Use of_clk_init() for DT case

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Replace .init_time() hook with of_clk_init() for DT targets.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Alexander Shiyan 2014-06-07 20:09:26 +04:00 committed by Shawn Guo
parent bb9c3398ef
commit c349adde00
3 changed files with 29 additions and 35 deletions
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57
arch/arm/mach-imx/clk-imx27.c
View file

@ -1,32 +1,31 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h" #include "clk.h"
#include "common.h" #include "common.h"
#include "hardware.h" #include "hardware.h"
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) static void __iomem *ccm __initdata;
/* Register offsets */ /* Register offsets */
#define CCM_CSCR IO_ADDR_CCM(0x0) #define CCM_CSCR (ccm + 0x00)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4) #define CCM_MPCTL0 (ccm + 0x04)
#define CCM_MPCTL1 IO_ADDR_CCM(0x8) #define CCM_MPCTL1 (ccm + 0x08)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc) #define CCM_SPCTL0 (ccm + 0x0c)
#define CCM_SPCTL1 IO_ADDR_CCM(0x10) #define CCM_SPCTL1 (ccm + 0x10)
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) #define CCM_OSC26MCTL (ccm + 0x14)
#define CCM_PCDR0 IO_ADDR_CCM(0x18) #define CCM_PCDR0 (ccm + 0x18)
#define CCM_PCDR1 IO_ADDR_CCM(0x1c) #define CCM_PCDR1 (ccm + 0x1c)
#define CCM_PCCR0 IO_ADDR_CCM(0x20) #define CCM_PCCR0 (ccm + 0x20)
#define CCM_PCCR1 IO_ADDR_CCM(0x24) #define CCM_PCCR1 (ccm + 0x24)
#define CCM_CCSR IO_ADDR_CCM(0x28) #define CCM_CCSR (ccm + 0x28)
#define CCM_PMCTL IO_ADDR_CCM(0x2c) #define CCM_PMCTL (ccm + 0x2c)
#define CCM_PMCOUNT IO_ADDR_CCM(0x30) #define CCM_PMCOUNT (ccm + 0x30)
#define CCM_WKGDCTL IO_ADDR_CCM(0x34) #define CCM_WKGDCTL (ccm + 0x34)
#define CCM_CSCR_UPDATE_DIS (1 << 31) #define CCM_CSCR_UPDATE_DIS (1 << 31)
#define CCM_CSCR_SSI2 (1 << 23) #define CCM_CSCR_SSI2 (1 << 23)
@ -93,6 +92,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
{ {
unsigned i; unsigned i;
BUG_ON(!ccm);
clk[dummy] = imx_clk_fixed("dummy", 0); clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckih] = imx_clk_fixed("ckih", fref); clk[ckih] = imx_clk_fixed("ckih", fref);
clk[ckil] = imx_clk_fixed("ckil", 32768); clk[ckil] = imx_clk_fixed("ckil", 32768);
@ -214,6 +215,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
int __init mx27_clocks_init(unsigned long fref) int __init mx27_clocks_init(unsigned long fref)
{ {
ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
_mx27_clocks_init(fref); _mx27_clocks_init(fref);
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
@ -283,29 +286,27 @@ int __init mx27_clocks_init(unsigned long fref)
return 0; return 0;
} }
int __init mx27_clocks_init_dt(void) static void __init mx27_clocks_init_dt(struct device_node *np)
{ {
struct device_node *np; struct device_node *refnp;
u32 fref = 26000000; /* default */ u32 fref = 26000000; /* default */
for_each_compatible_node(np, NULL, "fixed-clock") { for_each_compatible_node(refnp, NULL, "fixed-clock") {
if (!of_device_is_compatible(np, "fsl,imx-osc26m")) if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
continue; continue;
if (!of_property_read_u32(np, "clock-frequency", &fref)) if (!of_property_read_u32(refnp, "clock-frequency", &fref))
break; break;
} }
_mx27_clocks_init(fref); ccm = of_iomap(np, 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); _mx27_clocks_init(fref);
BUG_ON(!np);
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt")); mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
return 0;
} }
CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);

1
arch/arm/mach-imx/common.h
View file

@ -56,7 +56,6 @@ int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref); int mx31_clocks_init(unsigned long fref);
int mx35_clocks_init(void); int mx35_clocks_init(void);
int mx25_clocks_init_dt(void); int mx25_clocks_init_dt(void);
int mx27_clocks_init_dt(void);
int mx31_clocks_init_dt(void); int mx31_clocks_init_dt(void);
struct platform_device *mxc_register_gpio(char *name, int id, struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);

6
arch/arm/mach-imx/imx27-dt.c
View file

@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = {
NULL NULL
}; };
static void __init imx27_timer_init(void)
{
mx27_clocks_init_dt();
}
DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_early = imx27_init_early, .init_early = imx27_init_early,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_time = imx27_timer_init,
.init_machine = imx27_dt_init, .init_machine = imx27_dt_init,
.dt_compat = imx27_dt_board_compat, .dt_compat = imx27_dt_board_compat,
.restart = mxc_restart, .restart = mxc_restart,