mirror of
https://github.com/followmsi/android_kernel_google_msm.git
synced 2024-11-06 23:17:41 +00:00
Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
Bryan Wu
parent
226a6ec311
commit
d310fb4bb7
2 changed files with 89 additions and 98 deletions
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@ -151,7 +151,7 @@
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#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
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#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
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#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
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#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
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#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
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#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
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#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
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@ -634,18 +634,9 @@
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/* PLL_DIV Macros */
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#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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/* VR_CTL Masks */
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#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
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/* VR_CTL Masks */
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#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
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#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
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#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
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#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
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#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
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#define GAIN 0x000C /* Voltage Level Gain */
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#define GAIN_5 0x0000 /* GAIN = 5 */
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#define GAIN_10 0x0004 /* GAIN = 10 */
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#define GAIN_20 0x0008 /* GAIN = 20 */
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#define GAIN_50 0x000C /* GAIN = 50 */
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#define VLEV 0x00F0 /* Internal Voltage Level */
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#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
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@ -660,7 +651,7 @@
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#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
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#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
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#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
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#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
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#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
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#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
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#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
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@ -697,16 +688,16 @@
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#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
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#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
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#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
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#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
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#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
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#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
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#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
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#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
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#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
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#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
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#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
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#define IRQ_TWI 0x00000200 /* TWI Interrupt */
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#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
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#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
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#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
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#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
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#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
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#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
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@ -801,7 +792,7 @@
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#define WDEV_NONE 0x0006 /* no event on roll over */
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#define WDEN 0x0FF0 /* enable watchdog */
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#define WDDIS 0x0AD0 /* disable watchdog */
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#define WDRO 0x8000 /* watchdog rolled over latch */
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#define WDRO 0x8000 /* watchdog rolled over latch */
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/* depreciated WDOG_CTL Register Masks for legacy code */
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@ -882,7 +873,7 @@
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#define NINT 0x01 /* Pending Interrupt */
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#define IIR_TX_READY 0x02 /* UART_THR empty */
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#define IIR_RX_READY 0x04 /* Receive data ready */
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#define IIR_LINE_CHANGE 0x06 /* Receive line status */
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#define IIR_LINE_CHANGE 0x06 /* Receive line status */
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#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
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/* UARTx_GCTL Masks */
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@ -1638,12 +1629,12 @@
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/* entry addresses of the user-callable Boot ROM functions */
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#define _BOOTROM_RESET 0xEF000000
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#define _BOOTROM_FINAL_INIT 0xEF000002
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#define _BOOTROM_RESET 0xEF000000
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#define _BOOTROM_FINAL_INIT 0xEF000002
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#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
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#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
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#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
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#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
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#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
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#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
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#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
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#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
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#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
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#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
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@ -1771,71 +1762,71 @@
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/* Bit masks for CNT_CONFIG */
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#define CNTE 0x1 /* Counter Enable */
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#define nCNTE 0x0
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#define nCNTE 0x0
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#define DEBE 0x2 /* Debounce Enable */
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#define nDEBE 0x0
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#define nDEBE 0x0
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#define CDGINV 0x10 /* CDG Pin Polarity Invert */
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#define nCDGINV 0x0
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#define nCDGINV 0x0
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#define CUDINV 0x20 /* CUD Pin Polarity Invert */
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#define nCUDINV 0x0
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#define nCUDINV 0x0
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#define CZMINV 0x40 /* CZM Pin Polarity Invert */
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#define nCZMINV 0x0
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#define nCZMINV 0x0
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#define CNTMODE 0x700 /* Counter Operating Mode */
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#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
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#define nZMZC 0x0
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#define nZMZC 0x0
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#define BNDMODE 0x3000 /* Boundary register Mode */
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#define INPDIS 0x8000 /* CUG and CDG Input Disable */
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#define nINPDIS 0x0
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#define nINPDIS 0x0
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/* Bit masks for CNT_IMASK */
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#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
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#define nICIE 0x0
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#define nICIE 0x0
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#define UCIE 0x2 /* Up count Interrupt Enable */
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#define nUCIE 0x0
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#define nUCIE 0x0
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#define DCIE 0x4 /* Down count Interrupt Enable */
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#define nDCIE 0x0
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#define nDCIE 0x0
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#define MINCIE 0x8 /* Min Count Interrupt Enable */
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#define nMINCIE 0x0
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#define nMINCIE 0x0
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#define MAXCIE 0x10 /* Max Count Interrupt Enable */
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#define nMAXCIE 0x0
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#define nMAXCIE 0x0
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#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
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#define nCOV31IE 0x0
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#define nCOV31IE 0x0
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#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
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#define nCOV15IE 0x0
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#define nCOV15IE 0x0
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#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
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#define nCZEROIE 0x0
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#define nCZEROIE 0x0
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#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
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#define nCZMIE 0x0
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#define nCZMIE 0x0
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#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
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#define nCZMEIE 0x0
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#define nCZMEIE 0x0
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#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
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#define nCZMZIE 0x0
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#define nCZMZIE 0x0
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/* Bit masks for CNT_STATUS */
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#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
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#define nICII 0x0
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#define nICII 0x0
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#define UCII 0x2 /* Up count Interrupt Identifier */
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#define nUCII 0x0
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#define nUCII 0x0
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#define DCII 0x4 /* Down count Interrupt Identifier */
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#define nDCII 0x0
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#define nDCII 0x0
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#define MINCII 0x8 /* Min Count Interrupt Identifier */
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#define nMINCII 0x0
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#define nMINCII 0x0
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#define MAXCII 0x10 /* Max Count Interrupt Identifier */
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#define nMAXCII 0x0
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#define nMAXCII 0x0
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#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
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#define nCOV31II 0x0
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#define nCOV31II 0x0
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#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
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#define nCOV15II 0x0
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#define nCOV15II 0x0
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#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
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#define nCZEROII 0x0
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#define nCZEROII 0x0
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#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
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#define nCZMII 0x0
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#define nCZMII 0x0
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#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
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#define nCZMEII 0x0
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#define nCZMEII 0x0
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#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
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#define nCZMZII 0x0
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#define nCZMZII 0x0
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/* Bit masks for CNT_COMMAND */
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@ -1843,7 +1834,7 @@
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#define W1LMIN 0xf0 /* Load Min Register */
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#define W1LMAX 0xf00 /* Load Max Register */
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#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
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#define nW1ZMONCE 0x0
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#define nW1ZMONCE 0x0
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/* Bit masks for CNT_DEBOUNCE */
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@ -1853,15 +1844,15 @@
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#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
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#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
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#define nFIEN 0x0
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#define nFIEN 0x0
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#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
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#define nFTESTDEC 0x0
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#define nFTESTDEC 0x0
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#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
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#define nFWRTEST 0x0
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#define nFWRTEST 0x0
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#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
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#define nFRDEN 0x0
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#define nFRDEN 0x0
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#define FWREN 0x8000 /* OTP/Fuse Write Enable */
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#define nFWREN 0x0
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#define nFWREN 0x0
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/* Bit masks for OTP_BEN */
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@ -1870,15 +1861,15 @@
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/* Bit masks for OTP_STATUS */
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#define FCOMP 0x1 /* OTP/Fuse Access Complete */
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#define nFCOMP 0x0
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#define nFCOMP 0x0
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#define FERROR 0x2 /* OTP/Fuse Access Error */
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#define nFERROR 0x0
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#define nFERROR 0x0
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#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
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#define nMMRGLOAD 0x0
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#define nMMRGLOAD 0x0
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#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
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#define nMMRGLOCK 0x0
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#define nMMRGLOCK 0x0
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#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
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#define nFPGMEN 0x0
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#define nFPGMEN 0x0
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/* Bit masks for OTP_TIMING */
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@ -1892,42 +1883,42 @@
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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#define nEMUDABL 0x0
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#define nEMUDABL 0x0
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#define RSTDABL 0x2 /* Reset Disable */
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#define nRSTDABL 0x0
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#define nRSTDABL 0x0
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#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
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#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
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#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
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#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
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#define nDMA0OVR 0x0
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#define nDMA0OVR 0x0
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#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
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#define nDMA1OVR 0x0
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#define nDMA1OVR 0x0
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#define EMUOVR 0x4000 /* Emulation Override */
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#define nEMUOVR 0x0
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#define nEMUOVR 0x0
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#define OTPSEN 0x8000 /* OTP Secrets Enable. */
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#define nOTPSEN 0x0
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#define nOTPSEN 0x0
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#define L2DABL 0x70000 /* L2 Memory Disable. */
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/* Bit masks for SECURE_CONTROL */
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#define SECURE0 0x1 /* SECURE 0 */
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#define nSECURE0 0x0
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#define nSECURE0 0x0
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#define SECURE1 0x2 /* SECURE 1 */
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#define nSECURE1 0x0
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#define nSECURE1 0x0
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#define SECURE2 0x4 /* SECURE 2 */
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#define nSECURE2 0x0
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#define nSECURE2 0x0
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#define SECURE3 0x8 /* SECURE 3 */
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#define nSECURE3 0x0
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#define nSECURE3 0x0
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/* Bit masks for SECURE_STATUS */
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#define SECMODE 0x3 /* Secured Mode Control State */
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#define NMI 0x4 /* Non Maskable Interrupt */
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#define nNMI 0x0
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#define nNMI 0x0
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#define AFVALID 0x8 /* Authentication Firmware Valid */
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#define nAFVALID 0x0
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#define nAFVALID 0x0
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#define AFEXIT 0x10 /* Authentication Firmware Exit */
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#define nAFEXIT 0x0
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#define nAFEXIT 0x0
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#define SECSTAT 0xe0 /* Secure Status */
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/* Bit masks for NFC_CTL */
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@ -1935,60 +1926,60 @@
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#define WR_DLY 0xf /* Write Strobe Delay */
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#define RD_DLY 0xf0 /* Read Strobe Delay */
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#define NWIDTH 0x100 /* NAND Data Width */
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#define nNWIDTH 0x0
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#define nNWIDTH 0x0
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#define PG_SIZE 0x200 /* Page Size */
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#define nPG_SIZE 0x0
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#define nPG_SIZE 0x0
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/* Bit masks for NFC_STAT */
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#define NBUSY 0x1 /* Not Busy */
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#define nNBUSY 0x0
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#define nNBUSY 0x0
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#define WB_FULL 0x2 /* Write Buffer Full */
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#define nWB_FULL 0x0
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#define nWB_FULL 0x0
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#define PG_WR_STAT 0x4 /* Page Write Pending */
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#define nPG_WR_STAT 0x0
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#define nPG_WR_STAT 0x0
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#define PG_RD_STAT 0x8 /* Page Read Pending */
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#define nPG_RD_STAT 0x0
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#define nPG_RD_STAT 0x0
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#define WB_EMPTY 0x10 /* Write Buffer Empty */
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#define nWB_EMPTY 0x0
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#define nWB_EMPTY 0x0
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/* Bit masks for NFC_IRQSTAT */
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#define NBUSYIRQ 0x1 /* Not Busy IRQ */
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#define nNBUSYIRQ 0x0
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#define nNBUSYIRQ 0x0
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#define WB_OVF 0x2 /* Write Buffer Overflow */
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#define nWB_OVF 0x0
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#define nWB_OVF 0x0
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#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
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#define nWB_EDGE 0x0
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#define nWB_EDGE 0x0
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#define RD_RDY 0x8 /* Read Data Ready */
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#define nRD_RDY 0x0
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#define nRD_RDY 0x0
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#define WR_DONE 0x10 /* Page Write Done */
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#define nWR_DONE 0x0
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#define nWR_DONE 0x0
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/* Bit masks for NFC_IRQMASK */
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#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
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#define nMASK_BUSYIRQ 0x0
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#define nMASK_BUSYIRQ 0x0
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#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
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#define nMASK_WBOVF 0x0
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#define nMASK_WBOVF 0x0
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#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
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#define nMASK_WBEMPTY 0x0
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#define nMASK_WBEMPTY 0x0
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#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
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#define nMASK_RDRDY 0x0
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#define nMASK_RDRDY 0x0
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#define MASK_WRDONE 0x10 /* Mask Write Done */
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#define nMASK_WRDONE 0x0
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#define nMASK_WRDONE 0x0
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/* Bit masks for NFC_RST */
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#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
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#define nECC_RST 0x0
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#define nECC_RST 0x0
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/* Bit masks for NFC_PGCTL */
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#define PG_RD_START 0x1 /* Page Read Start */
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#define nPG_RD_START 0x0
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#define nPG_RD_START 0x0
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#define PG_WR_START 0x2 /* Page Write Start */
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#define nPG_WR_START 0x0
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#define nPG_WR_START 0x0
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/* Bit masks for NFC_ECC0 */
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@ -216,7 +216,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
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wakeup |= KPADWE;
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break;
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#endif
|
||||
#ifdef IRQ_CNT
|
||||
#ifdef CONFIG_BF54x
|
||||
case IRQ_CNT:
|
||||
wakeup |= ROTWE;
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in a new issue