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msm: pil-pronto: Add delay after de-assertion of CLK_CTL_WCNSS_RESTART_BIT

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A previous change introduced a udelay after de-asserting this
bit in another place in this driver, but this second de-assertion
was missed. Add it for similar reasons: the subsystem cannot be
accessed until the reset de-assertion has finished propagating.

Change-Id: I97abe8b81cd599ab3187f989429501d35f50aec6
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
This commit is contained in:
Matt Wagantall 2012-08-03 18:29:47 -07:00 committed by Stephen Boyd
parent 450560c84c
commit d450fa4cd7
1 changed files with 2 additions and 1 deletions
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3
arch/arm/mach-msm/pil-pronto.c
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@ -207,11 +207,12 @@ static int pil_pronto_shutdown(struct pil_desc *pil)
mb();
usleep_range(1000, 2000);
/* Deassert reset to Pronto */
/* Deassert reset to subsystem and wait for propagation */
reg = readl_relaxed(drv->reset_base);
reg &= ~CLK_CTL_WCNSS_RESTART_BIT;
writel_relaxed(reg, drv->reset_base);
mb();
udelay(2);
return 0;
}