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msm: clock-8960: Store current HDMI PLL rate in clk->rate
This allows for a vdd_class, which reference clk->rate, to be used with the HDMI PLL. It also removes the need to have a .get_rate op implemented. Change-Id: I1fd7eba16fa1e1af56513d400e58fdfdaff931e4 Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
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parent
dd4d59b117
commit
dcbc3173b6
3 changed files with 3 additions and 15 deletions
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@ -3912,11 +3912,6 @@ static void hdmi_pll_clk_disable(struct clk *c)
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spin_unlock_irqrestore(&local_clock_reg_lock, flags);
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}
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static unsigned long hdmi_pll_clk_get_rate(struct clk *c)
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{
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return hdmi_pll_get_rate();
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}
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static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
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{
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return &pxo_clk.c;
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@ -3925,7 +3920,6 @@ static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
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static struct clk_ops clk_ops_hdmi_pll = {
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.enable = hdmi_pll_clk_enable,
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.disable = hdmi_pll_clk_disable,
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.get_rate = hdmi_pll_clk_get_rate,
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.get_parent = hdmi_pll_clk_get_parent,
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};
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@ -3975,8 +3969,10 @@ static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
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void set_rate_tv(struct rcg_clk *rcg, struct clk_freq_tbl *nf)
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{
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unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
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if (pll_rate)
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if (pll_rate) {
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hdmi_pll_set_rate(pll_rate);
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hdmi_pll_clk.rate = pll_rate;
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}
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set_rate_mnd(rcg, nf);
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}
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@ -90,7 +90,6 @@
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#define PLL_PWRDN_B BIT(3)
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#define PD_PLL BIT(1)
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static unsigned current_rate;
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static unsigned hdmi_pll_on;
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int hdmi_pll_enable(void)
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@ -219,11 +218,6 @@ void hdmi_pll_disable(void)
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hdmi_pll_on = 0;
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}
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unsigned hdmi_pll_get_rate(void)
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{
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return current_rate;
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}
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int hdmi_pll_set_rate(unsigned rate)
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{
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unsigned int set_power_dwn = 0;
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@ -378,7 +372,6 @@ int hdmi_pll_set_rate(unsigned rate)
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if (set_power_dwn)
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hdmi_pll_enable();
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current_rate = rate;
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if (!ahb_enabled)
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writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
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@ -15,7 +15,6 @@
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int hdmi_pll_enable(void);
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void hdmi_pll_disable(void);
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unsigned hdmi_pll_get_rate(void);
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int hdmi_pll_set_rate(unsigned rate);
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#endif
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