diff --git a/arch/arm/configs/mako-perf_defconfig b/arch/arm/configs/mako-perf_defconfig new file mode 100755 index 000000000000..b15cb02b9425 --- /dev/null +++ b/arch/arm/configs/mako-perf_defconfig @@ -0,0 +1,451 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="-perf" +CONFIG_SYSVIPC=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_ASHMEM=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8930=y +CONFIG_ARCH_APQ8064=y +CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y +CONFIG_MACH_APQ8064_MTP=y +CONFIG_BOARD_HEADER_FILE="mach/lge/board_mako.h" +CONFIG_MACH_APQ8064_MAKO=y +# CONFIG_MSM_STACKED_MEMORY is not set +CONFIG_KERNEL_PMEM_EBI_REGION=y +# CONFIG_MSM_FIQ_SUPPORT is not set +# CONFIG_MSM_PROC_COMM is not set +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_PKG4=y +CONFIG_MSM_BAM_DMUX=y +CONFIG_MSM_DSPS=y +CONFIG_MSM_IPC_ROUTER=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +# CONFIG_MSM_HW3D is not set +CONFIG_MSM_PIL_QDSP6V4=y +CONFIG_MSM_PIL_RIVA=y +CONFIG_MSM_PIL_TZAPPS=y +CONFIG_MSM_PIL_DSPS=y +CONFIG_MSM_PIL_VIDC=y +CONFIG_MSM_PIL_GSS=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_MODEM_8960=y +CONFIG_MSM_LPASS_8960=y +CONFIG_MSM_WCNSS_SSR_8960=y +CONFIG_MSM_GSS_SSR_8064=y +CONFIG_MSM_TZ_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +CONFIG_MSM_BUS_SCALING=y +CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y +CONFIG_MSM_WATCHDOG=y +CONFIG_MSM_DLOAD_MODE=y +CONFIG_MSM_QDSS=y +CONFIG_MSM_SLEEP_STATS=y +CONFIG_MSM_RTB=y +CONFIG_MSM_RTB_SEPARATE_CPUS=y +CONFIG_MSM_CACHE_ERP=y +CONFIG_MSM_L1_ERR_PANIC=y +CONFIG_MSM_L2_ERP_2BIT_PANIC=y +CONFIG_MSM_DCVS=y +CONFIG_MSM_CACHE_DUMP=y +CONFIG_MSM_CACHE_DUMP_ON_PANIC=y +CONFIG_MSM_HSIC_SYSMON=y +CONFIG_STRICT_MEMORY_RWX=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_VMALLOC_RESERVE=0x19000000 +CONFIG_COMPACTION=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_CP_ACCESS=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_WAKELOCK=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_L2TP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCISMD=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_WEXT is not set +CONFIG_RFKILL=y +CONFIG_GENLOCK=y +CONFIG_GENLOCK_MISCDEVICE=y +CONFIG_CONNECTOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_UID_STAT=y +CONFIG_HAPTIC_ISA1200=y +CONFIG_PMIC8XXX_VIBRATOR=y +CONFIG_QSEECOM=y +CONFIG_USB_HSIC_SMSC_HUB=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_KS8851=m +# CONFIG_MSM_RMNET is not set +CONFIG_MSM_RMNET_BAM=y +CONFIG_MSM_RMNET_SMUX=y +CONFIG_USB_USBNET=y +CONFIG_MSM_RMNET_USB=y +CONFIG_WCNSS_CORE=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_PMIC8XXX=y +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PMIC8XXX_PWRKEY=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_N_SMUX=y +CONFIG_N_SMUX_LOOPBACK=y +CONFIG_SMUX_CTL=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_HSL=y +CONFIG_SERIAL_MSM_HSL_CONSOLE=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MSM is not set +CONFIG_I2C_QUP=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SLIMBUS_MSM_CTRL=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SX150X=y +CONFIG_POWER_SUPPLY=y +# CONFIG_BATTERY_MSM is not set +CONFIG_ISL9519_CHARGER=y +CONFIG_PM8921_CHARGER=y +CONFIG_PM8921_BMS=y +CONFIG_SENSORS_PM8XXX_ADC=y +CONFIG_THERMAL=y +CONFIG_THERMAL_TSENS8960=y +CONFIG_THERMAL_PM8XXX=y +CONFIG_THERMAL_MONITOR=y +CONFIG_MFD_PM8921_CORE=y +CONFIG_MFD_PM8821_CORE=y +CONFIG_MFD_PM8038_CORE=y +CONFIG_MFD_PM8XXX_SPK=y +CONFIG_MFD_PM8XXX_BATT_ALARM=y +CONFIG_WCD9304_CODEC=y +CONFIG_WCD9310_CODEC=y +CONFIG_REGULATOR_PM8XXX=y +CONFIG_REGULATOR_MSM_GPIO=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_MSM_KGSL=y +CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y +CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24 +CONFIG_FB=y +CONFIG_FB_VIRTUAL=y +CONFIG_FB_MSM=y +# CONFIG_FB_MSM_BACKLIGHT is not set +CONFIG_FB_MSM_LOGO=y +CONFIG_FB_MSM_TRIPLE_BUFFER=y +CONFIG_FB_MSM_MDP40=y +CONFIG_FB_MSM_OVERLAY=y +CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y +CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y +CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y +CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT=y +CONFIG_FB_MSM_HDMI_MSM_PANEL=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_MSM8960=y +CONFIG_HID_APPLE=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EHSET=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_MSM_HSIC=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_CSVT=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_QCOM_DIAG_BRIDGE=y +CONFIG_USB_QCOM_MDM_BRIDGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CI13XXX_MSM=y +CONFIG_USB_G_ANDROID=y +CONFIG_USB_ANDROID_RMNET_CTRL_SMD=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_MSM=y +CONFIG_MMC_MSM_CARD_HW_DETECTION=y +CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y +# CONFIG_MMC_MSM_SDC2_SUPPORT is not set +CONFIG_MMC_MSM_SDC3_SUPPORT=y +CONFIG_MMC_MSM_SDC3_WP_SUPPORT=y +CONFIG_MMC_MSM_SPS_SUPPORT=y +CONFIG_LEDS_PM8XXX=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MSM is not set +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_MSM_SSBI=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_BAMDMA=y +CONFIG_MSM_IOMMU=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT4_FS=y +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_CIFS=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_USER=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEV_QCRYPTO=m +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCEDEV=m +CONFIG_CRC_CCITT=y diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 38f1d2b94ff7..8e0d5eebd157 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -867,6 +867,8 @@ config MACH_FSM9XXX_SURF endmenu +source "arch/arm/mach-msm/lge/Kconfig" + config MSM_STACKED_MEMORY bool "Stacked Memory" default y diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index f763d497ca2a..10ee3d4dfe87 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -281,7 +281,9 @@ obj-$(CONFIG_MACH_MSM8930_MTP) += board-8930-all.o board-8930-regulator.o obj-$(CONFIG_MACH_MSM8930_FLUID) += board-8930-all.o board-8930-regulator.o obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o obj-$(CONFIG_MACH_APQ8064_CDP) += board-8064-all.o board-8064-regulator.o +ifndef CONFIG_MACH_LGE # FIXME: will be fixed obj-$(CONFIG_MACH_APQ8064_MTP) += board-8064-all.o board-8064-regulator.o +endif obj-$(CONFIG_MACH_APQ8064_LIQUID) += board-8064-all.o board-8064-regulator.o obj-$(CONFIG_MACH_MPQ8064_HRD) += board-8064-all.o board-8064-regulator.o obj-$(CONFIG_MACH_MPQ8064_DTV) += board-8064-all.o board-8064-regulator.o @@ -300,6 +302,9 @@ obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-mmc.o board-sapphire-wifi.o obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-rfkill.o msm_vibrator.o +obj-$(CONFIG_MACH_LGE) += board-8960-all.o board-8960-regulator.o +obj-$(CONFIG_MACH_LGE) += lge/ + CFLAGS_msm_vibrator.o += -Idrivers/staging/android CFLAGS_board-9615.o += -Idrivers/usb/gadget diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c old mode 100644 new mode 100755 index df5f7488f9ad..90e8d2c3c816 --- a/arch/arm/mach-msm/clock-8960.c +++ b/arch/arm/mach-msm/clock-8960.c @@ -5198,13 +5198,13 @@ static struct clk_lookup msm_clocks_8064[] = { CLK_LOOKUP("core_clk", gp0_clk.c, ""), CLK_LOOKUP("core_clk", gp1_clk.c, ""), CLK_LOOKUP("core_clk", gp2_clk.c, ""), - CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"), + CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), - CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), + CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, "msm_serial_hsl.0"), CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""), CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""), - CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"), + CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"), CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), @@ -5246,10 +5246,11 @@ static struct clk_lookup msm_clocks_8064[] = { CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"), CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"), CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), - CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"), + CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, ""), CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"), CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), + CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "msm_serial_hsl.0"), CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"), CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"), diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c index c6a0441d9673..ac13819ce055 100644 --- a/arch/arm/mach-msm/devices-8064.c +++ b/arch/arm/mach-msm/devices-8064.c @@ -49,6 +49,7 @@ /* Address of GSBI blocks */ #define MSM_GSBI1_PHYS 0x12440000 +#define MSM_GSBI2_PHYS 0x13440000 #define MSM_GSBI3_PHYS 0x16200000 #define MSM_GSBI4_PHYS 0x16300000 #define MSM_GSBI5_PHYS 0x1A200000 @@ -58,10 +59,13 @@ /* GSBI UART devices */ #define MSM_UART1DM_PHYS (MSM_GSBI1_PHYS + 0x10000) #define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000) +#define MSM_UART4DM_PHYS (MSM_GSBI4_PHYS + 0x40000) +#define MSM_UART6DM_PHYS (MSM_GSBI6_PHYS + 0x40000) #define MSM_UART7DM_PHYS (MSM_GSBI7_PHYS + 0x40000) /* GSBI QUP devices */ #define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x20000) +#define MSM_GSBI2_QUP_PHYS (MSM_GSBI2_PHYS + 0x20000) #define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000) #define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000) #define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000) @@ -285,6 +289,33 @@ struct platform_device apq8064_device_qup_i2c_gsbi3 = { .resource = resources_qup_i2c_gsbi3, }; +static struct resource resources_uart_gsbi4[] = { + { + .start = GSBI4_UARTDM_IRQ, + .end = GSBI4_UARTDM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART4DM_PHYS, + .end = MSM_UART4DM_PHYS + PAGE_SIZE - 1, + .name = "uartdm_resource", + .flags = IORESOURCE_MEM, + }, + { + .start = MSM_GSBI4_PHYS, + .end = MSM_GSBI4_PHYS + PAGE_SIZE - 1, + .name = "gsbi_resource", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device apq8064_device_uart_gsbi4 = { + .name = "msm_serial_hsl", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart_gsbi4), + .resource = resources_uart_gsbi4, +}; + static struct resource resources_qup_i2c_gsbi4[] = { { .name = "gsbi_qup_i2c_addr", diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 3587672323b3..e3e7de44464e 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -84,6 +84,7 @@ extern struct platform_device msm8960_device_ebi1_ch1_erp; extern struct platform_device apq8064_device_uart_gsbi1; extern struct platform_device apq8064_device_uart_gsbi3; +extern struct platform_device apq8064_device_uart_gsbi4; extern struct platform_device apq8064_device_uart_gsbi7; extern struct platform_device apq8064_device_qup_i2c_gsbi1; extern struct platform_device apq8064_device_qup_i2c_gsbi3; diff --git a/arch/arm/mach-msm/include/mach/board_lge.h b/arch/arm/mach-msm/include/mach/board_lge.h new file mode 100644 index 000000000000..e95512b1deb4 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/board_lge.h @@ -0,0 +1,151 @@ +/* arch/arm/mach-msm/include/mach/board_lge.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_BOARD_LGE_H +#define __ASM_ARCH_MSM_BOARD_LGE_H + +#ifdef CONFIG_ANDROID_RAM_CONSOLE +#define LGE_RAM_CONSOLE_SIZE (124*SZ_1K * 2) +#endif + +#ifdef CONFIG_LGE_HANDLE_PANIC +#define LGE_CRASH_LOG_SIZE (4*SZ_1K) +#endif + +typedef enum { + HW_REV_EVB1 = 0, + HW_REV_EVB2, + HW_REV_A, + HW_REV_B, + HW_REV_C, + HW_REV_D, + HW_REV_E, + HW_REV_F, + HW_REV_G, + HW_REV_H, + HW_REV_1_0, + HW_REV_1_1, + HW_REV_1_2, + HW_REV_MAX +} hw_rev_type; + +hw_rev_type lge_get_board_revno(void); + +#ifdef CONFIG_LGE_PM +/*Classified the ADC value for cable detection */ +typedef enum { + NO_INIT_CABLE = 0, + CABLE_MHL_1K, + CABLE_U_28P7K, + CABLE_28P7K, + CABLE_56K, + CABLE_100K, + CABLE_130K, + CABLE_180K, + CABLE_200K, + CABLE_220K, + CABLE_270K, + CABLE_330K, + CABLE_620K, + CABLE_910K, + CABLE_NONE +} acc_cable_type; + +struct chg_cable_info { + acc_cable_type cable_type; + unsigned ta_ma; + unsigned usb_ma; +}; + +int lge_pm_get_cable_info(struct chg_cable_info *); +void lge_pm_read_cable_info(void); +acc_cable_type lge_pm_get_cable_type(void); +unsigned lge_pm_get_ta_current(void); +unsigned lge_pm_get_usb_current(void); +#endif + +#ifdef CONFIG_LGE_PM_BATTERY_ID_CHECKER +enum { + BATT_UNKNOWN, + BATT_DS2704_N = 17, + BATT_DS2704_L = 32, + BATT_ISL6296_N = 73, + BATT_ISL6296_L = 94, +}; +extern int lge_battery_info; +#endif + +#ifdef CONFIG_LGE_KCAL +struct kcal_platform_data { + int (*set_values) (int r, int g, int b); + int (*get_values) (int *r, int *g, int *b); + int (*refresh_display) (void); +}; +#endif + +#ifdef CONFIG_LGE_PM +struct pseudo_batt_info_type { + int mode; + int id; + int therm; + int temp; + int volt; + int capacity; + int charging; +}; +#endif +int __init lge_get_uart_mode(void); + +#if defined(CONFIG_LGE_NFC_PN544) +void __init lge_add_nfc_devices(void); +#endif +/* from androidboot.mode */ +enum lge_boot_mode_type { + LGE_BOOT_MODE_NORMAL = 0, + LGE_BOOT_MODE_CHARGER, + LGE_BOOT_MODE_CHARGERLOGO, + LGE_BOOT_MODE_FACTORY, + LGE_BOOT_MODE_FACTORY2, + LGE_BOOT_MODE_PIFBOOT, + LGE_BOOT_MODE_PIFBOOT2, +}; +#ifdef CONFIG_ANDROID_RAM_CONSOLE +void __init lge_add_ramconsole_devices(void); +#endif + +#ifdef CONFIG_LGE_HANDLE_PANIC +void __init lge_add_panic_handler_devices(void); +int lge_get_magic_for_subsystem(void); +void lge_set_magic_for_subsystem(const char *subsys_name); +#endif + +#ifdef CONFIG_LGE_QFPROM_INTERFACE +void __init lge_add_qfprom_devices(void); +#endif + +enum lge_boot_mode_type lge_get_boot_mode(void); +int lge_get_factory_boot(void); + +#ifdef CONFIG_LGE_BOOT_TIME_CHECK +void __init lge_add_boot_time_checker(void); +#endif + +#ifdef CONFIG_LGE_ECO_MODE +void __init lge_add_lge_kernel_devices(void); +#endif +#endif // __ASM_ARCH_MSM_BOARD_LGE_H diff --git a/arch/arm/mach-msm/include/mach/lge/board_mako.h b/arch/arm/mach-msm/include/mach/lge/board_mako.h new file mode 100644 index 000000000000..947ea544eca2 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/lge/board_mako.h @@ -0,0 +1,93 @@ +/* arch/arm/mach-msm/include/mach/board_mako.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_BOARD_MAKO_H +#define __ASM_ARCH_MSM_BOARD_MAKO_H + +#ifdef CONFIG_LGE_PM +#define ADC_CHANGE_REV HW_REV_EVB1 +#define IBAT_CURRENT 825 + +/* Ref resistance value = 665K */ +#define ADC_NO_INIT_CABLE 0 +#define ADC_CABLE_MHL_1K 30000 +#define ADC_CABLE_U_28P7K 60000 +#define ADC_CABLE_28P7K 110000 +#define ADC_CABLE_56K 185000 +#define ADC_CABLE_100K 265000 +#define ADC_CABLE_130K 340000 +#define ADC_CABLE_180K 400000 +#define ADC_CABLE_200K 431000 +#define ADC_CABLE_220K 485000 +#define ADC_CABLE_270K 560000 +#define ADC_CABLE_330K 735000 +#define ADC_CABLE_620K 955000 +#define ADC_CABLE_910K 1140000 +#define ADC_CABLE_NONE 1800000 + +/* Ref resistance value = 200K */ +#define ADC_NO_INIT_CABLE2 0 +#define ADC_CABLE_MHL_1K2 50000 +#define ADC_CABLE_U_28P7K2 200000 +#define ADC_CABLE_28P7K2 300000 +#define ADC_CABLE_56K2 490000 +#define ADC_CABLE_100K2 650000 +#define ADC_CABLE_130K2 780000 +#define ADC_CABLE_180K2 875000 +#define ADC_CABLE_200K2 920000 +#define ADC_CABLE_220K2 988000 +#define ADC_CABLE_270K2 1077000 +#define ADC_CABLE_330K2 1294000 +#define ADC_CABLE_620K2 1418000 +#define ADC_CABLE_910K2 1600000 +#define ADC_CABLE_NONE2 1800000 + +#define C_NO_INIT_TA_MA 0 +#define C_MHL_1K_TA_MA 500 +#define C_U_28P7K_TA_MA 500 +#define C_28P7K_TA_MA 500 +#define C_56K_TA_MA 1500 /* it will be changed in future */ +#define C_100K_TA_MA 500 +#define C_130K_TA_MA 1500 +#define C_180K_TA_MA 700 +#define C_200K_TA_MA 700 +#define C_220K_TA_MA 900 +#define C_270K_TA_MA 800 +#define C_330K_TA_MA 500 +#define C_620K_TA_MA 500 +#define C_910K_TA_MA 1500//[ORG]500 +#define C_NONE_TA_MA 900 //900mA for open cable + +#define C_NO_INIT_USB_MA 0 +#define C_MHL_1K_USB_MA 500 +#define C_U_28P7K_USB_MA 500 +#define C_28P7K_USB_MA 500 +#define C_56K_USB_MA 1500 /* it will be changed in future */ +#define C_100K_USB_MA 500 +#define C_130K_USB_MA 1500 +#define C_180K_USB_MA 500 +#define C_200K_USB_MA 500 +#define C_220K_USB_MA 500 +#define C_270K_USB_MA 500 +#define C_330K_USB_MA 500 +#define C_620K_USB_MA 500 +#define C_910K_USB_MA 1500//[ORG]500 +#define C_NONE_USB_MA 500 +#endif + +#endif // __ASM_ARCH_MSM_BOARD_MAKO_H diff --git a/arch/arm/mach-msm/lge/Kconfig b/arch/arm/mach-msm/lge/Kconfig new file mode 100644 index 000000000000..544aac314950 --- /dev/null +++ b/arch/arm/mach-msm/lge/Kconfig @@ -0,0 +1,11 @@ +config MACH_LGE + bool + +menu "LGE Board Selection" +source "arch/arm/mach-msm/lge/Kconfig.board" +endmenu + + +menu "LGE Specific Patches" + +endmenu diff --git a/arch/arm/mach-msm/lge/Kconfig.board b/arch/arm/mach-msm/lge/Kconfig.board new file mode 100644 index 000000000000..38598e3ed132 --- /dev/null +++ b/arch/arm/mach-msm/lge/Kconfig.board @@ -0,0 +1,7 @@ +# +# Inlcude the specific Kconfig file for LGE board +# + +# MAKO +source "arch/arm/mach-msm/lge/mako/Kconfig" + diff --git a/arch/arm/mach-msm/lge/Makefile b/arch/arm/mach-msm/lge/Makefile new file mode 100644 index 000000000000..bbf23bb07c7e --- /dev/null +++ b/arch/arm/mach-msm/lge/Makefile @@ -0,0 +1,5 @@ +subdir-ccflags-$(CONFIG_ARCH_MSM) += -Iarch/arm/mach-msm + +-include $(src)/Makefile.board + +obj-$(CONFIG_MACH_LGE) += devices_lge.o diff --git a/arch/arm/mach-msm/lge/Makefile.board b/arch/arm/mach-msm/lge/Makefile.board new file mode 100644 index 000000000000..aa94e36316dd --- /dev/null +++ b/arch/arm/mach-msm/lge/Makefile.board @@ -0,0 +1,6 @@ +# +# Makefile for the LGE board +# + +# MAKO +obj-$(CONFIG_MACH_APQ8064_MAKO) += mako/ diff --git a/arch/arm/mach-msm/lge/devices_lge.c b/arch/arm/mach-msm/lge/devices_lge.c new file mode 100644 index 000000000000..49c8225a8358 --- /dev/null +++ b/arch/arm/mach-msm/lge/devices_lge.c @@ -0,0 +1,404 @@ +/* Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#ifdef CONFIG_LGE_PM +#include +#include +#endif + +#include + +#ifdef CONFIG_LGE_PM +#include CONFIG_BOARD_HEADER_FILE +#endif + +#ifdef CONFIG_LGE_BOOT_TIME_CHECK +#include "lge_boot_time_checker.h" +#endif + +/* setting whether uart console is enalbed or disabled */ +static int uart_console_mode = 0; + +int __init lge_get_uart_mode(void) +{ + return uart_console_mode; +} + +static int __init lge_uart_mode(char *uart_mode) +{ + if (!strncmp("enable", uart_mode, 5)) { + printk(KERN_INFO"UART CONSOLE : enable\n"); + uart_console_mode = 1; + } + else + printk(KERN_INFO"UART CONSOLE : disable\n"); + + return 1; +} +__setup("uart_console=", lge_uart_mode); + + +#ifdef CONFIG_LGE_PM +/* Implement cable detection */ +struct chg_cable_info_table { + int threshhold; + acc_cable_type type; + unsigned ta_ma; + unsigned usb_ma; +}; + +/* This table is only for J1 */ +static struct chg_cable_info_table pm8921_acc_cable_type_data[]={ + {ADC_NO_INIT_CABLE, NO_INIT_CABLE, C_NO_INIT_TA_MA, C_NO_INIT_USB_MA}, + {ADC_CABLE_MHL_1K, CABLE_MHL_1K, C_MHL_1K_TA_MA, C_MHL_1K_USB_MA}, + {ADC_CABLE_U_28P7K, CABLE_U_28P7K, C_U_28P7K_TA_MA, C_U_28P7K_USB_MA}, + {ADC_CABLE_28P7K, CABLE_28P7K, C_28P7K_TA_MA, C_28P7K_USB_MA}, + {ADC_CABLE_56K, CABLE_56K, C_56K_TA_MA, C_56K_USB_MA}, + {ADC_CABLE_100K, CABLE_100K, C_100K_TA_MA, C_100K_USB_MA}, + {ADC_CABLE_130K, CABLE_130K, C_130K_TA_MA, C_130K_USB_MA}, + {ADC_CABLE_180K, CABLE_180K, C_180K_TA_MA, C_180K_USB_MA}, + {ADC_CABLE_200K, CABLE_200K, C_200K_TA_MA, C_200K_USB_MA}, + {ADC_CABLE_220K, CABLE_220K, C_220K_TA_MA, C_220K_USB_MA}, + {ADC_CABLE_270K, CABLE_270K, C_270K_TA_MA, C_270K_USB_MA}, + {ADC_CABLE_330K, CABLE_330K, C_330K_TA_MA, C_330K_USB_MA}, + {ADC_CABLE_620K, CABLE_620K, C_620K_TA_MA, C_620K_USB_MA}, + {ADC_CABLE_910K, CABLE_910K, C_910K_TA_MA, C_910K_USB_MA}, + {ADC_CABLE_NONE, CABLE_NONE, C_NONE_TA_MA, C_NONE_USB_MA}, +}; +#endif + +/* for board revision */ +static hw_rev_type lge_bd_rev = HW_REV_EVB1; + +static int __init board_revno_setup(char *rev_info) +{ + /* CAUTION: These strings are come from LK. */ + char *rev_str[] = {"evb1", "evb2", "rev_a", "rev_b", "rev_c", "rev_d", + "rev_e", "rev_f", "rev_g", "rev_h", "rev_10", "rev_11", "rev_12", + "reserved"}; + int i; + + printk(KERN_INFO "BOARD : LGE input %s \n", rev_info); + for (i=0; i< HW_REV_MAX; i++) { + if( !strncmp(rev_info, rev_str[i], 6)) { + lge_bd_rev = (hw_rev_type) i; + system_rev = lge_bd_rev; + break; + } + } + + printk(KERN_INFO "BOARD : LGE matched %s \n", rev_str[lge_bd_rev]); + return 1; +} +__setup("lge.rev=", board_revno_setup); + +hw_rev_type lge_get_board_revno(void) +{ + return lge_bd_rev; +} + +#ifdef CONFIG_LGE_PM +int lge_pm_get_cable_info(struct chg_cable_info *cable_info) +{ + char *type_str[] = {"NOT INIT", "MHL 1K", "U_28P7K", "28P7K", "56K", + "100K", "130K", "180K", "200K", "220K", "270K", "330K", "620K", "910K", + "OPEN"}; + + struct pm8xxx_adc_chan_result result; + struct chg_cable_info *info = cable_info; + struct chg_cable_info_table *table; + int table_size = ARRAY_SIZE(pm8921_acc_cable_type_data); + int acc_read_value = 0; + int i, rc; + int count = 5; + + if (!info) { + pr_err("lge_pm_get_cable_info: invalid info parameters\n"); + return -1; + } + + for (i = 0; i < count; i++) { + rc = pm8xxx_adc_mpp_config_read(PM8XXX_AMUX_MPP_12, + ADC_MPP_1_AMUX6, &result); + + if (rc < 0) { + if (rc == -ETIMEDOUT) { + /* reason: adc read timeout, assume it is open cable */ + info->cable_type = CABLE_NONE; + info->ta_ma = C_NONE_TA_MA; + info->usb_ma = C_NONE_USB_MA; + pr_err("[DEBUG] lge_pm_get_cable_info : adc read timeout \n"); + } else { + pr_err("lge_pm_get_cable_info: adc read error - %d\n", rc); + } + return rc; + } + + acc_read_value = (int)result.physical; + pr_info("%s: acc_read_value - %d\n", __func__, (int)result.physical); + mdelay(10); + } + + info->cable_type = NO_INIT_CABLE; + info->ta_ma = C_NO_INIT_TA_MA; + info->usb_ma = C_NO_INIT_USB_MA; + + /* assume: adc value must be existed in ascending order */ + for (i = 0; i < table_size; i++) { + table = &pm8921_acc_cable_type_data[i]; + + if (acc_read_value <= table->threshhold) { + info->cable_type = table->type; + info->ta_ma = table->ta_ma; + info->usb_ma = table->usb_ma; + break; + } + } + + pr_info("\n\n[PM]Cable detected: %d(%s)(%d, %d)\n\n", + acc_read_value, type_str[info->cable_type], + info->ta_ma, info->usb_ma); + + return 0; +} + +/* Belows are for using in interrupt context */ +static struct chg_cable_info lge_cable_info; + +acc_cable_type lge_pm_get_cable_type(void) +{ + return lge_cable_info.cable_type; +} + +unsigned lge_pm_get_ta_current(void) +{ + return lge_cable_info.ta_ma; +} + +unsigned lge_pm_get_usb_current(void) +{ + return lge_cable_info.usb_ma; +} + +/* This must be invoked in process context */ +void lge_pm_read_cable_info(void) +{ + lge_cable_info.cable_type = NO_INIT_CABLE; + lge_cable_info.ta_ma = C_NO_INIT_TA_MA; + lge_cable_info.usb_ma = C_NO_INIT_USB_MA; + + lge_pm_get_cable_info(&lge_cable_info); +} +#endif + +#ifdef CONFIG_LGE_PM_BATTERY_ID_CHECKER +int lge_battery_info = BATT_UNKNOWN; + +static int __init battery_information_setup(char *batt_info) +{ + if(!strcmp(batt_info, "ds2704_n")) + lge_battery_info = BATT_DS2704_N; + else if(!strcmp(batt_info, "ds2704_l")) + lge_battery_info = BATT_DS2704_L; + else if(!strcmp(batt_info, "isl6296_n")) + lge_battery_info = BATT_ISL6296_N; + else if(!strcmp(batt_info, "isl6296_l")) + lge_battery_info = BATT_ISL6296_L; + else + lge_battery_info = BATT_UNKNOWN; + + printk(KERN_INFO "Battery : %s %d\n", batt_info, lge_battery_info); + + return 1; +} +__setup("lge.batt_info=", battery_information_setup); +#endif + +#ifdef CONFIG_LGE_KCAL +int g_kcal_r = 255; +int g_kcal_g = 255; +int g_kcal_b = 255; +static int __init display_kcal_setup(char *kcal) +{ + char vaild_k = 0; + sscanf(kcal, "%d|%d|%d|%c", &g_kcal_r, &g_kcal_g, &g_kcal_b, &vaild_k ); + printk(KERN_INFO "kcal is %d|%d|%d|%c\n", + g_kcal_r, g_kcal_g, g_kcal_b, vaild_k); + + if(vaild_k != 'K') { + printk(KERN_INFO "kcal not calibrated yet : %d\n", vaild_k); + g_kcal_r = g_kcal_g = g_kcal_b = 255; + printk(KERN_INFO "set to default : %d\n", g_kcal_r); + } + return 1; +} +__setup("lge.kcal=", display_kcal_setup); +#endif + +/* get boot mode information from cmdline. + * If any boot mode is not specified, + * boot mode is normal type. + */ +static enum lge_boot_mode_type lge_boot_mode = LGE_BOOT_MODE_NORMAL; +int __init lge_boot_mode_init(char *s) +{ + if (!strcmp(s, "charger")) + lge_boot_mode = LGE_BOOT_MODE_CHARGER; + else if (!strcmp(s, "chargerlogo")) + lge_boot_mode = LGE_BOOT_MODE_CHARGERLOGO; + else if (!strcmp(s, "factory")) + lge_boot_mode = LGE_BOOT_MODE_FACTORY; + else if (!strcmp(s, "factory2")) + lge_boot_mode = LGE_BOOT_MODE_FACTORY2; + else if (!strcmp(s, "pifboot")) + lge_boot_mode = LGE_BOOT_MODE_PIFBOOT; + else if (!strcmp(s, "pifboot2")) + lge_boot_mode = LGE_BOOT_MODE_PIFBOOT2; + + return 1; +} +__setup("androidboot.mode=", lge_boot_mode_init); + +enum lge_boot_mode_type lge_get_boot_mode(void) +{ + return lge_boot_mode; +} + +int lge_get_factory_boot(void) +{ + int res; + + /* if boot mode is factory, + * cable must be factory cable. + */ + switch (lge_boot_mode) { + case LGE_BOOT_MODE_FACTORY: + case LGE_BOOT_MODE_FACTORY2: + case LGE_BOOT_MODE_PIFBOOT: + case LGE_BOOT_MODE_PIFBOOT2: + res = 1; + break; + default: + res = 0; + break; + } + + return res; +} + +#ifdef CONFIG_ANDROID_RAM_CONSOLE +static struct resource ram_console_resource[] = { + { + .name = "ram_console", + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +void __init lge_add_ramconsole_devices(void) +{ + struct resource* res = ram_console_resource; + struct membank* bank = &meminfo.bank[0]; + + res->start = PHYS_OFFSET + bank->size; + res->end = res->start + LGE_RAM_CONSOLE_SIZE - 1; + + printk(KERN_INFO "RAM CONSOLE START ADDR : %X\n", res->start); + printk(KERN_INFO "RAM CONSOLE END ADDR : %X\n", res->end); + + platform_device_register(&ram_console_device); +} +#endif // CONFIG_ANDROID_RAM_CONSOLE + +#ifdef CONFIG_LGE_HANDLE_PANIC +static struct resource crash_log_resource[] = { + { + .name = "crash_log", + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device panic_handler_device = { + .name = "panic-handler", + .num_resources = ARRAY_SIZE(crash_log_resource), + .resource = crash_log_resource, + .dev = { + .platform_data = NULL, + } +}; + +void __init lge_add_panic_handler_devices(void) +{ + struct resource* res = crash_log_resource; + struct membank* bank = &meminfo.bank[0]; + + res->start = bank->start + bank->size + LGE_RAM_CONSOLE_SIZE; + res->end = res->start + LGE_CRASH_LOG_SIZE - 1; + + printk(KERN_INFO "CRASH LOG START ADDR : %X\n", res->start); + printk(KERN_INFO "CRASH LOG END ADDR : %X\n", res->end); + + platform_device_register(&panic_handler_device); +} +#endif // CONFIG_LGE_HANDLE_PANIC + +#ifdef CONFIG_LGE_ECO_MODE +static struct platform_device lge_kernel_device = { + .name = "lge_kernel_driver", + .id = -1, +}; + +void __init lge_add_lge_kernel_devices(void) +{ + platform_device_register(&lge_kernel_device); +} +#endif + +#ifdef CONFIG_LGE_QFPROM_INTERFACE +static struct platform_device qfprom_device = { + .name = "lge-apq8064-qfprom", + .id = -1, +}; +void __init lge_add_qfprom_devices(void) +{ + platform_device_register(&qfprom_device); +} +#endif + +#ifdef CONFIG_LGE_BOOT_TIME_CHECK +static struct platform_device boot_time_device = { +.name = "boot_time", + .id = -1, + .dev = { + .platform_data = NULL, + }, +}; +void __init lge_add_boot_time_checker(void) +{ + platform_device_register(&boot_time_device); +} +#endif diff --git a/arch/arm/mach-msm/lge/mako/Kconfig b/arch/arm/mach-msm/lge/mako/Kconfig new file mode 100644 index 000000000000..9290b0cad5d2 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/Kconfig @@ -0,0 +1,10 @@ +config BOARD_HEADER_FILE + string "LGE board specific header file name" + default "" + +config MACH_APQ8064_MAKO + depends on ARCH_APQ8064 + select MACH_LGE + bool "MSM8064 MAKO" + help + Support for the LGE MAKO device. diff --git a/arch/arm/mach-msm/lge/mako/Makefile b/arch/arm/mach-msm/lge/mako/Makefile new file mode 100644 index 000000000000..1dc54f519c37 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/Makefile @@ -0,0 +1,12 @@ +obj-$(CONFIG_MACH_APQ8064_MAKO) += board-mako.o \ + board-mako-camera.o \ + board-mako-display.o \ + board-mako-gpiomux.o \ + board-mako-gpu.o \ + board-mako-input.o \ + board-mako-pmic.o \ + board-mako-regulator.o \ + board-mako-misc.o \ + board-mako-sound.o \ + board-mako-storage.o \ + board-mako-nfc.o diff --git a/arch/arm/mach-msm/lge/mako/board-mako-camera.c b/arch/arm/mach-msm/lge/mako/board-mako-camera.c new file mode 100644 index 000000000000..b81c2744bd4f --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-camera.c @@ -0,0 +1,628 @@ +/* Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "board-mako.h" + +#ifdef CONFIG_MSM_CAMERA +static struct gpiomux_setting cam_settings[] = { + { + .func = GPIOMUX_FUNC_GPIO, /*suspend*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + + { + .func = GPIOMUX_FUNC_1, /*active 1*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + }, + + { + .func = GPIOMUX_FUNC_GPIO, /*active 2*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + }, + + { + .func = GPIOMUX_FUNC_1, /*active 3*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + }, + + { + .func = GPIOMUX_FUNC_4, /*active 4*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + }, + + { + .func = GPIOMUX_FUNC_6, /*active 5*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_UP, + }, + + { + .func = GPIOMUX_FUNC_2, /*active 6*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_UP, + }, + + { + .func = GPIOMUX_FUNC_3, /*active 7*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_UP, + }, + + { + .func = GPIOMUX_FUNC_GPIO, /*i2c suspend*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_KEEPER, + }, + + { + .func = GPIOMUX_FUNC_9, /*active 9*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + }, + { + .func = GPIOMUX_FUNC_A, /*active 10*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + }, + { + .func = GPIOMUX_FUNC_6, /*active 11*/ + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + }, + { + .func = GPIOMUX_FUNC_4, /*active 12*/ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + }, + +}; + +static struct msm_gpiomux_config apq8064_cam_common_configs[] = { + { + .gpio = GPIO_CAM_FLASH_EN, /* 7 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[2], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, + { + .gpio = GPIO_CAM_MCLK0, /* 5 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[1], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, + +/* FIXME: for old HW (LGU Rev.A,B VZW Rev.A,B ATT Rev.A) */ +#if 1 + { + .gpio = GPIO_CAM_MCLK2, /* 2 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[4], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, +#else + { + .gpio = GPIO_CAM_MCLK1, /* 4 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[1], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, +#endif + { + .gpio = GPIO_CAM2_RST_N, /* 34 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[2], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, + { + .gpio = GPIO_CAM1_RST_N, /* 32 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[2], + [GPIOMUX_SUSPENDED] = &cam_settings[0], + }, + }, + { + .gpio = GPIO_CAM_I2C_SDA, /* 12 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[3], + [GPIOMUX_SUSPENDED] = &cam_settings[8], + }, + }, + { + .gpio = GPIO_CAM_I2C_SCL, /* 13 */ + .settings = { + [GPIOMUX_ACTIVE] = &cam_settings[3], + [GPIOMUX_SUSPENDED] = &cam_settings[8], + }, + }, +}; + +#if defined(CONFIG_IMX111) || defined(CONFIG_IMX091) +static struct msm_gpiomux_config apq8064_cam_2d_configs[] = { +}; + +static struct msm_bus_vectors cam_init_vectors[] = { + { + .src = MSM_BUS_MASTER_VFE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_VPE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_JPEG_ENC, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors cam_preview_vectors[] = { + { + .src = MSM_BUS_MASTER_VFE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 27648000, + .ib = 110592000, + }, + { + .src = MSM_BUS_MASTER_VPE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_JPEG_ENC, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors cam_video_vectors[] = { + { + .src = MSM_BUS_MASTER_VFE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 140451840, + .ib = 561807360, + }, + { + .src = MSM_BUS_MASTER_VPE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 206807040, + .ib = 488816640, + }, + { + .src = MSM_BUS_MASTER_JPEG_ENC, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors cam_snapshot_vectors[] = { + { + .src = MSM_BUS_MASTER_VFE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 274423680, + .ib = 1097694720, + }, + { + .src = MSM_BUS_MASTER_VPE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_JPEG_ENC, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 540000000, + .ib = 1350000000, + }, +}; + +static struct msm_bus_vectors cam_zsl_vectors[] = { + { + .src = MSM_BUS_MASTER_VFE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 302071680, + .ib = 1812430080, + }, + { + .src = MSM_BUS_MASTER_VPE, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_JPEG_ENC, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 540000000, + .ib = 2025000000, + }, +}; + +static struct msm_bus_paths cam_bus_client_config[] = { + { + ARRAY_SIZE(cam_init_vectors), + cam_init_vectors, + }, + { + ARRAY_SIZE(cam_preview_vectors), + cam_preview_vectors, + }, + { + ARRAY_SIZE(cam_video_vectors), + cam_video_vectors, + }, + { + ARRAY_SIZE(cam_snapshot_vectors), + cam_snapshot_vectors, + }, + { + ARRAY_SIZE(cam_zsl_vectors), + cam_zsl_vectors, + }, +}; + +static struct msm_bus_scale_pdata cam_bus_client_pdata = { + cam_bus_client_config, + ARRAY_SIZE(cam_bus_client_config), + .name = "msm_camera", +}; + +static struct msm_camera_device_platform_data msm_camera_csi_device_data[] = { + { + .csid_core = 0, + .is_csiphy = 1, + .is_csid = 1, + .is_ispif = 1, + .is_vpe = 1, + .cam_bus_scale_table = &cam_bus_client_pdata, + }, + { + .csid_core = 1, + .is_csiphy = 1, + .is_csid = 1, + .is_ispif = 1, + .is_vpe = 1, + .cam_bus_scale_table = &cam_bus_client_pdata, + }, +}; +static struct camera_vreg_t apq_8064_back_cam_vreg[] = { + {"cam1_vdig", REG_LDO, 1200000, 1200000, 105000}, + {"cam1_vio", REG_VS, 0, 0, 0}, + {"cam1_vana", REG_LDO, 2850000, 2850000, 85600}, +#if defined(CONFIG_IMX111) || defined(CONFIG_IMX091) + {"cam1_vaf", REG_LDO, 2800000, 2800000, 300000}, +#else + {"cam1_vaf", REG_LDO, 1800000, 1800000, 150000}, +#endif +}; +#endif + +#ifdef CONFIG_IMX119 +static struct camera_vreg_t apq_8064_front_cam_vreg[] = { + {"cam2_vio", REG_VS, 0, 0, 0}, + {"cam2_vana", REG_LDO, 2800000, 2850000, 85600}, + {"cam2_vdig", REG_LDO, 1200000, 1200000, 105000}, +}; +#endif + +#if defined(CONFIG_IMX111) || defined(CONFIG_IMX091) +static struct gpio apq8064_common_cam_gpio[] = { + {12, GPIOF_DIR_IN, "CAMIF_I2C_DATA"}, + {13, GPIOF_DIR_IN, "CAMIF_I2C_CLK"}, +}; + +static struct gpio apq8064_back_cam_gpio[] = { + {GPIO_CAM_MCLK0, GPIOF_DIR_IN, "CAMIF_MCLK"}, + {GPIO_CAM1_RST_N, GPIOF_DIR_OUT, "CAM_RESET"}, +}; + +static struct msm_gpio_set_tbl apq8064_back_cam_gpio_set_tbl[] = { + {GPIO_CAM1_RST_N, GPIOF_OUT_INIT_LOW, 10000}, + {GPIO_CAM1_RST_N, GPIOF_OUT_INIT_HIGH, 10000}, +}; + +static struct msm_camera_gpio_conf apq8064_back_cam_gpio_conf = { + .cam_gpiomux_conf_tbl = apq8064_cam_2d_configs, + .cam_gpiomux_conf_tbl_size = ARRAY_SIZE(apq8064_cam_2d_configs), + .cam_gpio_common_tbl = apq8064_common_cam_gpio, + .cam_gpio_common_tbl_size = ARRAY_SIZE(apq8064_common_cam_gpio), + .cam_gpio_req_tbl = apq8064_back_cam_gpio, + .cam_gpio_req_tbl_size = ARRAY_SIZE(apq8064_back_cam_gpio), + .cam_gpio_set_tbl = apq8064_back_cam_gpio_set_tbl, + .cam_gpio_set_tbl_size = ARRAY_SIZE(apq8064_back_cam_gpio_set_tbl), +}; +#endif + +#ifdef CONFIG_IMX119 +static struct gpio apq8064_front_cam_gpio[] = { +/* FIXME: for old HW (LGU Rev.A,B VZW Rev.A,B ATT Rev.A) */ +#if 1 + {GPIO_CAM_MCLK2, GPIOF_DIR_IN, "CAMIF_MCLK"}, +#else + {GPIO_CAM_MCLK1, GPIOF_DIR_IN, "CAMIF_MCLK"}, +#endif + {GPIO_CAM2_RST_N, GPIOF_DIR_OUT, "CAM_RESET"}, +}; + +static struct msm_gpio_set_tbl apq8064_front_cam_gpio_set_tbl[] = { + {GPIO_CAM2_RST_N, GPIOF_OUT_INIT_LOW, 10000}, + {GPIO_CAM2_RST_N, GPIOF_OUT_INIT_HIGH, 10000}, +}; + +static struct msm_camera_gpio_conf apq8064_front_cam_gpio_conf = { + .cam_gpiomux_conf_tbl = apq8064_cam_2d_configs, + .cam_gpiomux_conf_tbl_size = ARRAY_SIZE(apq8064_cam_2d_configs), + .cam_gpio_common_tbl = apq8064_common_cam_gpio, + .cam_gpio_common_tbl_size = ARRAY_SIZE(apq8064_common_cam_gpio), + .cam_gpio_req_tbl = apq8064_front_cam_gpio, + .cam_gpio_req_tbl_size = ARRAY_SIZE(apq8064_front_cam_gpio), + .cam_gpio_set_tbl = apq8064_front_cam_gpio_set_tbl, + .cam_gpio_set_tbl_size = ARRAY_SIZE(apq8064_front_cam_gpio_set_tbl), +}; +#endif + +#if defined (CONFIG_IMX091) || defined (CONFIG_IMX111) +static struct msm_camera_i2c_conf apq8064_back_cam_i2c_conf = { + .use_i2c_mux = 1, + .mux_dev = &msm8960_device_i2c_mux_gsbi4, + .i2c_mux_mode = MODE_L, +}; +#endif +#ifdef CONFIG_IMX111_ACT +static struct i2c_board_info msm_act_main_cam_i2c_info = { + I2C_BOARD_INFO("msm_actuator", I2C_SLAVE_ADDR_IMX111_ACT), +}; + +static struct msm_actuator_info msm_act_main_cam_0_info = { + .board_info = &msm_act_main_cam_i2c_info, + .cam_name = MSM_ACTUATOR_MAIN_CAM_1, + .bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID, + .vcm_pwd = 0, + .vcm_enable = 0, +}; +#endif + +#ifdef CONFIG_IMX111 +static struct msm_camera_sensor_flash_data flash_imx111 = { + .flash_type = MSM_CAMERA_FLASH_LED, +}; + +static struct msm_camera_csi_lane_params imx111_csi_lane_params = { + .csi_lane_assign = 0xE4, + .csi_lane_mask = 0xF, +}; + +static struct msm_camera_sensor_platform_info sensor_board_info_imx111 = { + .mount_angle = 90, + .cam_vreg = apq_8064_back_cam_vreg, + .num_vreg = ARRAY_SIZE(apq_8064_back_cam_vreg), + .gpio_conf = &apq8064_back_cam_gpio_conf, + .i2c_conf = &apq8064_back_cam_i2c_conf, + .csi_lane_params = &imx111_csi_lane_params, +}; + +static struct msm_camera_sensor_info msm_camera_sensor_imx111_data = { + .sensor_name = "imx111", + .pdata = &msm_camera_csi_device_data[0], + .flash_data = &flash_imx111, + .sensor_platform_info = &sensor_board_info_imx111, + .csi_if = 1, + .camera_type = BACK_CAMERA_2D, + .sensor_type = BAYER_SENSOR, +#ifdef CONFIG_IMX111_ACT + .actuator_info = &msm_act_main_cam_0_info, + +#endif +}; +#endif + +#ifdef CONFIG_IMX091_ACT +static struct i2c_board_info msm_act_main_cam_i2c_info = { + I2C_BOARD_INFO("msm_actuator", I2C_SLAVE_ADDR_IMX091_ACT), /* 0x18 */ +}; + +static struct msm_actuator_info msm_act_main_cam_0_info = { + .board_info = &msm_act_main_cam_i2c_info, + .cam_name = MSM_ACTUATOR_MAIN_CAM_1, + .bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID, + .vcm_pwd = 0, + .vcm_enable = 0, +}; +#endif +#ifdef CONFIG_IMX091 +static struct msm_camera_sensor_flash_data flash_imx091 = { + .flash_type = MSM_CAMERA_FLASH_LED, +}; + +static struct msm_camera_csi_lane_params imx091_csi_lane_params = { + .csi_lane_assign = 0xE4, + .csi_lane_mask = 0xF, +}; + +static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = { + .mount_angle = 90, + .cam_vreg = apq_8064_back_cam_vreg, + .num_vreg = ARRAY_SIZE(apq_8064_back_cam_vreg), + .gpio_conf = &apq8064_back_cam_gpio_conf, + .i2c_conf = &apq8064_back_cam_i2c_conf, + .csi_lane_params = &imx091_csi_lane_params, +}; + +static struct i2c_board_info imx091_eeprom_i2c_info = { + I2C_BOARD_INFO("imx091_eeprom", 0x21), +}; + +static struct msm_eeprom_info imx091_eeprom_info = { + .board_info = &imx091_eeprom_i2c_info, + .bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID, +}; + +static struct msm_camera_sensor_info msm_camera_sensor_imx091_data = { + .sensor_name = "imx091", + .pdata = &msm_camera_csi_device_data[0], + .flash_data = &flash_imx091, + .sensor_platform_info = &sensor_board_info_imx091, + .csi_if = 1, + .camera_type = BACK_CAMERA_2D, + .sensor_type = BAYER_SENSOR, +#ifdef CONFIG_IMX091_ACT + .actuator_info = &msm_act_main_cam_0_info, +#endif + .eeprom_info = &imx091_eeprom_info, +}; +#endif + +#ifdef CONFIG_IMX119 +static struct msm_camera_i2c_conf apq8064_front_cam_i2c_conf = { + .use_i2c_mux = 1, + .mux_dev = &msm8960_device_i2c_mux_gsbi4, + .i2c_mux_mode = MODE_L, +}; +#endif + + +#ifdef CONFIG_IMX119 +static struct msm_camera_sensor_flash_data flash_imx119 = { + .flash_type = MSM_CAMERA_FLASH_NONE, +}; + +static struct msm_camera_csi_lane_params imx119_csi_lane_params = { + .csi_lane_assign = 0xE4, + .csi_lane_mask = 0x1, +}; + +static struct msm_camera_sensor_platform_info sensor_board_info_imx119 = { + .mount_angle = 270, + .cam_vreg = apq_8064_front_cam_vreg, + .num_vreg = ARRAY_SIZE(apq_8064_front_cam_vreg), + .gpio_conf = &apq8064_front_cam_gpio_conf, + .i2c_conf = &apq8064_front_cam_i2c_conf, + .csi_lane_params = &imx119_csi_lane_params, +}; + +static struct msm_camera_sensor_info msm_camera_sensor_imx119_data = { + .sensor_name = "imx119", + .pdata = &msm_camera_csi_device_data[1], + .flash_data = &flash_imx119, + .sensor_platform_info = &sensor_board_info_imx119, + .csi_if = 1, + .camera_type = FRONT_CAMERA_2D, + .sensor_type = BAYER_SENSOR, +}; +#endif + +/* Enabling flash LED for camera */ +struct led_flash_platform_data { + unsigned gpio_en; + unsigned scl_gpio; + unsigned sda_gpio; +}; + +static struct led_flash_platform_data lm3559_flash_pdata[] = { + { + .scl_gpio = GPIO_CAM_FLASH_I2C_SCL, + .sda_gpio = GPIO_CAM_FLASH_I2C_SDA, + .gpio_en = GPIO_CAM_FLASH_EN, + } +}; + +static struct platform_device msm_camera_server = { + .name = "msm_cam_server", + .id = 0, +}; + +void __init apq8064_init_cam(void) +{ + msm_gpiomux_install(apq8064_cam_common_configs, + ARRAY_SIZE(apq8064_cam_common_configs)); + + platform_device_register(&msm_camera_server); + platform_device_register(&msm8960_device_i2c_mux_gsbi4); + platform_device_register(&msm8960_device_csiphy0); + platform_device_register(&msm8960_device_csiphy1); + platform_device_register(&msm8960_device_csid0); + platform_device_register(&msm8960_device_csid1); + platform_device_register(&msm8960_device_ispif); + platform_device_register(&msm8960_device_vfe); + platform_device_register(&msm8960_device_vpe); +} + +#ifdef CONFIG_I2C +static struct i2c_board_info apq8064_camera_i2c_boardinfo[] = { +#ifdef CONFIG_IMX111 + { + I2C_BOARD_INFO("imx111", I2C_SLAVE_ADDR_IMX111), /* 0x0D */ + .platform_data = &msm_camera_sensor_imx111_data, + }, +#endif +#ifdef CONFIG_IMX091 + { + I2C_BOARD_INFO("imx091", I2C_SLAVE_ADDR_IMX091), /* 0x0D */ + .platform_data = &msm_camera_sensor_imx091_data, + }, +#endif +#ifdef CONFIG_IMX119 + { + I2C_BOARD_INFO("imx119", I2C_SLAVE_ADDR_IMX119), /* 0x6E */ + .platform_data = &msm_camera_sensor_imx119_data, + }, +#endif +}; + +/* Enabling flash LED for camera */ +static struct i2c_board_info apq8064_lge_camera_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("lm3559", I2C_SLAVE_ADDR_FLASH), + .platform_data = &lm3559_flash_pdata, + }, +}; + +struct msm_camera_board_info apq8064_camera_board_info = { + .board_info = apq8064_camera_i2c_boardinfo, + .num_i2c_board_info = ARRAY_SIZE(apq8064_camera_i2c_boardinfo), +}; + +/* Enabling flash LED for camera */ +struct msm_camera_board_info apq8064_lge_camera_board_info = { + .board_info = apq8064_lge_camera_i2c_boardinfo, + .num_i2c_board_info = ARRAY_SIZE(apq8064_lge_camera_i2c_boardinfo), +}; + +#endif +#endif diff --git a/arch/arm/mach-msm/lge/mako/board-mako-display.c b/arch/arm/mach-msm/lge/mako/board-mako-display.c new file mode 100644 index 000000000000..b1d71af71c9f --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-display.c @@ -0,0 +1,1354 @@ +/* Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "board-mako.h" + +#include "../../../../drivers/video/msm/msm_fb.h" +#include "../../../../drivers/video/msm/msm_fb_def.h" +#include "../../../../drivers/video/msm/mipi_dsi.h" + +#include + +#include +#include + +#ifndef LGE_DSDR_SUPPORT +#define LGE_DSDR_SUPPORT +#endif + +/* FIXME: temporarily undef to build */ +#undef CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT + +#ifdef CONFIG_LGE_KCAL +#ifdef CONFIG_LGE_QC_LCDC_LUT +extern int set_qlut_kcal_values(int kcal_r, int kcal_g, int kcal_b); +extern int refresh_qlut_display(void); +#else +#error only kcal by Qucalcomm LUT is supported now!!! +#endif +#endif + +#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER +/* prim = 1366 x 768 x 3(bpp) x 3(pages) */ +#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) +#define MSM_FB_PRIM_BUF_SIZE roundup(768 * 1280 * 4 * 3, 0x10000) +#elif defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) +#define MSM_FB_PRIM_BUF_SIZE roundup(736 * 1280 * 4 * 3, 0x10000) +#else +#define MSM_FB_PRIM_BUF_SIZE roundup(1920 * 1088 * 4 * 3, 0x10000) +#endif +#else +/* prim = 1366 x 768 x 3(bpp) x 2(pages) */ +#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) +#define MSM_FB_PRIM_BUF_SIZE roundup(768 * 1280 * 4 * 2, 0x10000) +#elif definded(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) +#define MSM_FB_PRIM_BUF_SIZE roundup(736 * 1280 * 4 * 2, 0x10000) +#else +#define MSM_FB_PRIM_BUF_SIZE roundup(1920 * 1088 * 4 * 2, 0x10000) +#endif +#endif /*CONFIG_FB_MSM_TRIPLE_BUFFER */ + +#ifdef LGE_DSDR_SUPPORT +#define MSM_FB_EXT_BUF_SIZE \ + (roundup((1920 * 1088 * 4), 4096) * 3) /* 4 bpp x 3 page */ +#else /* LGE_DSDR_SUPPORT */ +#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL +#define MSM_FB_EXT_BUF_SIZE \ + (roundup((1920 * 1088 * 2), 4096) * 1) /* 2 bpp x 1 page */ +#elif defined(CONFIG_FB_MSM_TVOUT) +#define MSM_FB_EXT_BUF_SIZE \ + (roundup((720 * 576 * 2), 4096) * 2) /* 2 bpp x 2 pages */ +#else +#define MSM_FB_EXT_BUF_SIZE 0 +#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */ +#endif /* LGE_DSDR_SUPPORT */ + +#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL +#define MSM_FB_WFD_BUF_SIZE \ + (roundup((1280 * 736 * 2), 4096) * 3) /* 2 bpp x 3 page */ +#else +#define MSM_FB_WFD_BUF_SIZE 0 +#endif + +#define MSM_FB_SIZE \ + roundup(MSM_FB_PRIM_BUF_SIZE + \ + MSM_FB_EXT_BUF_SIZE + MSM_FB_WFD_BUF_SIZE, 4096) + +#ifdef CONFIG_FB_MSM_OVERLAY0_WRITEBACK + #if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) + #define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((768 * 1280 * 3 * 2), 4096) + #elif defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + #define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((736 * 1280 * 3 * 2), 4096) + #else + #define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0) + #endif +#else +#define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0) +#endif /* CONFIG_FB_MSM_OVERLAY0_WRITEBACK */ + +#ifdef CONFIG_FB_MSM_OVERLAY1_WRITEBACK +#define MSM_FB_OVERLAY1_WRITEBACK_SIZE roundup((1920 * 1088 * 3 * 2), 4096) +#else +#define MSM_FB_OVERLAY1_WRITEBACK_SIZE (0) +#endif /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */ + +#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) +#define LGIT_IEF +#endif +static struct resource msm_fb_resources[] = { + { + .flags = IORESOURCE_DMA, + } +}; + +#define LVDS_CHIMEI_PANEL_NAME "lvds_chimei_wxga" +#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME "mipi_video_toshiba_wsvga" +#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME "mipi_video_chimei_wxga" +#define HDMI_PANEL_NAME "hdmi_msm" +#define TVOUT_PANEL_NAME "tvout_msm" + +#ifndef CONFIG_MACH_LGE +#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY +static unsigned char hdmi_is_primary = 1; +#else +static unsigned char hdmi_is_primary; +#endif + +unsigned char apq8064_hdmi_as_primary_selected(void) +{ + return hdmi_is_primary; +} + +static void set_mdp_clocks_for_wuxga(void); +#endif + +static int msm_fb_detect_panel(const char *name) +{ + return 0; +} + +static struct msm_fb_platform_data msm_fb_pdata = { + .detect_client = msm_fb_detect_panel, +}; + +static struct platform_device msm_fb_device = { + .name = "msm_fb", + .id = 0, + .num_resources = ARRAY_SIZE(msm_fb_resources), + .resource = msm_fb_resources, + .dev.platform_data = &msm_fb_pdata, +}; + +void __init apq8064_allocate_fb_region(void) +{ + void *addr; + unsigned long size; + + size = MSM_FB_SIZE; + addr = alloc_bootmem_align(size, 0x1000); + msm_fb_resources[0].start = __pa(addr); + msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1; + pr_info("allocating %lu bytes at %p (%lx physical) for fb\n", + size, addr, __pa(addr)); +} + +#define MDP_VSYNC_GPIO 0 + +static struct msm_bus_vectors mdp_init_vectors[] = { + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors mdp_ui_vectors[] = { + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 216000000 * 2, + .ib = 270000000 * 2, + }, +}; + +static struct msm_bus_vectors mdp_vga_vectors[] = { + /* VGA and less video */ + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 216000000 * 2, + .ib = 270000000 * 2, + }, +}; + +static struct msm_bus_vectors mdp_720p_vectors[] = { + /* 720p and less video */ + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 230400000 * 2, + .ib = 288000000 * 2, + }, +}; + +static struct msm_bus_vectors mdp_1080p_vectors[] = { + /* 1080p and less video */ + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 334080000 * 2, + .ib = 417600000 * 2, + }, +}; + +static struct msm_bus_paths mdp_bus_scale_usecases[] = { + { + ARRAY_SIZE(mdp_init_vectors), + mdp_init_vectors, + }, + { + ARRAY_SIZE(mdp_ui_vectors), + mdp_ui_vectors, + }, + { + ARRAY_SIZE(mdp_ui_vectors), + mdp_ui_vectors, + }, + { + ARRAY_SIZE(mdp_vga_vectors), + mdp_vga_vectors, + }, + { + ARRAY_SIZE(mdp_720p_vectors), + mdp_720p_vectors, + }, + { + ARRAY_SIZE(mdp_1080p_vectors), + mdp_1080p_vectors, + }, +}; + +static struct msm_bus_scale_pdata mdp_bus_scale_pdata = { + mdp_bus_scale_usecases, + ARRAY_SIZE(mdp_bus_scale_usecases), + .name = "mdp", +}; + +static int mdp_core_clk_rate_table[] = { + 85330000, + 128000000, + 160000000, + 200000000, +}; + +static struct msm_panel_common_pdata mdp_pdata = { + .gpio = MDP_VSYNC_GPIO, + .mdp_core_clk_rate = 85330000, + .mdp_core_clk_table = mdp_core_clk_rate_table, + .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table), + .mdp_bus_scale_table = &mdp_bus_scale_pdata, + .mdp_rev = MDP_REV_44, +#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION + .mem_hid = BIT(ION_CP_MM_HEAP_ID), +#else + .mem_hid = MEMTYPE_EBI1, +#endif + /* for early backlight on for APQ8064 */ + .cont_splash_enabled = 0x01, +}; + +void __init apq8064_mdp_writeback(struct memtype_reserve* reserve_table) +{ + mdp_pdata.ov0_wb_size = MSM_FB_OVERLAY0_WRITEBACK_SIZE; + mdp_pdata.ov1_wb_size = MSM_FB_OVERLAY1_WRITEBACK_SIZE; +#if defined(CONFIG_ANDROID_PMEM) && !defined(CONFIG_MSM_MULTIMEDIA_USE_ION) + reserve_table[mdp_pdata.mem_hid].size += + mdp_pdata.ov0_wb_size; + reserve_table[mdp_pdata.mem_hid].size += + mdp_pdata.ov1_wb_size; +#endif +} + +#ifdef CONFIG_LGE_KCAL +extern int set_kcal_values(int kcal_r, int kcal_g, int kcal_b); +extern int refresh_kcal_display(void); +extern int get_kcal_values(int *kcal_r, int *kcal_g, int *kcal_b); + +static struct kcal_platform_data kcal_pdata = { + .set_values = set_kcal_values, + .get_values = get_kcal_values, + .refresh_display = refresh_kcal_display +}; + +static struct platform_device kcal_platrom_device = { + .name = "kcal_ctrl", + .dev = { + .platform_data = &kcal_pdata, + } +}; +#endif + +static struct resource hdmi_msm_resources[] = { + { + .name = "hdmi_msm_qfprom_addr", + .start = 0x00700000, + .end = 0x007060FF, + .flags = IORESOURCE_MEM, + }, + { + .name = "hdmi_msm_hdmi_addr", + .start = 0x04A00000, + .end = 0x04A00FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "hdmi_msm_irq", + .start = HDMI_IRQ, + .end = HDMI_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static int hdmi_enable_5v(int on); +static int hdmi_core_power(int on, int show); +static int hdmi_cec_power(int on); + +static struct msm_hdmi_platform_data hdmi_msm_data = { + .irq = HDMI_IRQ, + .enable_5v = hdmi_enable_5v, + .core_power = hdmi_core_power, + .cec_power = hdmi_cec_power, +}; + +static struct platform_device hdmi_msm_device = { + .name = "hdmi_msm", + .id = 0, + .num_resources = ARRAY_SIZE(hdmi_msm_resources), + .resource = hdmi_msm_resources, + .dev.platform_data = &hdmi_msm_data, +}; + +#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL +static struct platform_device wfd_panel_device = { + .name = "wfd_panel", + .id = 0, + .dev.platform_data = NULL, +}; + +static struct platform_device wfd_device = { + .name = "msm_wfd", + .id = -1, +}; +#endif + +/* HDMI related GPIOs */ +#define HDMI_CEC_VAR_GPIO 69 +#define HDMI_DDC_CLK_GPIO 70 +#define HDMI_DDC_DATA_GPIO 71 +#define HDMI_HPD_GPIO 72 + +static bool dsi_power_on; +static int mipi_dsi_panel_power(int on) +{ + static struct regulator *reg_l8, *reg_l2, *reg_lvs6; +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + static int gpio20; // LCD RST GPIO for rev.B +#endif + static int gpio42; + int rc; + +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + // LCD RST GPIO for rev.B + struct pm_gpio gpio20_param = { + .direction = PM_GPIO_DIR_OUT, + .output_buffer = PM_GPIO_OUT_BUF_CMOS, + .output_value = 0, + .pull = PM_GPIO_PULL_NO, + .vin_sel = 2, + .out_strength = PM_GPIO_STRENGTH_HIGH, + .function = PM_GPIO_FUNC_PAIRED, + .inv_int_pol = 0, + .disable_pin = 0, + }; +#endif + + struct pm_gpio gpio42_param = { + .direction = PM_GPIO_DIR_OUT, + .output_buffer = PM_GPIO_OUT_BUF_CMOS, + .output_value = 0, + .pull = PM_GPIO_PULL_NO, + .vin_sel = 2, + .out_strength = PM_GPIO_STRENGTH_HIGH, + .function = PM_GPIO_FUNC_PAIRED, + .inv_int_pol = 0, + .disable_pin = 0, + }; + printk(KERN_INFO"%s: mipi lcd function started status = %d \n", __func__, on); + + pr_debug("%s: state : %d\n", __func__, on); + + if (!dsi_power_on) { + +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + // LCD RST GPIO for rev.B + if (lge_get_board_revno() == HW_REV_B) { + gpio20 = PM8921_GPIO_PM_TO_SYS(20); + + rc = gpio_request(gpio20, "disp_rst_n"); + if (rc) { + pr_err("request gpio 20 failed, rc=%d\n", rc); + return -ENODEV; + } + } + else { + gpio42 = PM8921_GPIO_PM_TO_SYS(42); + + rc = gpio_request(gpio42, "disp_rst_n"); + if (rc) { + pr_err("request gpio 42 failed, rc=%d\n", rc); + return -ENODEV; + } + } +#else + gpio42 = PM8921_GPIO_PM_TO_SYS(42); + + rc = gpio_request(gpio42, "disp_rst_n"); + if (rc) { + pr_err("request gpio 42 failed, rc=%d\n", rc); + return -ENODEV; + } +#endif + + reg_l8 = regulator_get(&msm_mipi_dsi1_device.dev, "dsi_vci"); + if (IS_ERR(reg_l8)) { + pr_err("could not get 8921_l8, rc = %ld\n", + PTR_ERR(reg_l8)); + return -ENODEV; + } + + reg_lvs6 = regulator_get(&msm_mipi_dsi1_device.dev, "dsi_iovcc"); + if (IS_ERR(reg_lvs6)) { + pr_err("could not get 8921_lvs6, rc = %ld\n", + PTR_ERR(reg_lvs6)); + return -ENODEV; + } + + reg_l2 = regulator_get(&msm_mipi_dsi1_device.dev, "dsi_vdda"); + if (IS_ERR(reg_l2)) { + pr_err("could not get 8921_l2, rc = %ld\n", + PTR_ERR(reg_l2)); + return -ENODEV; + } + + rc = regulator_set_voltage(reg_l8, 3000000, 3000000); + if (rc) { + pr_err("set_voltage l8 failed, rc=%d\n", rc); + return -EINVAL; + } + + rc = regulator_set_voltage(reg_l2, 1200000, 1200000); + if (rc) { + pr_err("set_voltage l2 failed, rc=%d\n", rc); + return -EINVAL; + } + + dsi_power_on = true; + } + if (on) { + + rc = regulator_set_optimum_mode(reg_l8, 100000); + if (rc < 0) { + pr_err("set_optimum_mode l8 failed, rc=%d\n", rc); + return -EINVAL; + } + + rc = regulator_set_optimum_mode(reg_l2, 100000); + if (rc < 0) { + pr_err("set_optimum_mode l2 failed, rc=%d\n", rc); + return -EINVAL; + } + +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + rc = regulator_enable(reg_lvs6); // IOVCC + if (rc) { + pr_err("enable lvs6 failed, rc=%d\n", rc); + return -ENODEV; + } + + udelay(100); + + rc = regulator_enable(reg_l8); // dsi_vci + if (rc) { + pr_err("enable l8 failed, rc=%d\n", rc); + return -ENODEV; + } + + udelay(100); + + rc = regulator_enable(reg_l2); // DSI + if (rc) { + pr_err("enable l2 failed, rc=%d\n", rc); + return -ENODEV; + } +#elif defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) + rc = regulator_enable(reg_l8); // dsi_vci + if (rc) { + pr_err("enable l8 failed, rc=%d\n", rc); + return -ENODEV; + } + + udelay(100); + + rc = regulator_enable(reg_lvs6); // IOVCC + if (rc) { + pr_err("enable lvs6 failed, rc=%d\n", rc); + return -ENODEV; + } + + udelay(100); +#endif + + rc = regulator_enable(reg_l2); // DSI + if (rc) { + pr_err("enable l2 failed, rc=%d\n", rc); + return -ENODEV; + } + + printk(KERN_INFO " %s : reset start.", __func__); +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + // LCD RESET HIGH for rev.B + if (lge_get_board_revno() == HW_REV_B) { + mdelay(2); + gpio20_param.output_value = 1; + rc = pm8xxx_gpio_config(gpio20,&gpio20_param); + if (rc) { + pr_err("gpio_config 20 failed (3), rc=%d\n", rc); + return -EINVAL; + } + } + else { + mdelay(2); + gpio42_param.output_value = 1; + rc = pm8xxx_gpio_config(gpio42,&gpio42_param); + if (rc) { + pr_err("gpio_config 42 failed (3), rc=%d\n", rc); + return -EINVAL; + } + mdelay(11); + } +#else + /* LCD RESET HIGH */ + mdelay(2); + gpio42_param.output_value = 1; + rc = pm8xxx_gpio_config(gpio42,&gpio42_param); + if (rc) { + pr_err("gpio_config 42 failed (3), rc=%d\n", rc); + return -EINVAL; + } + mdelay(11); +#endif + + } else { +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + /* LCD RESET LOW for rev.B */ + if (lge_get_board_revno() == HW_REV_B) { + gpio20_param.output_value = 0; + rc = pm8xxx_gpio_config(gpio20,&gpio20_param); + if (rc) { + pr_err("gpio_config 20 failed, rc=%d\n", rc); + return -ENODEV; + } + } + else { + /* LCD RESET LOW */ + gpio42_param.output_value = 0; + rc = pm8xxx_gpio_config(gpio42,&gpio42_param); + if (rc) { + pr_err("gpio_config 42 failed, rc=%d\n", rc); + return -ENODEV; + } + udelay(100); + } +#else + /* LCD RESET LOW */ + gpio42_param.output_value = 0; + rc = pm8xxx_gpio_config(gpio42,&gpio42_param); + if (rc) { + pr_err("gpio_config 42 failed, rc=%d\n", rc); + return -ENODEV; + } + udelay(100); +#endif + +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + rc = regulator_disable(reg_l8); //VCI + if (rc) { + pr_err("disable reg_l8 failed, rc=%d\n", rc); + return -ENODEV; + } + + rc = regulator_disable(reg_lvs6); // IOVCC + if (rc) { + pr_err("disable lvs6 failed, rc=%d\n", rc); + return -ENODEV; + } +#elif defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) + rc = regulator_disable(reg_lvs6); // IOVCC + if (rc) { + pr_err("disable lvs6 failed, rc=%d\n", rc); + return -ENODEV; + } + udelay(100); + + rc = regulator_disable(reg_l8); //VCI + if (rc) { + pr_err("disable reg_l8 failed, rc=%d\n", rc); + return -ENODEV; + } + udelay(100); +#endif + rc = regulator_disable(reg_l2); //DSI + if (rc) { + pr_err("disable reg_l2 failed, rc=%d\n", rc); + return -ENODEV; + } + + rc = regulator_set_optimum_mode(reg_l8, 100); + if (rc < 0) { + pr_err("set_optimum_mode l8 failed, rc=%d\n", rc); + return -EINVAL; + } + + rc = regulator_set_optimum_mode(reg_l2, 100); + if (rc < 0) { + pr_err("set_optimum_mode l2 failed, rc=%d\n", rc); + return -EINVAL; + } + } + + return 0; +} + +static char mipi_dsi_splash_is_enabled(void) +{ + return mdp_pdata.cont_splash_enabled; +} + +static struct mipi_dsi_platform_data mipi_dsi_pdata = { + .dsi_power_save = mipi_dsi_panel_power, + .splash_is_enabled = mipi_dsi_splash_is_enabled, +}; + +static struct msm_bus_vectors dtv_bus_init_vectors[] = { + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors dtv_bus_def_vectors[] = { + { + .src = MSM_BUS_MASTER_MDP_PORT0, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 566092800 * 2, + .ib = 707616000 * 2, + }, +}; + +static struct msm_bus_paths dtv_bus_scale_usecases[] = { + { + ARRAY_SIZE(dtv_bus_init_vectors), + dtv_bus_init_vectors, + }, + { + ARRAY_SIZE(dtv_bus_def_vectors), + dtv_bus_def_vectors, + }, +}; +static struct msm_bus_scale_pdata dtv_bus_scale_pdata = { + dtv_bus_scale_usecases, + ARRAY_SIZE(dtv_bus_scale_usecases), + .name = "dtv", +}; + +static struct lcdc_platform_data dtv_pdata = { + .bus_scale_table = &dtv_bus_scale_pdata, +}; + +static int hdmi_enable_5v(int on) +{ + return 0; +} + +static int hdmi_core_power(int on, int show) +{ + static struct regulator *reg_8921_lvs7; + static int prev_on; + int rc; + + if (on == prev_on) + return 0; + + if (!reg_8921_lvs7) { + reg_8921_lvs7 = regulator_get(&hdmi_msm_device.dev, + "hdmi_vdda"); + if (IS_ERR(reg_8921_lvs7)) { + pr_err("could not get reg_8921_lvs7, rc = %ld\n", + PTR_ERR(reg_8921_lvs7)); + reg_8921_lvs7 = NULL; + return -ENODEV; + } + } + + if (on) { + rc = regulator_enable(reg_8921_lvs7); + if (rc) { + pr_err("'%s' regulator enable failed, rc=%d\n", + "hdmi_vdda", rc); + return rc; + } + + rc = gpio_request(HDMI_DDC_CLK_GPIO, "HDMI_DDC_CLK"); + if (rc) { + pr_err("'%s'(%d) gpio_request failed, rc=%d\n", + "HDMI_DDC_CLK", HDMI_DDC_CLK_GPIO, rc); + goto error1; + } + rc = gpio_request(HDMI_DDC_DATA_GPIO, "HDMI_DDC_DATA"); + if (rc) { + pr_err("'%s'(%d) gpio_request failed, rc=%d\n", + "HDMI_DDC_DATA", HDMI_DDC_DATA_GPIO, rc); + goto error2; + } + rc = gpio_request(HDMI_HPD_GPIO, "HDMI_HPD"); + if (rc) { + pr_err("'%s'(%d) gpio_request failed, rc=%d\n", + "HDMI_HPD", HDMI_HPD_GPIO, rc); + goto error3; + } + + pr_debug("%s(on): success\n", __func__); + + } else { + gpio_free(HDMI_DDC_CLK_GPIO); + gpio_free(HDMI_DDC_DATA_GPIO); + gpio_free(HDMI_HPD_GPIO); + + rc = regulator_disable(reg_8921_lvs7); + if (rc) { + pr_err("disable reg_8921_l23 failed, rc=%d\n", rc); + return -ENODEV; + } + pr_debug("%s(off): success\n", __func__); + } + + prev_on = on; + + return 0; + +error3: + gpio_free(HDMI_DDC_DATA_GPIO); +error2: + gpio_free(HDMI_DDC_CLK_GPIO); +error1: + regulator_disable(reg_8921_lvs7); + return rc; +} + +static int hdmi_cec_power(int on) +{ + return 0; +} + +#if defined (CONFIG_LGE_BACKLIGHT_LM3530) +extern void lm3530_lcd_backlight_set_level( int level); +#elif defined (CONFIG_LGE_BACKLIGHT_LM3533) +extern void lm3533_lcd_backlight_set_level( int level); +#endif + +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) +static int mipi_hitachi_backlight_level(int level, int max, int min) +{ + lm3533_lcd_backlight_set_level(level); + return 0; +} + +/* HITACHI 4.67" HD panel */ +static char set_address_mode[2] = {0x36, 0x00}; +static char set_pixel_format[2] = {0x3A, 0x70}; + +static char exit_sleep[2] = {0x11, 0x00}; +static char display_on[2] = {0x29, 0x00}; +static char enter_sleep[2] = {0x10, 0x00}; +static char display_off[2] = {0x28, 0x00}; + +static char macp_off[2] = {0xB0, 0x04}; +static char macp_on[2] = {0xB0, 0x03}; + +#if defined(CONFIG_LGE_BACKLIGHT_CABC) +#define CABC_POWERON_OFFSET 4 /* offset from lcd display on cmds */ + +#define CABC_OFF 0 +#define CABC_ON 1 + +#define CABC_10 1 +#define CABC_20 2 +#define CABC_30 3 +#define CABC_40 4 +#define CABC_50 5 + +#define CABC_DEFUALT CABC_10 + +#if defined (CONFIG_LGE_BACKLIGHT_CABC_DEBUG) +static int hitachi_cabc_index = CABC_DEFUALT; +#endif + +static char backlight_ctrl1[2][6] = { + + /* off */ + { + 0xB8, 0x00, 0x1A, 0x1A, + 0x02, 0x40 + }, + /* on */ + { + 0xB8, 0x01, 0x1A, 0x1A, + 0x02, 0x40 + }, +}; + +static char backlight_ctrl2[6][8] = { + /* off */ + { + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }, + /* 10% */ + { + 0xB9, 0x18, 0x00, 0x18, + 0x18, 0x9F, 0x1F, 0x0F + }, + + /* 20% */ + { + 0xB9, 0x18, 0x00, 0x18, + 0x18, 0x9F, 0x1F, 0x0F + }, + + /* 30% */ + { + 0xB9, 0x18, 0x00, 0x18, + 0x18, 0x9F, 0x1F, 0x0F + }, + + /* 40% */ + { + 0xB9, 0x18, 0x00, 0x18, + 0x18, 0x9F, 0x1F, 0x0F + }, + /* 50% */ + { + 0xB9, 0x18, 0x00, 0x18, + 0x18, 0x9F, 0x1F, 0x0F + } +}; + +static char backlight_ctrl3[6][25] = { + /* off */ + { + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00 + }, + /* 10% */ + { + 0xBA, 0x00, 0x00, 0x0C, + 0x0A, 0x6C, 0x0A, 0xAC, + 0x0A, 0x0C, 0x0A, 0x00, + 0xDA, 0x6D, 0x03, 0xFF, + 0xFF, 0x10, 0xD9, 0xE4, + 0xEE, 0xF7, 0xFF, 0x9F, + 0x00 + }, + /* 20% */ + { + 0xBA, 0x00, 0x00, 0x0C, + 0x0B, 0x6C, 0x0B, 0xAC, + 0x0B, 0x0C, 0x0B, 0x00, + 0xDA, 0x6D, 0x03, 0xFF, + 0xFF, 0x10, 0xB3, 0xC9, + 0xDC, 0xEE, 0xFF, 0x9F, + 0x00 + }, + /* 30% */ + { + 0xBA, 0x00, 0x00, 0x0C, + 0x0D, 0x6C, 0x0D, 0xAC, + 0x0D, 0x0C, 0x0D, 0x00, + 0xDA, 0x6D, 0x03, 0xFF, + 0xFF, 0x10, 0x8C, 0xAA, + 0xC7, 0xE3, 0xFF, 0x9F, + 0x00 + }, + /* 40% */ + { + 0xBA, 0x00, 0x00, 0x0C, + 0x13, 0xAC, 0x13, 0x6C, + 0x13, 0x0C, 0x13, 0x00, + 0xDA, 0x6D, 0x03, 0xFF, + 0xFF, 0x10, 0x67, 0x89, + 0xAF, 0xD6, 0xFF, 0x9F, + 0x00 + }, + /* 50% */ + { + 0xBA, 0x00, 0x00, 0x0C, + 0x14, 0xAC, 0x14, 0x6C, + 0x14, 0x0C, 0x14, 0x00, + 0xDA, 0x6D, 0x03, 0xFF, + 0xFF, 0x10, 0x37, 0x5A, + 0x87, 0xBD, 0xFF, 0x9F, + 0x00 + } +}; +#endif + +static struct dsi_cmd_desc hitachi_power_on_set[] = { + /* Display initial set */ + {DTYPE_DCS_WRITE1, 1, 0, 0, 20, sizeof(set_address_mode), + set_address_mode}, + {DTYPE_DCS_WRITE1, 1, 0, 0, 0, sizeof(set_pixel_format), + set_pixel_format}, + + /* Sleep mode exit */ + {DTYPE_DCS_WRITE, 1, 0, 0, 70, sizeof(exit_sleep), exit_sleep}, + + /* Manufacturer command protect off */ + {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(macp_off), macp_off}, +#if defined(CONFIG_LGE_BACKLIGHT_CABC) + /* Content adaptive backlight control */ + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(backlight_ctrl1[0]), + backlight_ctrl1[CABC_ON]}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(backlight_ctrl2[0]), + backlight_ctrl2[CABC_DEFUALT]}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(backlight_ctrl3[0]), + backlight_ctrl3[CABC_DEFUALT]}, +#endif + /* Manufacturer command protect on */ + {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(macp_on), macp_on}, + /* Display on */ + {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(display_on), display_on}, +}; + +static struct dsi_cmd_desc hitachi_power_off_set[] = { + {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(display_off), display_off}, + {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(enter_sleep), enter_sleep} +}; + +#if defined (CONFIG_LGE_BACKLIGHT_CABC) &&\ + defined (CONFIG_LGE_BACKLIGHT_CABC_DEBUG) +void set_hitachi_cabc(int cabc_index) +{ + switch(cabc_index) { + case 0: /* off */ + case 1: /* 10% */ + case 2: /* 20% */ + case 3: /* 30% */ + case 4: /* 40% */ + case 5: /* 50% */ + if (cabc_index == 0) { /* CABC OFF */ + hitachi_power_on_set[CABC_POWERON_OFFSET].payload = + backlight_ctrl1[CABC_OFF]; + } else { /* CABC ON */ + hitachi_power_on_set[CABC_POWERON_OFFSET].payload = + backlight_ctrl1[CABC_ON]; + hitachi_power_on_set[CABC_POWERON_OFFSET+1].payload = + backlight_ctrl2[cabc_index]; + hitachi_power_on_set[CABC_POWERON_OFFSET+2].payload = + backlight_ctrl3[cabc_index]; + } + hitachi_cabc_index = cabc_index; + break; + default: + printk("out of range cabc_index %d", cabc_index); + } + return; +} +EXPORT_SYMBOL(set_hitachi_cabc); + +int get_hitachi_cabc(void) +{ + return hitachi_cabc_index; +} +EXPORT_SYMBOL(get_hitachi_cabc); + +#endif +static struct msm_panel_common_pdata mipi_hitachi_pdata = { + .backlight_level = mipi_hitachi_backlight_level, + .power_on_set_1 = hitachi_power_on_set, + .power_off_set_1 = hitachi_power_off_set, + .power_on_set_size_1 = ARRAY_SIZE(hitachi_power_on_set), + .power_off_set_size_1 = ARRAY_SIZE(hitachi_power_off_set), +}; + +static struct platform_device mipi_dsi_hitachi_panel_device = { + .name = "mipi_hitachi", + .id = 0, + .dev = { + .platform_data = &mipi_hitachi_pdata, + } +}; +#elif defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) +static int mipi_lgit_backlight_level(int level, int max, int min) +{ +#ifdef CONFIG_LGE_BACKLIGHT_LM3530 + lm3530_lcd_backlight_set_level(level); +#endif + + return 0; +} + + +/* for making one source of DSV feature. */ +char lcd_mirror [2] = {0x36, 0x02}; + +// values of DSV setting START +static char panel_setting_1_for_DSV [6] = {0xB0, 0x43, 0xFF, 0x80, 0x00, 0x00}; +static char panel_setting_2_for_DSV [3] = {0xB3, 0x0A, 0x9F}; +//static char panel_setting_3_for_DSV [2] = {0xB4, 0x02}; //2 dot inversion + +static char display_mode1_for_DSV [6] = {0xB5, 0x50, 0x20, 0x40, 0x00, 0x20}; +static char display_mode2_for_DSV [8] = {0xB6, 0x00, 0x14, 0x0F, 0x16, 0x13, 0x05, 0x05}; + +static char p_gamma_r_setting_for_DSV[10] = {0xD0, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; +static char n_gamma_r_setting_for_DSV[10] = {0xD1, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; +static char p_gamma_g_setting_for_DSV[10] = {0xD2, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; +static char n_gamma_g_setting_for_DSV[10] = {0xD3, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; +static char p_gamma_b_setting_for_DSV[10] = {0xD4, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; +static char n_gamma_b_setting_for_DSV[10] = {0xD5, 0x40, 0x14, 0x76, 0x00, 0x00, 0x00, 0x50, 0x30, 0x02}; + +#if defined(LGIT_IEF) +static char ief_set0_for_DSV[2] = {0xE0, 0x07}; +static char ief_set1_for_DSV[5] = {0xE1, 0x00, 0x00, 0x01, 0x01}; +static char ief_set2_for_DSV[3] = {0xE2, 0x01, 0x0F}; +static char ief_set3_for_DSV[6] = {0xE3, 0x00, 0x00, 0x42, 0x35, 0x00}; +static char ief_set4_for_DSV[4] = {0xE4, 0x04, 0x01, 0x17}; +static char ief_set5_for_DSV[4] = {0xE5, 0x03, 0x0F, 0x17}; +static char ief_set6_for_DSV[4] = {0xE6, 0x07, 0x00, 0x15}; +static char ief_set7_for_DSV[9] = {0xE7, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; +static char ief_set8_for_DSV[9] = {0xE8, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; +static char ief_set9_for_DSV[9] = {0xE9, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; +static char ief_setA_for_DSV[9] = {0xEA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +static char ief_setB_for_DSV[9] = {0xEB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +static char ief_setC_for_DSV[9] = {0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +#endif + +static char osc_setting_for_DSV[4] = {0xC0, 0x00, 0x0A, 0x10}; +static char power_setting3_for_DSV[13] = {0xC3, 0x00, 0x88, 0x03, 0x20, 0x00, 0x55, 0x4F, 0x33,0x02,0x38,0x38,0x00}; +static char power_setting4_for_DSV[6] = {0xC4, 0x22, 0x24, 0x13, 0x13, 0x3D}; +static char power_setting5_for_DSV[4] = {0xC5, 0x3B, 0x3B, 0x03}; +static char power_setting6_for_DSV[2] = {0x11,0x00}; + +#if defined(CONFIG_LGE_BACKLIGHT_CABC) +static char cabc_set0[2] = {0x51, 0xFF}; +static char cabc_set1[2] = {0x5E, 0x00}; // CABC MIN +//static char cabc_set1[2] = {0x5E, 0x00}; //CABC MAX +static char cabc_set2[2] = {0x53, 0x2C}; +static char cabc_set3[2] = {0x55, 0x02}; +static char cabc_set4[6] = {0xC8, 0x21, 0x21, 0x21, 0x33, 0x80};//A-CABC applied +//static char cabc_set4[6] = {0xC8, 0x04, 0x04, 0x04, 0x33, 0x9F};//CABC MIN +//static char cabc_set4[6] = {0xC8, 0x74, 0x74, 0x74, 0x33, 0x9F};//CABC MAX +//static char cabc_set4[6] = {0xC8, 0x74, 0x74, 0x74, 0x33, 0x80};//CABC MAX - Tuning +#endif + +static char exit_sleep_power_control_1_for_DSV[2] = {0xC2,0x02}; +static char exit_sleep_power_control_2_for_DSV[2] = {0xC2,0x06}; +static char exit_sleep_power_control_3_for_DSV[2] = {0xC2,0x0E}; +static char exit_sleep_power_control_4_for_DSV[2] = {0xC1,0x08}; + +static char display_on_for_DSV[2] = {0x29,0x00}; + +static char display_off_for_DSV[2] = {0x28,0x00}; + +static char enter_sleep_for_DSV[2] = {0x10,0x00}; + +static char enter_sleep_power_control_1_for_DSV[2] = {0xC1,0x00}; +static char enter_sleep_power_control_3_for_DSV[2] = {0xC2,0x01}; +static char enter_sleep_power_control_2_for_DSV[2] = {0xC2,0x00}; + +static char deep_standby_for_DSV[2] = {0xC1,0x03}; + +/* initialize device */ +static struct dsi_cmd_desc lgit_power_on_set_1_for_DSV[] = { + // Display Initial Set + + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(lcd_mirror ),lcd_mirror}, + + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(panel_setting_1_for_DSV ),panel_setting_1_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(panel_setting_2_for_DSV ),panel_setting_2_for_DSV}, +// {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(panel_setting_3_for_DSV ),panel_setting_3_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(display_mode1_for_DSV ),display_mode1_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(display_mode2_for_DSV ),display_mode2_for_DSV}, + + // Gamma Set + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(p_gamma_r_setting_for_DSV),p_gamma_r_setting_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(n_gamma_r_setting_for_DSV),n_gamma_r_setting_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(p_gamma_g_setting_for_DSV),p_gamma_g_setting_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(n_gamma_g_setting_for_DSV),n_gamma_g_setting_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(p_gamma_b_setting_for_DSV),p_gamma_b_setting_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(n_gamma_b_setting_for_DSV),n_gamma_b_setting_for_DSV}, + +#if defined(LGIT_IEF) + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set0_for_DSV),ief_set0_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set1_for_DSV),ief_set1_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set2_for_DSV),ief_set2_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set3_for_DSV),ief_set3_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set4_for_DSV),ief_set4_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set5_for_DSV),ief_set5_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set6_for_DSV),ief_set6_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set7_for_DSV),ief_set7_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set8_for_DSV),ief_set8_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_set9_for_DSV),ief_set9_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_setA_for_DSV),ief_setA_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_setB_for_DSV),ief_setB_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ief_setC_for_DSV),ief_setC_for_DSV}, +#endif + + // Power Supply Set + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(osc_setting_for_DSV ),osc_setting_for_DSV }, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(power_setting3_for_DSV),power_setting3_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(power_setting4_for_DSV),power_setting4_for_DSV}, + + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(power_setting5_for_DSV),power_setting5_for_DSV}, + {DTYPE_DCS_WRITE, 1, 0, 0, 5, sizeof(power_setting6_for_DSV),power_setting6_for_DSV}, + +#if defined(CONFIG_LGE_BACKLIGHT_CABC) + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(cabc_set0),cabc_set0}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(cabc_set1),cabc_set1}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(cabc_set2),cabc_set2}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(cabc_set3),cabc_set3}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(cabc_set4),cabc_set4}, +#endif + + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(exit_sleep_power_control_1_for_DSV ),exit_sleep_power_control_1_for_DSV }, + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(exit_sleep_power_control_2_for_DSV ),exit_sleep_power_control_2_for_DSV }, + {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(exit_sleep_power_control_3_for_DSV ),exit_sleep_power_control_3_for_DSV }, + +}; + +static struct dsi_cmd_desc lgit_power_on_set_2_for_DSV[] = { + // Power Supply Set + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(exit_sleep_power_control_4_for_DSV ),exit_sleep_power_control_4_for_DSV }, + {DTYPE_DCS_WRITE, 1, 0, 0, 20, sizeof(display_on_for_DSV ),display_on_for_DSV }, +}; + +static struct dsi_cmd_desc lgit_power_off_set_1_for_DSV[] = { + {DTYPE_DCS_WRITE, 1, 0, 0, 20, sizeof(display_off_for_DSV), display_off_for_DSV}, + {DTYPE_DCS_WRITE, 1, 0, 0, 20, sizeof(enter_sleep_for_DSV), enter_sleep_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(enter_sleep_power_control_1_for_DSV), enter_sleep_power_control_1_for_DSV}, +}; + +static struct dsi_cmd_desc lgit_power_off_set_2_for_DSV[] = { + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(enter_sleep_power_control_3_for_DSV), enter_sleep_power_control_3_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(enter_sleep_power_control_2_for_DSV), enter_sleep_power_control_2_for_DSV}, + {DTYPE_GEN_LWRITE, 1, 0, 0, 20, sizeof(deep_standby_for_DSV), deep_standby_for_DSV} +}; +// values of DSV setting END + +// values of normal setting START(not DSV) + + +static struct msm_panel_common_pdata mipi_lgit_pdata = { + .backlight_level = mipi_lgit_backlight_level, + .power_on_set_1 = lgit_power_on_set_1_for_DSV, + .power_on_set_2 = lgit_power_on_set_2_for_DSV, + .power_on_set_size_1 = ARRAY_SIZE(lgit_power_on_set_1_for_DSV), + .power_on_set_size_2 =ARRAY_SIZE(lgit_power_on_set_2_for_DSV), + .power_off_set_1 = lgit_power_off_set_1_for_DSV, + .power_off_set_2 = lgit_power_off_set_2_for_DSV, + .power_off_set_size_1 = ARRAY_SIZE(lgit_power_off_set_1_for_DSV), + .power_off_set_size_2 =ARRAY_SIZE(lgit_power_off_set_2_for_DSV), + +}; + +static struct platform_device mipi_dsi_lgit_panel_device = { + .name = "mipi_lgit", + .id = 0, + .dev = { + .platform_data = &mipi_lgit_pdata, + } +}; +#endif + +static struct platform_device *mako_panel_devices[] __initdata = { +#if defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) + &mipi_dsi_hitachi_panel_device, +#elif defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) + &mipi_dsi_lgit_panel_device, +#endif +#ifdef CONFIG_LGE_KCAL + &kcal_platrom_device, +#endif +}; + +void __init apq8064_init_fb(void) +{ + platform_device_register(&msm_fb_device); + +#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL + platform_device_register(&wfd_panel_device); + platform_device_register(&wfd_device); +#endif + + platform_add_devices(mako_panel_devices, + ARRAY_SIZE(mako_panel_devices)); + + msm_fb_register_device("mdp", &mdp_pdata); + msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata); + + platform_device_register(&hdmi_msm_device); + msm_fb_register_device("dtv", &dtv_pdata); + +} + +#define I2C_SURF 1 +#define I2C_FFA (1 << 1) +#define I2C_RUMI (1 << 2) +#define I2C_SIM (1 << 3) +#define I2C_LIQUID (1 << 4) +#define I2C_J1V (1 << 5) + +struct i2c_registry { + u8 machs; + int bus; + struct i2c_board_info *info; + int len; +}; + +#if defined(CONFIG_LGE_BACKLIGHT_CABC) +#define PWM_SIMPLE_EN 0xA0 +#define PWM_BRIGHTNESS 0x20 +#endif + +struct backlight_platform_data { + void (*platform_init)(void); + int gpio; + unsigned int mode; + int max_current; + int init_on_boot; + int min_brightness; + int max_brightness; + int default_brightness; + int factory_brightness; +}; + +#if defined (CONFIG_LGE_BACKLIGHT_LM3530) +static struct backlight_platform_data lm3530_data = { + + .gpio = PM8921_GPIO_PM_TO_SYS(24), +#if defined(CONFIG_LGE_BACKLIGHT_CABC) + .max_current = 0x17 | PWM_BRIGHTNESS, +#else + .max_current = 0x17, +#endif + .min_brightness = 0x01, + .max_brightness = 0x71, + +}; +#elif defined(CONFIG_LGE_BACKLIGHT_LM3533) +static struct backlight_platform_data lm3533_data = { + .gpio = PM8921_GPIO_PM_TO_SYS(24), +#if defined(CONFIG_LGE_BACKLIGHT_CABC) + .max_current = 0x17 | PWM_SIMPLE_EN, +#else + .max_current = 0x17, +#endif + .min_brightness = 0x05, + .max_brightness = 0xFF, + .default_brightness = 0x9C, + .factory_brightness = 0x78, +}; +#endif +static struct i2c_board_info msm_i2c_backlight_info[] = { + { + +#if defined(CONFIG_LGE_BACKLIGHT_LM3530) + I2C_BOARD_INFO("lm3530", 0x38), + .platform_data = &lm3530_data, +#elif defined(CONFIG_LGE_BACKLIGHT_LM3533) + I2C_BOARD_INFO("lm3533", 0x36), + .platform_data = &lm3533_data, +#endif + } +}; + +static struct i2c_registry apq8064_i2c_backlight_device[] __initdata = { + + { + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + msm_i2c_backlight_info, + ARRAY_SIZE(msm_i2c_backlight_info), + }, +}; + +void __init register_i2c_backlight_devices(void) +{ + u8 mach_mask = 0; + int i; + + /* Build the matching 'supported_machs' bitmask */ + if (machine_is_apq8064_cdp()) + mach_mask = I2C_SURF; + else if (machine_is_apq8064_mtp()) + mach_mask = I2C_FFA; + else if (machine_is_apq8064_liquid()) + mach_mask = I2C_LIQUID; + else if (machine_is_apq8064_rumi3()) + mach_mask = I2C_RUMI; + else if (machine_is_apq8064_sim()) + mach_mask = I2C_SIM; + else + pr_err("unmatched machine ID in register_i2c_devices\n"); + + /* Run the array and install devices as appropriate */ + for (i = 0; i < ARRAY_SIZE(apq8064_i2c_backlight_device); ++i) { + if (apq8064_i2c_backlight_device[i].machs & mach_mask) + i2c_register_board_info(apq8064_i2c_backlight_device[i].bus, + apq8064_i2c_backlight_device[i].info, + apq8064_i2c_backlight_device[i].len); + } +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-gpiomux.c b/arch/arm/mach-msm/lge/mako/board-mako-gpiomux.c new file mode 100644 index 000000000000..a1e66a1a9d15 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-gpiomux.c @@ -0,0 +1,1047 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" +#include "board-mako.h" + +#ifdef CONFIG_MSM_VCAP +static struct gpiomux_setting gpio_vcap_config[] = { + { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_2, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_3, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_4, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_5, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_6, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_7, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_8, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_9, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, + { + .func = GPIOMUX_FUNC_A, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + }, +}; + +struct msm_gpiomux_config vcap_configs[] = { + { + .gpio = 20, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[7], + } + }, + { + .gpio = 25, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 24, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[1], + } + }, + { + .gpio = 23, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 19, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[8], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[8], + } + }, + { + .gpio = 22, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 21, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[7], + } + }, + { + .gpio = 12, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[6], + } + }, + { + .gpio = 18, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[9], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[9], + } + }, + { + .gpio = 11, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[10], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[10], + } + }, + { + .gpio = 10, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[9], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[9], + } + }, + { + .gpio = 9, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 26, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[1], + } + }, + { + .gpio = 8, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[3], + } + }, + { + .gpio = 7, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[7], + } + }, + { + .gpio = 6, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[7], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[7], + } + }, + { + .gpio = 80, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 86, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[1], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[1], + } + }, + { + .gpio = 85, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[4], + } + }, + { + .gpio = 84, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[3], + } + }, + { + .gpio = 5, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 4, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[3], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[3], + } + }, + { + .gpio = 3, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[6], + } + }, + { + .gpio = 2, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[5], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[5], + } + }, + { + .gpio = 82, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[4], + } + }, + { + .gpio = 83, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[4], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[4], + } + }, + { + .gpio = 87, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[2], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[2], + } + }, + { + .gpio = 13, + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_vcap_config[6], + [GPIOMUX_ACTIVE] = &gpio_vcap_config[6], + } + }, +}; +#endif + +static struct gpiomux_setting mbhc_hs_detect = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting cdc_mclk = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting wcnss_5wire_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting wcnss_5wire_active_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_6MA, + .pull = GPIOMUX_PULL_DOWN, +}; + + +static struct gpiomux_setting slimbus = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_KEEPER, +}; + +static struct gpiomux_setting gsbi4_uart = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; +static struct gpiomux_setting gsbi4_uart_active = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) +static struct gpiomux_setting gsbi6_felica = { + .func = GPIOMUX_FUNC_2, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; +static struct gpiomux_setting gsbi6_felica_active = { + .func = GPIOMUX_FUNC_2, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_UP, +}; +#endif + +static struct gpiomux_setting gsbi1_suspended_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_KEEPER, +}; + +static struct gpiomux_setting gsbi1_active_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting gsbi2_suspended_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_KEEPER, +}; + +static struct gpiomux_setting gsbi2_active_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting gsbi3_suspended_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_KEEPER, +}; + +static struct gpiomux_setting gsbi3_active_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting hdmi_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting hdmi_active_1_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting hdmi_active_2_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_16MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting sx150x_suspended_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting sx150x_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting cyts_sleep_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_6MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting cyts_sleep_act_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_6MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting cyts_int_act_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting cyts_int_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct msm_gpiomux_config cyts_gpio_configs[] __initdata = { + { /* TS INTERRUPT */ + .gpio = 6, + .settings = { + [GPIOMUX_ACTIVE] = &cyts_int_act_cfg, + [GPIOMUX_SUSPENDED] = &cyts_int_sus_cfg, + }, + }, + { /* TS SLEEP */ + .gpio = 33, + .settings = { + [GPIOMUX_ACTIVE] = &cyts_sleep_act_cfg, + [GPIOMUX_SUSPENDED] = &cyts_sleep_sus_cfg, + }, + }, +}; + +#ifdef CONFIG_USB_EHCI_MSM_HSIC +static struct gpiomux_setting hsic_act_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting hsic_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_OUT_LOW, +}; + +static struct gpiomux_setting hsic_wakeup_act_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting hsic_wakeup_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_IN, +}; + +static struct msm_gpiomux_config apq8064_hsic_configs[] = { + { + .gpio = 88, /*HSIC_STROBE */ + .settings = { + [GPIOMUX_ACTIVE] = &hsic_act_cfg, + [GPIOMUX_SUSPENDED] = &hsic_sus_cfg, + }, + }, + { + .gpio = 89, /* HSIC_DATA */ + .settings = { + [GPIOMUX_ACTIVE] = &hsic_act_cfg, + [GPIOMUX_SUSPENDED] = &hsic_sus_cfg, + }, + }, + { + .gpio = 47, /* wake up */ + .settings = { + [GPIOMUX_ACTIVE] = &hsic_wakeup_act_cfg, + [GPIOMUX_SUSPENDED] = &hsic_wakeup_sus_cfg, + }, + }, +}; +#endif + +static struct gpiomux_setting mxt_reset_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_6MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting mxt_reset_act_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_6MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting mxt_int_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting mxt_int_act_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct msm_gpiomux_config apq8064_hdmi_configs[] __initdata = { + { + .gpio = 69, + .settings = { + [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg, + [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg, + }, + }, + { + .gpio = 70, + .settings = { + [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg, + [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg, + }, + }, + { + .gpio = 71, + .settings = { + [GPIOMUX_ACTIVE] = &hdmi_active_1_cfg, + [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg, + }, + }, + { + .gpio = 72, + .settings = { + [GPIOMUX_ACTIVE] = &hdmi_active_2_cfg, + [GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg, + }, + }, +}; + +static struct msm_gpiomux_config apq8064_gsbi_configs[] __initdata = { + { + .gpio = 20, /* GSBI1 I2C QUP SDA */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi1_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi1_active_cfg, + }, + }, + { + .gpio = 21, /* GSBI1 I2C QUP SCL */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi1_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi1_active_cfg, + }, + }, + { + .gpio = 24, /* GSBI2 I2C QUP SDA */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi2_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi2_active_cfg, + }, + }, + { + .gpio = 25, /* GSBI2 I2C QUP SCL */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi2_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi2_active_cfg, + }, + }, + { + .gpio = 8, /* GSBI3 I2C QUP SDA */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi3_active_cfg, + }, + }, + { + .gpio = 9, /* GSBI3 I2C QUP SCL */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg, + [GPIOMUX_ACTIVE] = &gsbi3_active_cfg, + }, + }, + { + .gpio = 10, /* GSBI4 UART TX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi4_uart, + [GPIOMUX_ACTIVE] = &gsbi4_uart_active + }, + }, + { + .gpio = 11, /* GSBI4 UART RX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gsbi4_uart, + [GPIOMUX_ACTIVE] = &gsbi4_uart_active + }, + }, +}; + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) +static struct msm_gpiomux_config apq8064_felica_uart_configs[] __initdata = { + { + .gpio = 14, /* GSBI6 UART TX */ + .settings = { + [GPIOMUX_ACTIVE] = &gsbi6_felica_active, + [GPIOMUX_SUSPENDED] = &gsbi6_felica, + }, + }, + { + .gpio = 15, /* GSBI6 UART RX */ + .settings = { + [GPIOMUX_ACTIVE] = &gsbi6_felica_active, + [GPIOMUX_SUSPENDED] = &gsbi6_felica, + }, + }, +}; +#endif +static struct msm_gpiomux_config apq8064_slimbus_config[] __initdata = { + { + .gpio = 40, /* slimbus clk */ + .settings = { + [GPIOMUX_SUSPENDED] = &slimbus, + }, + }, + { + .gpio = 41, /* slimbus data */ + .settings = { + [GPIOMUX_SUSPENDED] = &slimbus, + }, + }, +}; + +static struct gpiomux_setting spkr_i2c = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_KEEPER, +}; + +static struct msm_gpiomux_config mpq8064_spkr_i2s_config[] __initdata = { + { + .gpio = 47, /* spkr i2c sck */ + .settings = { + [GPIOMUX_SUSPENDED] = &spkr_i2c, + }, + }, + { + .gpio = 48, /* spkr_i2s_ws */ + .settings = { + [GPIOMUX_SUSPENDED] = &spkr_i2c, + }, + }, + { + .gpio = 49, /* spkr_i2s_dout */ + .settings = { + [GPIOMUX_SUSPENDED] = &spkr_i2c, + }, + }, + { + .gpio = 50, /* spkr_i2s_mclk */ + .settings = { + [GPIOMUX_SUSPENDED] = &spkr_i2c, + }, + }, +}; + +static struct msm_gpiomux_config apq8064_audio_codec_configs[] __initdata = { + { + .gpio = 38, + .settings = { + [GPIOMUX_SUSPENDED] = &mbhc_hs_detect, + }, + }, + { + .gpio = 39, + .settings = { + [GPIOMUX_SUSPENDED] = &cdc_mclk, + }, + }, +}; + +static struct gpiomux_setting ap2mdm_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting mdm2ap_status_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting mdm2ap_errfatal_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_16MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting ap2mdm_soft_reset_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct gpiomux_setting ap2mdm_wakeup = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_DOWN, +}; + +static struct msm_gpiomux_config mdm_configs[] __initdata = { + /* AP2MDM_STATUS */ + { + .gpio = 48, + .settings = { + [GPIOMUX_SUSPENDED] = &ap2mdm_cfg, + } + }, + /* MDM2AP_STATUS */ + { + .gpio = 49, + .settings = { + [GPIOMUX_SUSPENDED] = &mdm2ap_status_cfg, + } + }, + /* MDM2AP_ERRFATAL */ + { + .gpio = 19, + .settings = { + [GPIOMUX_SUSPENDED] = &mdm2ap_errfatal_cfg, + } + }, + /* AP2MDM_ERRFATAL */ + { + .gpio = 18, + .settings = { + [GPIOMUX_SUSPENDED] = &ap2mdm_cfg, + } + }, + /* AP2MDM_SOFT_RESET, aka AP2MDM_PON_RESET_N */ + { + .gpio = 27, + .settings = { + [GPIOMUX_SUSPENDED] = &ap2mdm_soft_reset_cfg, + } + }, + /* AP2MDM_WAKEUP */ + { + .gpio = 35, + .settings = { + [GPIOMUX_SUSPENDED] = &ap2mdm_wakeup, + } + }, +}; + +static struct gpiomux_setting mi2s_act_cfg = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting mi2s_sus_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, +}; +static struct msm_gpiomux_config mpq8064_mi2s_configs[] __initdata = { + { + .gpio = 27, /* mi2s ws */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + { + .gpio = 28, /* mi2s sclk */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + { + .gpio = 29, /* mi2s dout3 */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + { + .gpio = 30, /* mi2s dout2 */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + + { + .gpio = 31, /* mi2s dout1 */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + { + .gpio = 32, /* mi2s dout0 */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, + + { + .gpio = 33, /* mi2s mclk */ + .settings = { + [GPIOMUX_ACTIVE] = &mi2s_act_cfg, + [GPIOMUX_SUSPENDED] = &mi2s_sus_cfg, + }, + }, +}; +static struct msm_gpiomux_config apq8064_mxt_configs[] __initdata = { + { /* TS INTERRUPT */ + .gpio = 6, + .settings = { + [GPIOMUX_ACTIVE] = &mxt_int_act_cfg, + [GPIOMUX_SUSPENDED] = &mxt_int_sus_cfg, + }, + }, + { /* TS RESET */ + .gpio = 33, + .settings = { + [GPIOMUX_ACTIVE] = &mxt_reset_act_cfg, + [GPIOMUX_SUSPENDED] = &mxt_reset_sus_cfg, + }, + }, +}; + +static struct msm_gpiomux_config wcnss_5wire_interface[] = { + { + .gpio = 64, + .settings = { + [GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg, + [GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg, + }, + }, + { + .gpio = 65, + .settings = { + [GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg, + [GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg, + }, + }, + { + .gpio = 66, + .settings = { + [GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg, + [GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg, + }, + }, + { + .gpio = 67, + .settings = { + [GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg, + [GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg, + }, + }, + { + .gpio = 68, + .settings = { + [GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg, + [GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg, + }, + }, +}; + +static struct gpiomux_setting ir_suspended_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting ir_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct msm_gpiomux_config mpq8064_ir_configs[] __initdata = { + { + .gpio = 88, /* GPIO IR */ + .settings = { + [GPIOMUX_SUSPENDED] = &ir_suspended_cfg, + [GPIOMUX_ACTIVE] = &ir_active_cfg, + }, + }, +}; + +static struct msm_gpiomux_config sx150x_int_configs[] __initdata = { + { + .gpio = 81, + .settings = { + [GPIOMUX_SUSPENDED] = &sx150x_suspended_cfg, + [GPIOMUX_ACTIVE] = &sx150x_active_cfg, + }, + }, +}; + +#if defined(CONFIG_LGE_NFC_PN544) +static struct gpiomux_setting nfc_pn544_ven_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_LOW, +}; + +static struct gpiomux_setting nfc_pn544_irq_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting nfc_pn544_firm_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_LOW, +}; + +static struct msm_gpiomux_config apq8064_nfc_configs[] __initdata = { + { + .gpio = 37, + .settings = { + [GPIOMUX_SUSPENDED] = &nfc_pn544_firm_cfg, + }, + }, + { + .gpio = 29, + .settings = { + [GPIOMUX_SUSPENDED] = &nfc_pn544_irq_cfg, + }, + }, + { + .gpio = 55, + .settings = { + [GPIOMUX_SUSPENDED] = &nfc_pn544_ven_cfg, + }, + }, +}; +#endif + +void __init apq8064_init_gpiomux(void) +{ + int rc; + + rc = msm_gpiomux_init(NR_GPIO_IRQS); + if (rc) { + pr_err(KERN_ERR "msm_gpiomux_init failed %d\n", rc); + return; + } + + msm_gpiomux_install(wcnss_5wire_interface, + ARRAY_SIZE(wcnss_5wire_interface)); + + if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv()) { + +#ifdef CONFIG_MSM_VCAP + msm_gpiomux_install(vcap_configs, + ARRAY_SIZE(vcap_configs)); +#endif + msm_gpiomux_install(sx150x_int_configs, + ARRAY_SIZE(sx150x_int_configs)); + } else { + msm_gpiomux_install(apq8064_gsbi_configs, + ARRAY_SIZE(apq8064_gsbi_configs)); + } +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) + msm_gpiomux_install(apq8064_felica_uart_configs, + ARRAY_SIZE(apq8064_felica_uart_configs)); +#endif + msm_gpiomux_install(apq8064_slimbus_config, + ARRAY_SIZE(apq8064_slimbus_config)); + + msm_gpiomux_install(apq8064_audio_codec_configs, + ARRAY_SIZE(apq8064_audio_codec_configs)); + + if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv()) { + msm_gpiomux_install(mpq8064_spkr_i2s_config, + ARRAY_SIZE(mpq8064_spkr_i2s_config)); + } + + pr_debug("%s(): audio-auxpcm: Include GPIO configs" + " as audio is not the primary user" + " for these GPIO Pins\n", __func__); + + if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv()) + msm_gpiomux_install(mpq8064_mi2s_configs, + ARRAY_SIZE(mpq8064_mi2s_configs)); + + if (machine_is_apq8064_mtp()) + msm_gpiomux_install(mdm_configs, + ARRAY_SIZE(mdm_configs)); + + if (machine_is_apq8064_mtp()) + msm_gpiomux_install(cyts_gpio_configs, + ARRAY_SIZE(cyts_gpio_configs)); + +#ifdef CONFIG_USB_EHCI_MSM_HSIC + if (machine_is_apq8064_mtp()) + msm_gpiomux_install(apq8064_hsic_configs, + ARRAY_SIZE(apq8064_hsic_configs)); +#endif +#if defined(CONFIG_LGE_NFC_PN544) + msm_gpiomux_install(apq8064_nfc_configs, + ARRAY_SIZE(apq8064_nfc_configs)); +#endif + + if (machine_is_apq8064_cdp() || machine_is_apq8064_liquid()) + msm_gpiomux_install(apq8064_mxt_configs, + ARRAY_SIZE(apq8064_mxt_configs)); + + msm_gpiomux_install(apq8064_hdmi_configs, + ARRAY_SIZE(apq8064_hdmi_configs)); + + if (machine_is_mpq8064_cdp()) + msm_gpiomux_install(mpq8064_ir_configs, + ARRAY_SIZE(mpq8064_ir_configs)); +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-gpu.c b/arch/arm/mach-msm/lge/mako/board-mako-gpu.c new file mode 100644 index 000000000000..6176696212ce --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-gpu.c @@ -0,0 +1,252 @@ +/* Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "board-mako.h" + +#ifdef CONFIG_MSM_DCVS +static struct msm_dcvs_freq_entry grp3d_freq[] = { + {0, 0, 333932}, + {0, 0, 497532}, + {0, 0, 707610}, + {0, 0, 844545}, +}; + +static struct msm_dcvs_core_info grp3d_core_info = { + .freq_tbl = &grp3d_freq[0], + .core_param = { + .max_time_us = 100000, + .num_freq = ARRAY_SIZE(grp3d_freq), + }, + .algo_param = { + .slack_time_us = 39000, + .disable_pc_threshold = 86000, + .ss_window_size = 1000000, + .ss_util_pct = 95, + .em_max_util_pct = 97, + .ss_iobusy_conv = 100, + }, +}; +#endif /* CONFIG_MSM_DCVS */ + +#ifdef CONFIG_MSM_BUS_SCALING +static struct msm_bus_vectors grp3d_init_vectors[] = { + { + .src = MSM_BUS_MASTER_GRAPHICS_3D, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +static struct msm_bus_vectors grp3d_low_vectors[] = { + { + .src = MSM_BUS_MASTER_GRAPHICS_3D, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(1000), + }, + { + .src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(1000), + }, +}; + +static struct msm_bus_vectors grp3d_nominal_low_vectors[] = { + { + .src = MSM_BUS_MASTER_GRAPHICS_3D, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(2000), + }, + { + .src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(2000), + }, +}; + +static struct msm_bus_vectors grp3d_nominal_high_vectors[] = { + { + .src = MSM_BUS_MASTER_GRAPHICS_3D, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(3200), + }, + { + .src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(3200), + }, +}; + +static struct msm_bus_vectors grp3d_max_vectors[] = { + { + .src = MSM_BUS_MASTER_GRAPHICS_3D, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(4264), + }, + { + .src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = KGSL_CONVERT_TO_MBPS(4264), + }, +}; + +static struct msm_bus_paths grp3d_bus_scale_usecases[] = { + { + ARRAY_SIZE(grp3d_init_vectors), + grp3d_init_vectors, + }, + { + ARRAY_SIZE(grp3d_low_vectors), + grp3d_low_vectors, + }, + { + ARRAY_SIZE(grp3d_nominal_low_vectors), + grp3d_nominal_low_vectors, + }, + { + ARRAY_SIZE(grp3d_nominal_high_vectors), + grp3d_nominal_high_vectors, + }, + { + ARRAY_SIZE(grp3d_max_vectors), + grp3d_max_vectors, + }, +}; + +static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = { + grp3d_bus_scale_usecases, + ARRAY_SIZE(grp3d_bus_scale_usecases), + .name = "grp3d", +}; +#endif + +static struct resource kgsl_3d0_resources[] = { + { + .name = KGSL_3D0_REG_MEMORY, + .start = 0x04300000, /* GFX3D address */ + .end = 0x0431ffff, + .flags = IORESOURCE_MEM, + }, + { + .name = KGSL_3D0_IRQ, + .start = GFX3D_IRQ, + .end = GFX3D_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static const struct kgsl_iommu_ctx kgsl_3d0_iommu0_ctxs[] = { + { "gfx3d_user", 0 }, + { "gfx3d_priv", 1 }, +}; + +static const struct kgsl_iommu_ctx kgsl_3d0_iommu1_ctxs[] = { + { "gfx3d1_user", 0 }, + { "gfx3d1_priv", 1 }, +}; + +static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = { + { + .iommu_ctxs = kgsl_3d0_iommu0_ctxs, + .iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu0_ctxs), + .physstart = 0x07C00000, + .physend = 0x07C00000 + SZ_1M - 1, + }, + { + .iommu_ctxs = kgsl_3d0_iommu1_ctxs, + .iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu1_ctxs), + .physstart = 0x07D00000, + .physend = 0x07D00000 + SZ_1M - 1, + }, +}; + +static struct kgsl_device_platform_data kgsl_3d0_pdata = { + .pwrlevel = { + { + .gpu_freq = 400000000, + .bus_freq = 4, + .io_fraction = 0, + }, + { + .gpu_freq = 325000000, + .bus_freq = 3, + .io_fraction = 33, + }, + { + .gpu_freq = 200000000, + .bus_freq = 2, + .io_fraction = 100, + }, + { + .gpu_freq = 128000000, + .bus_freq = 1, + .io_fraction = 100, + }, + { + .gpu_freq = 27000000, + .bus_freq = 0, + }, + }, + .init_level = 1, + .num_levels = 5, + .set_grp_async = NULL, + .idle_timeout = HZ/10, + .nap_allowed = true, + .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE, +#ifdef CONFIG_MSM_BUS_SCALING + .bus_scale_table = &grp3d_bus_scale_pdata, +#endif + .iommu_data = kgsl_3d0_iommu_data, + .iommu_count = ARRAY_SIZE(kgsl_3d0_iommu_data), +#ifdef CONFIG_MSM_DCVS + .core_info = &grp3d_core_info, +#endif +}; + +struct platform_device device_kgsl_3d0 = { + .name = "kgsl-3d0", + .id = 0, + .num_resources = ARRAY_SIZE(kgsl_3d0_resources), + .resource = kgsl_3d0_resources, + .dev = { + .platform_data = &kgsl_3d0_pdata, + }, +}; + +void __init apq8064_init_gpu(void) +{ + platform_device_register(&device_kgsl_3d0); +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-input.c b/arch/arm/mach-msm/lge/mako/board-mako-input.c new file mode 100644 index 000000000000..95adc796bde6 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-input.c @@ -0,0 +1,310 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* keypad */ +#include + +/* i2c */ +#include +#include + +#ifdef CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 +#include +#include +#endif + +#include +#ifdef CONFIG_TOUCHSCREEN_MMS136 +#include +#endif + +#if defined(CONFIG_RMI4_I2C) +#include +#endif + +#include "board-mako.h" + +/* TOUCH GPIOS */ +#define SYNAPTICS_TS_I2C_SDA 8 +#define SYNAPTICS_TS_I2C_SCL 9 +#define SYNAPTICS_TS_I2C_INT_GPIO 6 +#define TOUCH_RESET 33 + +#define TOUCH_FW_VERSION 1 + +/* touch screen device */ +#define APQ8064_GSBI3_QUP_I2C_BUS_ID 3 + +#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) +int synaptics_t1320_power_on(int on) +{ + int rc = -EINVAL; + static struct regulator *vreg_l15; + static struct regulator *vreg_l22; + + vreg_l15 = regulator_get(NULL, "8921_l15"); //3.3V_TOUCH_VDD, VREG_L15: 2.75 ~ 3.3 + if (IS_ERR(vreg_l15)) { + pr_err("%s: regulator get of 8921_l15 failed (%ld)\n", __func__, + PTR_ERR(vreg_l15)); + rc = PTR_ERR(vreg_l15); + return rc; + } + vreg_l22 = regulator_get(NULL, "8921_l22"); //1.8V_TOUCH_IO, VREG_L22: 1.7 ~ 2.85 + if (IS_ERR(vreg_l22)) { + pr_err("%s: regulator get of 8921_l22 failed (%ld)\n", __func__, + PTR_ERR(vreg_l22)); + rc = PTR_ERR(vreg_l22); + return rc; + } + + rc = regulator_set_voltage(vreg_l15, 3300000, 3300000); + rc = regulator_set_voltage(vreg_l22, 1800000, 1800000); + + if (on) { + printk("[Touch D]touch enable\n"); + regulator_enable(vreg_l15); + regulator_enable(vreg_l22); + } else { + printk("[Touch D]touch disable\n"); + regulator_disable(vreg_l15); + regulator_disable(vreg_l22); + } + + if (rc < 0) { + printk(KERN_INFO "[Touch D] %s: cannot request GPIO\n", + __func__); + return rc; + } + + return rc; +} + +static struct touch_power_module touch_pwr = { + .use_regulator = 0, + .vdd = "8921_l15", + .vdd_voltage = 3300000, + .vio = "8921_l22", + .vio_voltage = 1800000, + .power = synaptics_t1320_power_on, +}; + +static struct touch_device_caps touch_caps = { + .button_support = 1, + .y_button_boundary = 0, + .number_of_button = 3, + .button_name = {KEY_BACK, KEY_HOMEPAGE, KEY_MENU}, + .button_margin = 0, + .is_width_supported = 1, + .is_pressure_supported = 1, + .is_id_supported = 1, + .max_width = 15, + .max_pressure = 0xFF, + .max_id = 10, + .lcd_x = 768, + .lcd_y = 1280, + .x_max = 1100, + .y_max = 1900, +}; + +static struct touch_operation_role touch_role = { + .operation_mode = INTERRUPT_MODE, + .key_type = TOUCH_HARD_KEY, + .report_mode = CONTINUOUS_REPORT_MODE, + .delta_pos_threshold = 0, + .orientation = 0, + .report_period = 10000000, + .booting_delay = 400, + .reset_delay = 20, + .suspend_pwr = POWER_OFF, + .resume_pwr = POWER_ON, + .jitter_filter_enable = 1, + .jitter_curr_ratio = 30, + .accuracy_filter_enable = 1, + .irqflags = IRQF_TRIGGER_FALLING, +#if defined(CONFIG_TOUCH_REG_MAP_TM2000) || defined(CONFIG_TOUCH_REG_MAP_TM2372) + .show_touches = 0, + .pointer_location = 0, +#endif +}; + +static struct touch_platform_data mako_ts_data = { + .int_pin = SYNAPTICS_TS_I2C_INT_GPIO, + .reset_pin = TOUCH_RESET, + .maker = "Synaptics", + .caps = &touch_caps, + .role = &touch_role, + .pwr = &touch_pwr, +}; + +static struct i2c_board_info synaptics_ts_info[] = { + [0] = { + I2C_BOARD_INFO(LGE_TOUCH_NAME, 0x20), + .platform_data = &mako_ts_data, + .irq = MSM_GPIO_TO_INT(SYNAPTICS_TS_I2C_INT_GPIO), + }, +}; +#endif + +#if defined(CONFIG_RMI4_I2C) +struct syna_gpio_data { + u16 gpio_number; + char *gpio_name; +}; + +static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure) +{ + + int rc = -EINVAL; + static struct regulator *vreg_l15; + static struct regulator *vreg_l22; + + struct syna_gpio_data *data = gpio_data; + + pr_err("%s: [Touch D] S1 \n", __func__); + + /* Touch IC Power On */ + vreg_l15 = regulator_get(NULL, "8921_l15"); //3.3V_TOUCH_VDD, VREG_L15: 2.75 ~ 3.3 + if (IS_ERR(vreg_l15)) { + pr_err("%s: regulator get of 8921_l15 failed (%ld)\n", __func__, + PTR_ERR(vreg_l15)); + rc = PTR_ERR(vreg_l15); + return rc; + } + + pr_err("%s: [Touch D] S2 \n", __func__); + vreg_l22 = regulator_get(NULL, "8921_l22"); //1.8V_TOUCH_IO, VREG_L22: 1.7 ~ 2.85 + if (IS_ERR(vreg_l22)) { + pr_err("%s: regulator get of 8921_l22 failed (%ld)\n", __func__, + PTR_ERR(vreg_l22)); + rc = PTR_ERR(vreg_l22); + return rc; + } + pr_err("%s: [Touch D] S3 \n", __func__); + rc = regulator_set_voltage(vreg_l15, 3300000, 3300000); + rc = regulator_set_voltage(vreg_l22, 1800000, 1800000); + + regulator_enable(vreg_l15); + regulator_enable(vreg_l22); + + if (configure) { + rc = gpio_request(data->gpio_number, "rmi4_attn"); + if (rc) { + pr_err("%s: Failed to get attn gpio %d. Code: %d.", + __func__, data->gpio_number, rc); + return rc; + } + + gpio_tlmm_config(GPIO_CFG(data->gpio_number, 0, GPIO_CFG_INPUT, + GPIO_CFG_PULL_UP, GPIO_CFG_6MA), + GPIO_CFG_ENABLE); + + rc = gpio_direction_input(data->gpio_number); + if (rc) { + pr_err("%s: Failed to setup attn gpio %d. Code: %d.", + __func__, data->gpio_number, rc); + gpio_free(data->gpio_number); + } + } else { + pr_warn("%s: No way to deconfigure gpio %d.", + __func__, data->gpio_number); + } + + if (rc < 0) { + printk(KERN_INFO "[Touch D] %s: cannot request GPIO\n", + __func__); + return rc; + } + + printk("[Touch D]synaptics_touchpad_gpio_setup -- \n"); + + return rc; +} + +#define AXIS_ALIGNMENT { \ + .swap_axes = false, \ + .flip_x = false, \ + .flip_y = false, \ + .clip_X_low = 0, \ + .clip_Y_low = 0, \ + .offset_X = 0, \ + .offset_Y = 0, \ +} + +#define TM2144_ADDR 0x20 +#define TM2144_ATTN 6 + +static unsigned char tm2144_button_codes[] = { + KEY_BACK, KEY_HOMEPAGE, KEY_MENU +}; +static struct rmi_f1a_button_map tm2144_button_map = { + .nbuttons = ARRAY_SIZE(tm2144_button_codes), + .map = tm2144_button_codes, +}; + +static struct syna_gpio_data tm2144_gpiodata = { + .gpio_number = TM2144_ATTN, + .gpio_name = "ts_int.gpio_6", +}; + +static struct rmi_device_platform_data tm2144_platformdata = { + .driver_name = "rmi_generic", + .sensor_name = "TM2144", + .attn_gpio = TM2144_ATTN, + .attn_polarity = RMI_ATTN_ACTIVE_LOW, + .gpio_data = &tm2144_gpiodata, + .gpio_config = synaptics_touchpad_gpio_setup, + .axis_align = AXIS_ALIGNMENT, + .f1a_button_map = &tm2144_button_map, + .reset_delay_ms = 100, +}; + +static struct i2c_board_info synaptics_ds4_rmi_info[] = { + [0] = { + I2C_BOARD_INFO("rmi_i2c", TM2144_ADDR), + .platform_data = &tm2144_platformdata, + }, +}; + +#endif + +/* common function */ +void __init apq8064_init_input(void) +{ +#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) + printk(KERN_INFO "[Touch D] %s: NOT DCM KDDI, reg synaptics driver \n", + __func__); + i2c_register_board_info(APQ8064_GSBI3_QUP_I2C_BUS_ID, + &synaptics_ts_info[0], 1); +#endif + +/* Wireless Debugging Porting */ +#if defined(CONFIG_RMI4_I2C) + i2c_register_board_info(APQ8064_GSBI3_QUP_I2C_BUS_ID, + &synaptics_ds4_rmi_info[0], 1); +#endif +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-misc.c b/arch/arm/mach-msm/lge/mako/board-mako-misc.c new file mode 100644 index 000000000000..c83e3dba4d39 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-misc.c @@ -0,0 +1,631 @@ +/* + * Copyright (C) 2011,2012 LGE, Inc. + * + * Author: Sungwoo Cho + * + * This software is licensed under the terms of the GNU General + * License version 2, as published by the Free Software Foundation, + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "devices.h" +#include + +#include + +#ifdef CONFIG_LGE_ISA1200 +#include +#endif + +#ifdef CONFIG_SII8334_MHL_TX +#include +#endif + +#ifdef CONFIG_BU52031NVX +#include +#endif + +#include "board-mako.h" +/* gpio and clock control for vibrator */ + +#define REG_WRITEL(value, reg) writel(value, (MSM_CLK_CTL_BASE+reg)) +#define REG_READL(reg) readl((MSM_CLK_CTL_BASE+reg)) + +#define GPn_MD_REG(n) (0x2D00+32*(n)) +#define GPn_NS_REG(n) (0x2D24+32*(n)) + +/* When use SM100 with GP_CLK + 170Hz motor : 22.4KHz - M=1, N=214 , + 230Hz motor : 29.4KHZ - M=1, N=163 , + */ + +#if !defined(CONFIG_LGE_ISA1200) && !defined(CONFIG_ANDROID_VIBRATOR) +/* temporal code due to build error.. */ +#define GPIO_LIN_MOTOR_EN 0 +#define GPIO_LIN_MOTOR_PWM 0 +#endif + +/* Vibrator GPIOs */ +#ifdef CONFIG_ANDROID_VIBRATOR +#define GPIO_LIN_MOTOR_EN 33 +#define GPIO_LIN_MOTOR_PWR 47 +#define GPIO_LIN_MOTOR_PWM 3 + +#define GP_CLK_ID 0 /* gp clk 0 */ +#define GP_CLK_M_DEFAULT 1 +#define GP_CLK_N_DEFAULT 166 +#define GP_CLK_D_MAX GP_CLK_N_DEFAULT +#define GP_CLK_D_HALF (GP_CLK_N_DEFAULT >> 1) + +#define MOTOR_AMP 120 +#endif + +#if defined(CONFIG_LGE_ISA1200) || defined(CONFIG_ANDROID_VIBRATOR) +static struct gpiomux_setting vibrator_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +/* gpio 3 */ +static struct gpiomux_setting vibrator_active_cfg_gpio3 = { + .func = GPIOMUX_FUNC_2, /*gp_mn:2 */ + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config gpio2_vibrator_configs[] = { + { + .gpio = 3, + .settings = { + [GPIOMUX_ACTIVE] = &vibrator_active_cfg_gpio3, + [GPIOMUX_SUSPENDED] = &vibrator_suspend_cfg, + }, + }, +}; + +static int gpio_vibrator_en = 33; +static int gpio_vibrator_pwm = 3; +static int gp_clk_id = 0; + +static int vibrator_gpio_init(void) +{ + gpio_vibrator_en = GPIO_LIN_MOTOR_EN; + gpio_vibrator_pwm = GPIO_LIN_MOTOR_PWM; + return 0; +} +#endif + +#ifdef CONFIG_ANDROID_VIBRATOR +static struct regulator *vreg_l16 = NULL; +static bool snddev_reg_8921_l16_status = false; + +static int vibrator_power_set(int enable) +{ + int rc = -EINVAL; + if (NULL == vreg_l16) { + vreg_l16 = regulator_get(NULL, "8921_l16"); //2.6 ~ 3V + INFO_MSG("enable=%d\n", enable); + + if (IS_ERR(vreg_l16)) { + pr_err("%s: regulator get of 8921_lvs6 failed (%ld)\n" + , __func__, PTR_ERR(vreg_l16)); + printk("woosock ERROR\n"); + rc = PTR_ERR(vreg_l16); + return rc; + } + } + rc = regulator_set_voltage(vreg_l16, 2800000, 2800000); + + if (enable == snddev_reg_8921_l16_status) + return 0; + + if (enable) { + rc = regulator_set_voltage(vreg_l16, 2800000, 2800000); + if (rc < 0) + pr_err("LGE: VIB %s: regulator_set_voltage(l1) failed (%d)\n", + __func__, rc); + + rc = regulator_enable(vreg_l16); + + if (rc < 0) + pr_err("LGE: VIB %s: regulator_enable(l1) failed (%d)\n", __func__, rc); + snddev_reg_8921_l16_status = true; + + } else { + rc = regulator_disable(vreg_l16); + if (rc < 0) + pr_err("%s: regulator_disable(l1) failed (%d)\n", __func__, rc); + snddev_reg_8921_l16_status = false; + } + + return 0; +} + +static int vibrator_pwm_set(int enable, int amp, int n_value) +{ + /* TODO: set clk for amp */ + uint M_VAL = GP_CLK_M_DEFAULT; + uint D_VAL = GP_CLK_D_MAX; + uint D_INV = 0; /* QCT support invert bit for msm8960 */ + uint clk_id = gp_clk_id; + + INFO_MSG("amp=%d, n_value=%d\n", amp, n_value); + + if (enable) { + D_VAL = ((GP_CLK_D_MAX * amp) >> 7); + if (D_VAL > GP_CLK_D_HALF) { + if (D_VAL == GP_CLK_D_MAX) { /* Max duty is 99% */ + D_VAL = 2; + } else { + D_VAL = GP_CLK_D_MAX - D_VAL; + } + D_INV = 1; + } + + REG_WRITEL( + (((M_VAL & 0xffU) << 16U) + /* M_VAL[23:16] */ + ((~(D_VAL << 1)) & 0xffU)), /* D_VAL[7:0] */ + GPn_MD_REG(clk_id)); + + REG_WRITEL( + ((((~(n_value-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */ + (1U << 11U) + /* CLK_ROOT_ENA[11] : Enable(1) */ + ((D_INV & 0x01U) << 10U) + /* CLK_INV[10] : Disable(0) */ + (1U << 9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */ + (1U << 8U) + /* NMCNTR_EN[8] : Enable(1) */ + (0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */ + (2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */ + (3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */ + (5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */ + GPn_NS_REG(clk_id)); + INFO_MSG("GPIO_LIN_MOTOR_PWM is enable with M=%d N=%d D=%d\n", + M_VAL, n_value, D_VAL); + } else { + REG_WRITEL( + ((((~(n_value-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */ + (0U << 11U) + /* CLK_ROOT_ENA[11] : Disable(0) */ + (0U << 10U) + /* CLK_INV[10] : Disable(0) */ + (0U << 9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */ + (0U << 8U) + /* NMCNTR_EN[8] : Disable(0) */ + (0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */ + (2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */ + (3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */ + (5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */ + GPn_NS_REG(clk_id)); + INFO_MSG("GPIO_LIN_MOTOR_PWM is disalbe \n"); + } + + return 0; +} + +static int vibrator_ic_enable_set(int enable) +{ + int gpio_lin_motor_en = 0; + gpio_lin_motor_en = PM8921_GPIO_PM_TO_SYS(GPIO_LIN_MOTOR_EN); + + INFO_MSG("enable=%d\n", enable); + + if (enable) + gpio_direction_output(gpio_lin_motor_en, 1); + else + gpio_direction_output(gpio_lin_motor_en, 0); + + return 0; +} + +static int vibrator_init(void) +{ + int rc; + int gpio_motor_en = 0; + int gpio_motor_pwm = 0; + + gpio_motor_en = gpio_vibrator_en; + gpio_motor_pwm = gpio_vibrator_pwm; + + /* GPIO function setting */ + msm_gpiomux_install(gpio2_vibrator_configs, + ARRAY_SIZE(gpio2_vibrator_configs)); + + /* GPIO setting for Motor EN in pmic8921 */ + gpio_motor_en = PM8921_GPIO_PM_TO_SYS(GPIO_LIN_MOTOR_EN); + rc = gpio_request(gpio_motor_en, "lin_motor_en"); + if (rc) { + ERR_MSG("GPIO_LIN_MOTOR_EN %d request failed\n", gpio_motor_en); + return 0; + } + + /* gpio init */ + rc = gpio_request(gpio_motor_pwm, "lin_motor_pwm"); + if (unlikely(rc < 0)) + ERR_MSG("not able to get gpio\n"); + + vibrator_ic_enable_set(0); + vibrator_pwm_set(0, 0, GP_CLK_N_DEFAULT); + vibrator_power_set(0); + + return 0; +} + + + +static struct android_vibrator_platform_data vibrator_data = { + .enable_status = 0, + .amp = MOTOR_AMP, + .vibe_n_value = GP_CLK_N_DEFAULT, + .power_set = vibrator_power_set, + .pwm_set = vibrator_pwm_set, + .ic_enable_set = vibrator_ic_enable_set, + .vibrator_init = vibrator_init, +}; + +static struct platform_device android_vibrator_device = { + .name = "android-vibrator", + .id = -1, + .dev = { + .platform_data = &vibrator_data, + }, +}; +#endif /* CONFIG_ANDROID_VIBRATOR */ + +#ifdef CONFIG_LGE_ISA1200 +static int lge_isa1200_clock(int enable) +{ + if (enable) { + REG_WRITEL( + (((0 & 0xffU) << 16U) + /* N_VAL[23:16] */ + (1U << 11U) + /* CLK_ROOT_ENA[11] : Enable(1) */ + (0U << 10U) + /* CLK_INV[10] : Disable(0) */ + (1U << 9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */ + (0U << 8U) + /* NMCNTR_EN[8] : Enable(1) */ + (0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */ + (0U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */ + (0U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */ + (0U << 0U)), /* SRC_SEL[2:0] : pxo (0) */ + GPn_NS_REG(1)); + /* printk("GPIO_LIN_MOTOR_PWM is enabled. pxo clock."); */ + } else { + REG_WRITEL( + (((0 & 0xffU) << 16U) + /* N_VAL[23:16] */ + (0U << 11U) + /* CLK_ROOT_ENA[11] : Disable(0) */ + (0U << 10U) + /* CLK_INV[10] : Disable(0) */ + (0U << 9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */ + (0U << 8U) + /* NMCNTR_EN[8] : Disable(0) */ + (1U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */ + (0U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */ + (0U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */ + (0U << 0U)), /* SRC_SEL[2:0] : pxo (0) */ + GPn_NS_REG(1)); + /* printk("GPIO_LIN_MOTOR_PWM is disabled."); */ + } + + return 0; +} + +static struct isa1200_reg_cmd isa1200_init_seq[] = { + + {LGE_ISA1200_HCTRL2, 0x00}, /* bk : release sw reset */ + + {LGE_ISA1200_SCTRL , 0x0F}, /* LDO:3V */ + + {LGE_ISA1200_HCTRL0, 0x10}, /* [4:3]10 : PWM Generation Mode [1:0]00 : Divider 1/128 */ + {LGE_ISA1200_HCTRL1, 0xC0}, /* [7] 1 : Ext. Clock Selection, [5] 0:LRA, 1:ERM */ + {LGE_ISA1200_HCTRL3, 0x33}, /* [6:4] 1:PWM/SE Generation PLL Clock Divider */ + + {LGE_ISA1200_HCTRL4, 0x81}, /* bk */ + {LGE_ISA1200_HCTRL5, 0x99}, /* [7:0] PWM High Duty(PWM Gen) 0-6B-D6 */ /* TODO make it platform data? */ + {LGE_ISA1200_HCTRL6, 0x9C}, /* [7:0] PWM Period(PWM Gen) */ /* TODO make it platform data? */ + +}; + +static struct isa1200_reg_seq isa1200_init = { + .reg_cmd_list = isa1200_init_seq, + .number_of_reg_cmd_list = ARRAY_SIZE(isa1200_init_seq), +}; + +static struct lge_isa1200_platform_data lge_isa1200_platform_data = { + .vibrator_name = "vibrator", + + .gpio_hen = GPIO_MOTOR_EN, + .gpio_len = GPIO_MOTOR_EN, + + .clock = lge_isa1200_clock, + .max_timeout = 30000, + .default_vib_strength = 255, /* max strength value is 255 */ + .init_seq = &isa1200_init, +}; + +static struct i2c_board_info lge_i2c_isa1200_board_info[] = { + { + I2C_BOARD_INFO("lge_isa1200", ISA1200_SLAVE_ADDR>>1), + .platform_data = &lge_isa1200_platform_data + }, +}; +#endif + +#if defined(CONFIG_LGE_ISA1200) || defined(CONFIG_ANDROID_VIBRATOR) +static struct platform_device *misc_devices[] __initdata = { +#ifdef CONFIG_ANDROID_VIBRATOR + &android_vibrator_device, +#endif +}; +#endif + +#if defined(CONFIG_SII8334_MHL_TX) + +#define MHL_RESET_N 31 +#define MHL_INT_N 43 + +static int mhl_gpio_init(void) +{ + int rc; + + rc = gpio_request(MHL_INT_N, "mhl_int_n"); + if (rc < 0) { + pr_err("failed to request mhl_int_n gpio\n"); + goto error1; + } + gpio_export(MHL_INT_N, 1); + + rc = gpio_request(MHL_RESET_N, "mhl_reset_n"); + if (rc < 0) { + pr_err("failed to request mhl_reset_n gpio\n"); + goto error2; + } + + rc = gpio_direction_output(MHL_RESET_N, 0); + if (rc < 0) { + pr_err("failed to request mhl_reset_n gpio\n"); + goto error3; + } + +error3: + gpio_free(MHL_RESET_N); +error2: + gpio_free(MHL_INT_N); +error1: + + return rc; +} + +static struct regulator *vreg_l18_mhl; + +static int mhl_power_onoff(bool on, bool pm_ctrl) +{ + static bool power_state=0; + int rc = 0; + + if (power_state == on) { + pr_info("sii_power_state is already %s \n", + power_state ? "on" : "off"); + return rc; + } + power_state = on; + + if (!vreg_l18_mhl) + vreg_l18_mhl = regulator_get(NULL, "8921_l18"); + + if (IS_ERR(vreg_l18_mhl)) { + rc = PTR_ERR(vreg_l18_mhl); + pr_err("%s: vreg_l18_mhl get failed (%d)\n", __func__, rc); + return rc; + } + + if (on) { + + gpio_set_value(MHL_RESET_N, 0); + + rc = regulator_set_optimum_mode(vreg_l18_mhl, 100000); + if (rc < 0) { + pr_err("%s : set optimum mode 100000,\ + vreg_l18_mhl failed (%d)\n", + __func__, rc); + return -EINVAL; + } + + rc = regulator_set_voltage(vreg_l18_mhl, 1200000, 1200000); + if (rc < 0) { + pr_err("%s : set voltage 1200000,\ + vreg_l18_mhl failed (%d)\n", + __func__, rc); + return -EINVAL; + } + + rc = regulator_enable(vreg_l18_mhl); + if (rc) { + pr_err("%s : vreg_l18_mhl enable failed (%d)\n", + __func__, rc); + return rc; + } + + msleep(100); + gpio_set_value(MHL_RESET_N, 1); + + } + else { + rc = regulator_set_optimum_mode(vreg_l18_mhl, 100); + if (rc < 0) { + pr_err("%s : set optimum mode 100,\ + vreg_l18_mhl failed (%d)\n", + __func__, rc); + return -EINVAL; + } + + rc = regulator_disable(vreg_l18_mhl); + if (rc) { + pr_err("%s : vreg_l18_mhl disable failed (%d)\n", + __func__, rc); + return rc; + } + + gpio_set_value(MHL_RESET_N, 0); + } + + return rc; +} + +static struct mhl_platform_data mhl_pdata = { + .power = mhl_power_onoff, +}; + + +#define I2C_SURF 1 +#define I2C_FFA (1 << 1) +#define I2C_RUMI (1 << 2) +#define I2C_SIM (1 << 3) +#define I2C_LIQUID (1 << 4) +#define I2C_J1V (1 << 5) + +struct i2c_registry { + u8 machs; + int bus; + struct i2c_board_info *info; + int len; +}; + +struct i2c_board_info i2c_mhl_info[] = { + { + I2C_BOARD_INFO("Sil-833x", 0x72 >> 1), /* 0x39 */ + .irq = MSM_GPIO_TO_INT(MHL_INT_N), + .platform_data = &mhl_pdata, + }, + { + I2C_BOARD_INFO("Sil-833x", 0x7A >> 1), /* 0x3D */ + }, + { + I2C_BOARD_INFO("Sil-833x", 0x92 >> 1), /* 0x49 */ + }, + { + I2C_BOARD_INFO("Sil-833x", 0x9A >> 1), /* 0x4D */ + }, + { + I2C_BOARD_INFO("Sil-833x", 0xC8 >> 1), /* 0x64 */ + }, +}; + +static struct i2c_registry i2c_mhl_devices __initdata = { + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + i2c_mhl_info, + ARRAY_SIZE(i2c_mhl_info), +}; + +static void __init lge_add_i2c_mhl_device(void) +{ + i2c_register_board_info(i2c_mhl_devices.bus, + i2c_mhl_devices.info, + i2c_mhl_devices.len); +} + +#endif /* CONFIG_SII8334_MHL_TX */ + +#ifdef CONFIG_BU52031NVX +#define GPIO_POUCH_INT 22 +#define GPIO_CARKIT_INT 23 + +static unsigned hall_ic_int_gpio[] = {GPIO_POUCH_INT, GPIO_CARKIT_INT}; + +static unsigned hall_ic_gpio[] = { + GPIO_CFG(22, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), + GPIO_CFG(23, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), +}; + +static void __init hall_ic_init(void) +{ + int rc = 0; + int i = 0; + + printk(KERN_INFO "%s, line: %d\n", __func__, __LINE__); + + rc = gpio_request(GPIO_POUCH_INT, "cradle_detect_s"); + if (rc) { + printk(KERN_ERR "%s: pouch_int %d request failed\n", + __func__, GPIO_POUCH_INT); + return; + } + + rc = gpio_request(GPIO_CARKIT_INT, "cradle_detect_n"); + if (rc) { + printk(KERN_ERR "%s: pouch_int %d request failed\n", + __func__, GPIO_CARKIT_INT); + return; + } + + for (i=0; i +#include +#include +#include +#include +#include +#include "devices.h" + +#include "board-mako.h" +#include "board-8064.h" + +#if defined(CONFIG_LGE_NFC_PN544) +#include + +#define I2C_SURF 1 +#define I2C_FFA (1 << 1) +#define I2C_RUMI (1 << 2) +#define I2C_SIM (1 << 3) +#define I2C_LIQUID (1 << 4) +#define I2C_J1V (1 << 5) + +struct i2c_registry { + u8 machs; + int bus; + struct i2c_board_info *info; + int len; +}; + +typedef void (gpio_i2c_init_func_t)(int bus_num); + +static struct pn544_i2c_platform_data pn544_i2c_platform_data[] = { + { + .ven_gpio = NFC_GPIO_VEN, + .irq_gpio = NFC_GPIO_IRQ, + .firm_gpio = NFC_GPIO_FIRM, + }, +}; + +static struct i2c_board_info msm_i2c_nxp_nfc_info[] = { + { + I2C_BOARD_INFO("pn544", NFC_I2C_SLAVE_ADDR), + .platform_data = &pn544_i2c_platform_data, + .irq = MSM_GPIO_TO_INT(NFC_GPIO_IRQ), + } +}; + +static struct i2c_registry apq8064_i2c_devices __initdata = { + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + msm_i2c_nxp_nfc_info, + ARRAY_SIZE(msm_i2c_nxp_nfc_info), +}; + +static void __init lge_add_i2c_nfc_devices(void) +{ + i2c_register_board_info(apq8064_i2c_devices.bus, + apq8064_i2c_devices.info, + apq8064_i2c_devices.len); +} + +void __init lge_add_nfc_devices(void) +{ + lge_add_i2c_nfc_devices(); +} +#endif diff --git a/arch/arm/mach-msm/lge/mako/board-mako-pmic.c b/arch/arm/mach-msm/lge/mako/board-mako-pmic.c new file mode 100644 index 000000000000..4b30a5602558 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-pmic.c @@ -0,0 +1,578 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" +#include "board-mako.h" + +struct pm8xxx_gpio_init { + unsigned gpio; + struct pm_gpio config; +}; + +struct pm8xxx_mpp_init { + unsigned mpp; + struct pm8xxx_mpp_config_data config; +}; + +#define PM8921_GPIO_INIT(_gpio, _dir, _buf, _val, _pull, _vin, _out_strength, \ + _func, _inv, _disable) \ +{ \ + .gpio = PM8921_GPIO_PM_TO_SYS(_gpio), \ + .config = { \ + .direction = _dir, \ + .output_buffer = _buf, \ + .output_value = _val, \ + .pull = _pull, \ + .vin_sel = _vin, \ + .out_strength = _out_strength, \ + .function = _func, \ + .inv_int_pol = _inv, \ + .disable_pin = _disable, \ + } \ +} + +#define PM8921_MPP_INIT(_mpp, _type, _level, _control) \ +{ \ + .mpp = PM8921_MPP_PM_TO_SYS(_mpp), \ + .config = { \ + .type = PM8XXX_MPP_TYPE_##_type, \ + .level = _level, \ + .control = PM8XXX_MPP_##_control, \ + } \ +} + +#define PM8821_MPP_INIT(_mpp, _type, _level, _control) \ +{ \ + .mpp = PM8821_MPP_PM_TO_SYS(_mpp), \ + .config = { \ + .type = PM8XXX_MPP_TYPE_##_type, \ + .level = _level, \ + .control = PM8XXX_MPP_##_control, \ + } \ +} + +#define PM8921_GPIO_DISABLE(_gpio) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, 0, 0, 0, PM_GPIO_VIN_S4, \ + 0, 0, 0, 1) + +#define PM8921_GPIO_OUTPUT(_gpio, _val, _strength) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \ + PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \ + PM_GPIO_STRENGTH_##_strength, \ + PM_GPIO_FUNC_NORMAL, 0, 0) + +#define PM8921_GPIO_OUTPUT_BUFCONF(_gpio, _val, _strength, _bufconf) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT,\ + PM_GPIO_OUT_BUF_##_bufconf, _val, \ + PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \ + PM_GPIO_STRENGTH_##_strength, \ + PM_GPIO_FUNC_NORMAL, 0, 0) + +#define PM8921_GPIO_INPUT(_gpio, _pull) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, PM_GPIO_OUT_BUF_CMOS, 0, \ + _pull, PM_GPIO_VIN_S4, \ + PM_GPIO_STRENGTH_NO, \ + PM_GPIO_FUNC_NORMAL, 0, 0) + +#define PM8921_GPIO_OUTPUT_FUNC(_gpio, _val, _func) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \ + PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \ + PM_GPIO_STRENGTH_HIGH, \ + _func, 0, 0) + +#define PM8921_GPIO_OUTPUT_VIN(_gpio, _val, _vin) \ + PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \ + PM_GPIO_PULL_NO, _vin, \ + PM_GPIO_STRENGTH_HIGH, \ + PM_GPIO_FUNC_NORMAL, 0, 0) + +#ifdef CONFIG_LGE_PM +/* Initial PM8921 GPIO configurations */ +static struct pm8xxx_gpio_init pm8921_gpios[] __initdata = { + PM8921_GPIO_OUTPUT(17, 0, HIGH), /* CAM_VCM_EN */ + PM8921_GPIO_OUTPUT(19, 0, HIGH), /* AMP_EN_AMP */ + PM8921_GPIO_OUTPUT(31, 0, HIGH), /* PMIC - FSA8008_EAR_MIC_EN */ + PM8921_GPIO_INPUT(32, PM_GPIO_PULL_UP_1P5), /* PMIC - FSA8008_EARPOL_DETECT */ + PM8921_GPIO_OUTPUT(33, 0, HIGH), /* HAPTIC_EN */ + PM8921_GPIO_OUTPUT(34, 0, HIGH), /* WCD_RESET_N */ +}; +#else +/* Initial PM8921 GPIO configurations */ +static struct pm8xxx_gpio_init pm8921_gpios[] __initdata = { + PM8921_GPIO_OUTPUT(14, 1, HIGH), /* HDMI Mux Selector */ + PM8921_GPIO_OUTPUT(23, 0, HIGH), /* touchscreen power FET */ + PM8921_GPIO_OUTPUT_BUFCONF(25, 0, LOW, CMOS), /* DISP_RESET_N */ + PM8921_GPIO_OUTPUT_FUNC(26, 0, PM_GPIO_FUNC_2), /* Bl: Off, PWM mode */ + PM8921_GPIO_OUTPUT_VIN(30, 1, PM_GPIO_VIN_VPH), /* SMB349 susp line */ + PM8921_GPIO_OUTPUT_BUFCONF(36, 1, LOW, OPEN_DRAIN), + PM8921_GPIO_OUTPUT_FUNC(44, 0, PM_GPIO_FUNC_2), + PM8921_GPIO_OUTPUT(33, 0, HIGH), + PM8921_GPIO_OUTPUT(20, 0, HIGH), + PM8921_GPIO_INPUT(35, PM_GPIO_PULL_UP_30), + PM8921_GPIO_INPUT(38, PM_GPIO_PULL_UP_30), + /* TABLA CODEC RESET */ + PM8921_GPIO_OUTPUT(34, 1, MED), + PM8921_GPIO_INPUT(31, PM_GPIO_PULL_NO), + PM8921_GPIO_OUTPUT(13, 0, HIGH), /* PCIE_CLK_PWR_EN */ +}; +#endif + +#ifndef CONFIG_LGE_PM +static struct pm8xxx_gpio_init pm8921_mtp_kp_gpios[] __initdata = { + PM8921_GPIO_INPUT(3, PM_GPIO_PULL_UP_30), + PM8921_GPIO_INPUT(4, PM_GPIO_PULL_UP_30), +}; + +static struct pm8xxx_gpio_init pm8921_cdp_kp_gpios[] __initdata = { + PM8921_GPIO_INPUT(27, PM_GPIO_PULL_UP_30), + PM8921_GPIO_INPUT(42, PM_GPIO_PULL_UP_30), + PM8921_GPIO_INPUT(17, PM_GPIO_PULL_UP_1P5), /* SD_WP */ +}; + +/* Initial PM8XXX MPP configurations */ +static struct pm8xxx_mpp_init pm8xxx_mpps[] __initdata = { + PM8921_MPP_INIT(3, D_OUTPUT, PM8921_MPP_DIG_LEVEL_VPH, DOUT_CTRL_LOW), + PM8921_MPP_INIT(8, D_OUTPUT, PM8921_MPP_DIG_LEVEL_S4, DOUT_CTRL_LOW), + /*MPP9 is used to detect docking station connection/removal on Liquid*/ + PM8921_MPP_INIT(9, D_INPUT, PM8921_MPP_DIG_LEVEL_S4, DIN_TO_INT), + /* PCIE_RESET_N */ + PM8921_MPP_INIT(1, D_OUTPUT, PM8921_MPP_DIG_LEVEL_VPH, DOUT_CTRL_HIGH), +}; +#endif + +void __init apq8064_pm8xxx_gpio_mpp_init(void) +{ + int i, rc; + + for (i = 0; i < ARRAY_SIZE(pm8921_gpios); i++) { + rc = pm8xxx_gpio_config(pm8921_gpios[i].gpio, + &pm8921_gpios[i].config); + if (rc) { + pr_err("%s: pm8xxx_gpio_config: rc=%d\n", __func__, rc); + break; + } + } +#ifndef CONFIG_LGE_PM + if (machine_is_apq8064_cdp() || machine_is_apq8064_liquid()) + for (i = 0; i < ARRAY_SIZE(pm8921_cdp_kp_gpios); i++) { + rc = pm8xxx_gpio_config(pm8921_cdp_kp_gpios[i].gpio, + &pm8921_cdp_kp_gpios[i].config); + if (rc) { + pr_err("%s: pm8xxx_gpio_config: rc=%d\n", + __func__, rc); + break; + } + } + + if (machine_is_apq8064_mtp()) + for (i = 0; i < ARRAY_SIZE(pm8921_mtp_kp_gpios); i++) { + rc = pm8xxx_gpio_config(pm8921_mtp_kp_gpios[i].gpio, + &pm8921_mtp_kp_gpios[i].config); + if (rc) { + pr_err("%s: pm8xxx_gpio_config: rc=%d\n", + __func__, rc); + break; + } + } + + for (i = 0; i < ARRAY_SIZE(pm8xxx_mpps); i++) { + rc = pm8xxx_mpp_config(pm8xxx_mpps[i].mpp, + &pm8xxx_mpps[i].config); + if (rc) { + pr_err("%s: pm8xxx_mpp_config: rc=%d\n", __func__, rc); + break; + } + } +#endif +} + +static struct pm8xxx_pwrkey_platform_data apq8064_pm8921_pwrkey_pdata = { + .pull_up = 1, + .kpd_trigger_delay_us = 15625, + .wakeup = 1, +}; + +static struct pm8xxx_misc_platform_data apq8064_pm8921_misc_pdata = { + .priority = 0, +}; + +#define PM8921_LC_LED_MAX_CURRENT 4 /* I = 4mA */ +#define PM8921_LC_LED_LOW_CURRENT 1 /* I = 1mA */ +#define PM8XXX_LED_PWM_PERIOD 1000 +#define PM8XXX_LED_PWM_DUTY_MS 20 +/** + * PM8XXX_PWM_CHANNEL_NONE shall be used when LED shall not be + * driven using PWM feature. + */ +#define PM8XXX_PWM_CHANNEL_NONE -1 + +static struct led_info pm8921_led_info[] = { +#if defined(CONFIG_LGE_PM) + [0] = { + .name = "led:red", + }, +#else + + [0] = { + .name = "led:red", + .default_trigger = "ac-online", + }, +#endif + [1] = { + .name = "button-backlight", + }, +}; + +static struct led_platform_data pm8921_led_core_pdata = { + .num_leds = ARRAY_SIZE(pm8921_led_info), + .leds = pm8921_led_info, +}; + +#if !defined(CONFIG_LGE_PM) +static int pm8921_led0_pwm_duty_pcts[56] = { + 1, 4, 8, 12, 16, 20, 24, 28, 32, 36, + 40, 44, 46, 52, 56, 60, 64, 68, 72, 76, + 80, 84, 88, 92, 96, 100, 100, 100, 98, 95, + 92, 88, 84, 82, 78, 74, 70, 66, 62, 58, + 58, 54, 50, 48, 42, 38, 34, 30, 26, 22, + 14, 10, 6, 4, 1 +}; + +static struct pm8xxx_pwm_duty_cycles pm8921_led0_pwm_duty_cycles = { + .duty_pcts = (int *)&pm8921_led0_pwm_duty_pcts, + .num_duty_pcts = ARRAY_SIZE(pm8921_led0_pwm_duty_pcts), + .duty_ms = PM8XXX_LED_PWM_DUTY_MS, + .start_idx = 0, +}; +#endif + +static struct pm8xxx_led_config pm8921_led_configs[] = { +#if defined(CONFIG_LGE_PM) + [0] = { + .id = PM8XXX_ID_LED_0, + .mode = PM8XXX_LED_MODE_MANUAL, + .max_current = PM8921_LC_LED_MAX_CURRENT, + }, +#else + [0] = { + .id = PM8XXX_ID_LED_0, + .mode = PM8XXX_LED_MODE_PWM2, + .max_current = PM8921_LC_LED_MAX_CURRENT, + .pwm_channel = 5, + .pwm_period_us = PM8XXX_LED_PWM_PERIOD, + .pwm_duty_cycles = &pm8921_led0_pwm_duty_cycles, + }, +#endif + [1] = { + .id = PM8XXX_ID_LED_1, + .mode = PM8XXX_LED_MODE_MANUAL, + .max_current = PM8921_LC_LED_MAX_CURRENT, + + }, +}; + +static struct pm8xxx_led_platform_data apq8064_pm8921_leds_pdata = { + .led_core = &pm8921_led_core_pdata, + .configs = pm8921_led_configs, + .num_configs = ARRAY_SIZE(pm8921_led_configs), +}; + +static struct pm8xxx_adc_amux apq8064_pm8921_adc_channels_data[] = { + {"vcoin", CHANNEL_VCOIN, CHAN_PATH_SCALING2, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"vbat", CHANNEL_VBAT, CHAN_PATH_SCALING2, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"dcin", CHANNEL_DCIN, CHAN_PATH_SCALING4, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"ichg", CHANNEL_ICHG, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"vph_pwr", CHANNEL_VPH_PWR, CHAN_PATH_SCALING2, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"ibat", CHANNEL_IBAT, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"batt_therm", CHANNEL_BATT_THERM, CHAN_PATH_SCALING1, AMUX_RSV2, + ADC_DECIMATION_TYPE2, ADC_SCALE_BATT_THERM}, + {"batt_id", CHANNEL_BATT_ID, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"usbin", CHANNEL_USBIN, CHAN_PATH_SCALING3, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"pmic_therm", CHANNEL_DIE_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_PMIC_THERM}, + {"625mv", CHANNEL_625MV, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"125v", CHANNEL_125V, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"chg_temp", CHANNEL_CHG_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, + {"xo_therm", CHANNEL_MUXOFF, CHAN_PATH_SCALING1, AMUX_RSV0, + ADC_DECIMATION_TYPE2, ADC_SCALE_XOTHERM}, +#ifdef CONFIG_LGE_PM + {"usb_id", ADC_MPP_1_AMUX6, CHAN_PATH_SCALING1, AMUX_RSV1, + ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT}, +#endif +}; + +static struct pm8xxx_adc_properties apq8064_pm8921_adc_data = { + .adc_vdd_reference = 1800, /* milli-voltage for this adc */ + .bitresolution = 15, + .bipolar = 0, +}; + +static struct pm8xxx_adc_platform_data apq8064_pm8921_adc_pdata = { + .adc_channel = apq8064_pm8921_adc_channels_data, + .adc_num_board_channel = ARRAY_SIZE(apq8064_pm8921_adc_channels_data), + .adc_prop = &apq8064_pm8921_adc_data, + .adc_mpp_base = PM8921_MPP_PM_TO_SYS(1), +}; + +static struct pm8xxx_mpp_platform_data +apq8064_pm8921_mpp_pdata __devinitdata = { + .mpp_base = PM8921_MPP_PM_TO_SYS(1), +}; + +static struct pm8xxx_gpio_platform_data +apq8064_pm8921_gpio_pdata __devinitdata = { + .gpio_base = PM8921_GPIO_PM_TO_SYS(1), +}; + +static struct pm8xxx_irq_platform_data +apq8064_pm8921_irq_pdata __devinitdata = { + .irq_base = PM8921_IRQ_BASE, + .devirq = MSM_GPIO_TO_INT(74), + .irq_trigger_flag = IRQF_TRIGGER_LOW, + .dev_id = 0, +}; + +static struct pm8xxx_rtc_platform_data +apq8064_pm8921_rtc_pdata = { + .rtc_write_enable = false, + .rtc_alarm_powerup = false, +}; + +static int apq8064_pm8921_therm_mitigation[] = { + 1100, + 700, + 600, + 325, +}; + +#if (defined(CONFIG_LGE_PM) && defined(CONFIG_LGE_PM_435V_BATT)) +/* + * J1 battery characteristic + * Typ.1900mAh capacity, Li-Ion Polymer 3.8V + * Battery/VDD voltage programmable range, 20mV steps. + * it will be changed in future + */ +#define MAX_VOLTAGE_MV 4360 + +static struct pm8921_charger_platform_data apq8064_pm8921_chg_pdata __devinitdata = { + + /* max charging time in minutes incl. fast and trkl. it will be changed in future */ + .safety_time = 512, /* 300 change max value for charging time */ + .update_time = 60000, + .max_voltage = MAX_VOLTAGE_MV, + + /* the voltage (mV) where charging method switches from trickle to fast. + * This is also the minimum voltage the system operates at */ + .min_voltage = 3200, + /* the (mV) drop to wait for before resume charging after the battery has been fully charged */ + .resume_voltage_delta = 50, + .term_current = 100, + +#ifdef CONFIG_LGE_CHARGER_TEMP_SCENARIO + /* Configuration of cool and warm thresholds (JEITA compliance only) */ + .cool_temp = 0, /* 10 */ /* 10 degree celsius */ + .warm_temp = 0, /* 40 */ /* 40 degree celsius */ + .cool_bat_chg_current = 350, /* 350 mA (max value = 2A) */ + .warm_bat_chg_current = 350, + .temp_level_1 = 550, + .temp_level_2 = 450, + .temp_level_3 = 420, + .temp_level_4 = -50, + .temp_level_5 = -100, + /* Temperature Thresholds (JEITA compliance) (-10'C ~ 60'C) */ + .cold_thr = 1, /* 80% */ + .hot_thr = 0, /* 20% */ +#else /* qualcomm original value */ + .cool_temp = 10, + .warm_temp = 40, + .cool_bat_chg_current = 350, + .warm_bat_chg_current = 350, +#endif + + .temp_check_period = 1, + + /* Battery charge current programmable range 50mA steps */ + /* max_bat_chg_current: + * Max charge current of the battery in mA + * Usually 70% of full charge capacity + */ + .max_bat_chg_current = 1350, + + .cool_bat_voltage = 4100, + .warm_bat_voltage = 4100, + .thermal_mitigation = apq8064_pm8921_therm_mitigation, + .thermal_levels = ARRAY_SIZE(apq8064_pm8921_therm_mitigation), + /* for led on, off control */ + .led_src_config = LED_SRC_MIN_VPH_5V, +}; +#else /* qualcomm original code */ +#define MAX_VOLTAGE_MV 4200 +static struct pm8921_charger_platform_data +apq8064_pm8921_chg_pdata __devinitdata = { + .safety_time = 180, + .update_time = 60000, + .max_voltage = MAX_VOLTAGE_MV, + .min_voltage = 3200, + .resume_voltage_delta = 100, + .term_current = 100, + .cool_temp = 10, + .warm_temp = 40, + .temp_check_period = 1, + .max_bat_chg_current = 1100, + .cool_bat_chg_current = 350, + .warm_bat_chg_current = 350, + .cool_bat_voltage = 4100, + .warm_bat_voltage = 4100, + .thermal_mitigation = apq8064_pm8921_therm_mitigation, + .thermal_levels = ARRAY_SIZE(apq8064_pm8921_therm_mitigation), +}; +#endif + +static struct pm8xxx_ccadc_platform_data +apq8064_pm8xxx_ccadc_pdata = { + .r_sense = 10, +}; + +static struct pm8921_bms_platform_data +apq8064_pm8921_bms_pdata __devinitdata = { +#ifdef CONFIG_LGE_PM + .battery_type = BATT_G_LGE, +#else + .battery_type = BATT_UNKNOWN, +#endif + .r_sense = 10, + .i_test = 834, + .v_failure = 3300, + .calib_delay_ms = 600000, + .max_voltage_uv = MAX_VOLTAGE_MV * 1000, +}; + +#ifdef CONFIG_LGE_PM +static unsigned int keymap[] = { + KEY(0, 0, KEY_VOLUMEUP), + KEY(0, 1, KEY_VOLUMEDOWN), +}; + +static struct matrix_keymap_data keymap_data = { + .keymap_size = ARRAY_SIZE(keymap), + .keymap = keymap, +}; + +static struct pm8xxx_keypad_platform_data keypad_data = { + .input_name = "keypad_8064", + .input_phys_device = "keypad_8064/input0", + .num_rows = 1, + .num_cols = 5, + .rows_gpio_start = PM8921_GPIO_PM_TO_SYS(9), + .cols_gpio_start = PM8921_GPIO_PM_TO_SYS(1), + .debounce_ms = 15, + .scan_delay_ms = 32, + .row_hold_ns = 91500, + .wakeup = 1, + .keymap_data = &keymap_data, +}; +#endif + +static struct pm8921_platform_data +apq8064_pm8921_platform_data __devinitdata = { + .regulator_pdatas = msm8064_pm8921_regulator_pdata, + .irq_pdata = &apq8064_pm8921_irq_pdata, + .gpio_pdata = &apq8064_pm8921_gpio_pdata, + .mpp_pdata = &apq8064_pm8921_mpp_pdata, + .rtc_pdata = &apq8064_pm8921_rtc_pdata, + .pwrkey_pdata = &apq8064_pm8921_pwrkey_pdata, +#ifdef CONFIG_LGE_PM + .keypad_pdata = &keypad_data, +#endif + .misc_pdata = &apq8064_pm8921_misc_pdata, + .leds_pdata = &apq8064_pm8921_leds_pdata, + .adc_pdata = &apq8064_pm8921_adc_pdata, + .charger_pdata = &apq8064_pm8921_chg_pdata, + .bms_pdata = &apq8064_pm8921_bms_pdata, + .ccadc_pdata = &apq8064_pm8xxx_ccadc_pdata, +}; + +static struct pm8xxx_irq_platform_data +apq8064_pm8821_irq_pdata __devinitdata = { + .irq_base = PM8821_IRQ_BASE, + .devirq = PM8821_SEC_IRQ_N, + .irq_trigger_flag = IRQF_TRIGGER_HIGH, + .dev_id = 1, +}; + +static struct pm8xxx_mpp_platform_data +apq8064_pm8821_mpp_pdata __devinitdata = { + .mpp_base = PM8821_MPP_PM_TO_SYS(1), +}; + +static struct pm8821_platform_data +apq8064_pm8821_platform_data __devinitdata = { + .irq_pdata = &apq8064_pm8821_irq_pdata, + .mpp_pdata = &apq8064_pm8821_mpp_pdata, +}; + +static struct msm_ssbi_platform_data apq8064_ssbi_pm8921_pdata __devinitdata = { + .controller_type = MSM_SBI_CTRL_PMIC_ARBITER, + .slave = { + .name = "pm8921-core", + .platform_data = &apq8064_pm8921_platform_data, + }, +}; + +static struct msm_ssbi_platform_data apq8064_ssbi_pm8821_pdata __devinitdata = { + .controller_type = MSM_SBI_CTRL_PMIC_ARBITER, + .slave = { + .name = "pm8821-core", + .platform_data = &apq8064_pm8821_platform_data, + }, +}; + +void __init apq8064_init_pmic(void) +{ + pmic_reset_irq = PM8921_IRQ_BASE + PM8921_RESOUT_IRQ; + + apq8064_device_ssbi_pmic1.dev.platform_data = + &apq8064_ssbi_pm8921_pdata; + apq8064_device_ssbi_pmic2.dev.platform_data = + &apq8064_ssbi_pm8821_pdata; + apq8064_pm8921_platform_data.num_regulators = + msm8064_pm8921_regulator_pdata_len; +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-regulator.c b/arch/arm/mach-msm/lge/mako/board-mako-regulator.c new file mode 100644 index 000000000000..3f32bf2597a0 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-regulator.c @@ -0,0 +1,598 @@ +/* + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "board-mako.h" + +#define VREG_CONSUMERS(_id) \ + static struct regulator_consumer_supply vreg_consumers_##_id[] + +/* + * Consumer specific regulator names: + * regulator name consumer dev_name + */ +VREG_CONSUMERS(L1) = { + REGULATOR_SUPPLY("8921_l1", NULL), +}; +VREG_CONSUMERS(L2) = { + REGULATOR_SUPPLY("8921_l2", NULL), + REGULATOR_SUPPLY("dsi_vdda", "mipi_dsi.1"), + REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.0"), + REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.1"), +}; +VREG_CONSUMERS(L3) = { + REGULATOR_SUPPLY("8921_l3", NULL), + REGULATOR_SUPPLY("HSUSB_3p3", "msm_otg"), + REGULATOR_SUPPLY("HSUSB_3p3", "msm_ehci_host.0"), + REGULATOR_SUPPLY("HSUSB_3p3", "msm_ehci_host.1"), +}; +VREG_CONSUMERS(L4) = { + REGULATOR_SUPPLY("8921_l4", NULL), + REGULATOR_SUPPLY("HSUSB_1p8", "msm_otg"), + REGULATOR_SUPPLY("iris_vddxo", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(L5) = { + REGULATOR_SUPPLY("8921_l5", NULL), + REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.1"), +}; +VREG_CONSUMERS(L6) = { + REGULATOR_SUPPLY("8921_l6", NULL), + REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.3"), +}; +VREG_CONSUMERS(L7) = { + REGULATOR_SUPPLY("8921_l7", NULL), + REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.3"), +}; +VREG_CONSUMERS(L8) = { + REGULATOR_SUPPLY("8921_l8", NULL), + REGULATOR_SUPPLY("cam_vana", "4-001a"), + REGULATOR_SUPPLY("cam_vana", "4-0048"), + REGULATOR_SUPPLY("cam_vana", "4-006c"), + REGULATOR_SUPPLY("cam_vana", "4-0034"), + REGULATOR_SUPPLY("cam_vana", "4-0020"), + REGULATOR_SUPPLY("dsi_vci", "mipi_dsi.1"), +}; +VREG_CONSUMERS(L9) = { + REGULATOR_SUPPLY("8921_l9", NULL), + REGULATOR_SUPPLY("vdd", "3-0024"), +}; +VREG_CONSUMERS(L10) = { + REGULATOR_SUPPLY("8921_l10", NULL), + REGULATOR_SUPPLY("iris_vddpa", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(L11) = { + REGULATOR_SUPPLY("8921_l11", NULL), + REGULATOR_SUPPLY("dsi1_avdd", "mipi_dsi.1"), + REGULATOR_SUPPLY("cam1_vana", "4-000d"), /* GSBI4, Slave Addr: 0x0d, imx111 */ + REGULATOR_SUPPLY("cam2_vana", "4-006e"), /* GSBI4, Slave Addr: 0x6e, imx119 */ +}; +VREG_CONSUMERS(L12) = { + REGULATOR_SUPPLY("cam1_vdig", "4-000d"), /* GSBI4, Slave Addr: 0x0d, imx111 */ + REGULATOR_SUPPLY("cam2_vdig", "4-006e"), /* GSBI4, Slave Addr: 0x6e, imx119 */ + REGULATOR_SUPPLY("8921_l12", NULL), +}; +VREG_CONSUMERS(L14) = { + REGULATOR_SUPPLY("8921_l14", NULL), + REGULATOR_SUPPLY("pa_therm", "pm8xxx-adc"), +}; +VREG_CONSUMERS(L15) = { + REGULATOR_SUPPLY("8921_l15", NULL), +}; +VREG_CONSUMERS(L16) = { + REGULATOR_SUPPLY("8921_l16", NULL), + REGULATOR_SUPPLY("cam_vaf", "4-001a"), + REGULATOR_SUPPLY("cam_vaf", "4-0048"), + REGULATOR_SUPPLY("cam_vaf", "4-006c"), + REGULATOR_SUPPLY("cam_vaf", "4-0034"), + REGULATOR_SUPPLY("cam_vaf", "4-0020"), +}; +VREG_CONSUMERS(L17) = { + REGULATOR_SUPPLY("8921_l17", NULL), +#if defined(CONFIG_IMX111) + REGULATOR_SUPPLY("cam1_vaf", "4-000d"), /* GSBI4, Slave Addr: 0x0d, imx111 */ +#endif +}; +VREG_CONSUMERS(L18) = { + REGULATOR_SUPPLY("8921_l18", NULL), +}; + +/* Power setting for 13M AF */ +#if defined(CONFIG_IMX091) +VREG_CONSUMERS(L21) = { + REGULATOR_SUPPLY("8921_l21", NULL), + REGULATOR_SUPPLY("cam1_vaf", "4-000d"), /* GSBI4, Slave Addr: 0x0d, imx091 */ +}; +#else +VREG_CONSUMERS(L21) = { + REGULATOR_SUPPLY("8921_l21", NULL), +}; +#endif + +VREG_CONSUMERS(L22) = { + REGULATOR_SUPPLY("8921_l22", NULL), +}; +VREG_CONSUMERS(L23) = { + REGULATOR_SUPPLY("8921_l23", NULL), + REGULATOR_SUPPLY("dsi_vddio", "mipi_dsi.1"), + REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.1"), + REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.2"), + REGULATOR_SUPPLY("HSUSB_1p8", "msm_ehci_host.0"), + REGULATOR_SUPPLY("HSUSB_1p8", "msm_ehci_host.1"), +}; +VREG_CONSUMERS(L24) = { + REGULATOR_SUPPLY("8921_l24", NULL), + REGULATOR_SUPPLY("riva_vddmx", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(L25) = { + REGULATOR_SUPPLY("8921_l25", NULL), + REGULATOR_SUPPLY("VDDD_CDC_D", "tabla-slim"), + REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla-slim"), + REGULATOR_SUPPLY("VDDD_CDC_D", "tabla2x-slim"), + REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla2x-slim"), +}; +VREG_CONSUMERS(L26) = { + REGULATOR_SUPPLY("8921_l26", NULL), + REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.0"), +}; +VREG_CONSUMERS(L27) = { + REGULATOR_SUPPLY("8921_l27", NULL), + REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.2"), +}; +VREG_CONSUMERS(L28) = { + REGULATOR_SUPPLY("8921_l28", NULL), + REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.1"), +}; +VREG_CONSUMERS(L29) = { + REGULATOR_SUPPLY("8921_l29", NULL), +}; +VREG_CONSUMERS(S1) = { + REGULATOR_SUPPLY("8921_s1", NULL), +}; +VREG_CONSUMERS(S2) = { + REGULATOR_SUPPLY("8921_s2", NULL), + REGULATOR_SUPPLY("iris_vddrfa", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(S3) = { + REGULATOR_SUPPLY("8921_s3", NULL), + REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"), + REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_ehci_host.0"), + REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_ehci_host.1"), + REGULATOR_SUPPLY("HSIC_VDDCX", "msm_hsic_host"), + REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"), + REGULATOR_SUPPLY("vp_pcie", "msm_pcie"), + REGULATOR_SUPPLY("vptx_pcie", "msm_pcie"), +}; +VREG_CONSUMERS(S4) = { + REGULATOR_SUPPLY("8921_s4", NULL), + REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.1"), + REGULATOR_SUPPLY("VDDIO_CDC", "tabla-slim"), + REGULATOR_SUPPLY("CDC_VDD_CP", "tabla-slim"), + REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla-slim"), + REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla-slim"), + REGULATOR_SUPPLY("VDDIO_CDC", "tabla2x-slim"), + REGULATOR_SUPPLY("CDC_VDD_CP", "tabla2x-slim"), + REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla2x-slim"), + REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla2x-slim"), + REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"), + REGULATOR_SUPPLY("vcc_i2c", "3-005b"), + REGULATOR_SUPPLY("vcc_i2c", "3-0024"), + REGULATOR_SUPPLY("vddp", "0-0048"), + REGULATOR_SUPPLY("hdmi_lvl_tsl", "hdmi_msm.0"), +}; +VREG_CONSUMERS(S5) = { + REGULATOR_SUPPLY("8921_s5", NULL), + REGULATOR_SUPPLY("krait0", NULL), +}; +VREG_CONSUMERS(S6) = { + REGULATOR_SUPPLY("8921_s6", NULL), + REGULATOR_SUPPLY("krait1", NULL), +}; +VREG_CONSUMERS(S7) = { + REGULATOR_SUPPLY("8921_s7", NULL), +}; +#if defined(CONFIG_IMX091) +VREG_CONSUMERS(S8) = { + REGULATOR_SUPPLY("8921_s8", NULL), +}; +#else +VREG_CONSUMERS(S8) = { + REGULATOR_SUPPLY("8921_s8", NULL), +}; +#endif +VREG_CONSUMERS(LVS1) = { + REGULATOR_SUPPLY("8921_lvs1", NULL), + REGULATOR_SUPPLY("iris_vddio", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(LVS2) = { + REGULATOR_SUPPLY("8921_lvs2", NULL), + REGULATOR_SUPPLY("iris_vdddig", "wcnss_wlan.0"), +}; +VREG_CONSUMERS(LVS3) = { + REGULATOR_SUPPLY("8921_lvs3", NULL), +}; +VREG_CONSUMERS(LVS4) = { + REGULATOR_SUPPLY("8921_lvs4", NULL), +}; +VREG_CONSUMERS(LVS5) = { + REGULATOR_SUPPLY("8921_lvs5", NULL), + REGULATOR_SUPPLY("cam1_vio", "4-000d"), /* GSBI4, Slave Addr: 0x0d, imx111 */ + REGULATOR_SUPPLY("cam2_vio", "4-006e"), /* GSBI4, Slave Addr: 0x6e, imx119 */ +}; +VREG_CONSUMERS(LVS6) = { + REGULATOR_SUPPLY("8921_lvs6", NULL), + REGULATOR_SUPPLY("vdd_pcie_vph", "msm_pcie"), + REGULATOR_SUPPLY("dsi_iovcc", "mipi_dsi.1"), +}; +VREG_CONSUMERS(LVS7) = { + REGULATOR_SUPPLY("8921_lvs7", NULL), + REGULATOR_SUPPLY("pll_vdd", "pil_riva"), + REGULATOR_SUPPLY("lvds_vdda", "lvds.0"), + REGULATOR_SUPPLY("dsi1_vddio", "mipi_dsi.1"), + REGULATOR_SUPPLY("hdmi_vdda", "hdmi_msm.0"), +}; +VREG_CONSUMERS(NCP) = { + REGULATOR_SUPPLY("8921_ncp", NULL), +}; +VREG_CONSUMERS(8821_S0) = { + REGULATOR_SUPPLY("8821_s0", NULL), + REGULATOR_SUPPLY("krait2", NULL), +}; +VREG_CONSUMERS(8821_S1) = { + REGULATOR_SUPPLY("8821_s1", NULL), + REGULATOR_SUPPLY("krait3", NULL), +}; +VREG_CONSUMERS(FRC_5V) = { + REGULATOR_SUPPLY("frc_5v", NULL), +}; +VREG_CONSUMERS(AVC_1P2V) = { + REGULATOR_SUPPLY("avc_1p2v", NULL), +}; +VREG_CONSUMERS(AVC_1P8V) = { + REGULATOR_SUPPLY("avc_1p8v", NULL), +}; +VREG_CONSUMERS(AVC_2P2V) = { + REGULATOR_SUPPLY("avc_2p2v", NULL), +}; +VREG_CONSUMERS(AVC_5V) = { + REGULATOR_SUPPLY("avc_5v", NULL), +}; +VREG_CONSUMERS(AVC_3P3V) = { + REGULATOR_SUPPLY("avc_3p3v", NULL), +}; + +#define PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, _modes, _ops, \ + _apply_uV, _pull_down, _always_on, _supply_regulator, \ + _system_uA, _enable_time, _reg_id) \ + { \ + .init_data = { \ + .constraints = { \ + .valid_modes_mask = _modes, \ + .valid_ops_mask = _ops, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .input_uV = _max_uV, \ + .apply_uV = _apply_uV, \ + .always_on = _always_on, \ + .name = _name, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(vreg_consumers_##_id), \ + .consumer_supplies = vreg_consumers_##_id, \ + .supply_regulator = _supply_regulator, \ + }, \ + .id = _reg_id, \ + .pull_down_enable = _pull_down, \ + .system_uA = _system_uA, \ + .enable_time = _enable_time, \ + } + +#define PM8XXX_LDO(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \ + _enable_time, _supply_regulator, _system_uA, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \ + | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \ + REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \ + _supply_regulator, _system_uA, _enable_time, _reg_id) + +#define PM8XXX_NLDO1200(_id, _name, _always_on, _pull_down, _min_uV, \ + _max_uV, _enable_time, _supply_regulator, _system_uA, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \ + | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \ + REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \ + _supply_regulator, _system_uA, _enable_time, _reg_id) + +#define PM8XXX_SMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \ + _enable_time, _supply_regulator, _system_uA, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \ + | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \ + REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \ + _supply_regulator, _system_uA, _enable_time, _reg_id) + +#define PM8XXX_FTSMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \ + _enable_time, _supply_regulator, _system_uA, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \ + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS \ + | REGULATOR_CHANGE_MODE, 0, _pull_down, _always_on, \ + _supply_regulator, _system_uA, _enable_time, _reg_id) + +#define PM8XXX_VS(_id, _name, _always_on, _pull_down, _enable_time, \ + _supply_regulator, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \ + _pull_down, _always_on, _supply_regulator, 0, _enable_time, \ + _reg_id) + +#define PM8XXX_VS300(_id, _name, _always_on, _pull_down, _enable_time, \ + _supply_regulator, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \ + _pull_down, _always_on, _supply_regulator, 0, _enable_time, \ + _reg_id) + +#define PM8XXX_NCP(_id, _name, _always_on, _min_uV, _max_uV, _enable_time, \ + _supply_regulator, _reg_id) \ + PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, 0, \ + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, 0, \ + _always_on, _supply_regulator, 0, _enable_time, _reg_id) + +/* Pin control initialization */ +#define PM8XXX_PC(_id, _name, _always_on, _pin_fn, _pin_ctrl, \ + _supply_regulator, _reg_id) \ + { \ + .init_data = { \ + .constraints = { \ + .valid_ops_mask = REGULATOR_CHANGE_STATUS, \ + .always_on = _always_on, \ + .name = _name, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(vreg_consumers_##_id##_PC), \ + .consumer_supplies = vreg_consumers_##_id##_PC, \ + .supply_regulator = _supply_regulator, \ + }, \ + .id = _reg_id, \ + .pin_fn = PM8XXX_VREG_PIN_FN_##_pin_fn, \ + .pin_ctrl = _pin_ctrl, \ + } + +#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \ + [GPIO_VREG_ID_##_id] = { \ + .init_data = { \ + .constraints = { \ + .valid_ops_mask = REGULATOR_CHANGE_STATUS, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(vreg_consumers_##_id), \ + .consumer_supplies = vreg_consumers_##_id, \ + .supply_regulator = _supply_regulator, \ + }, \ + .regulator_name = _reg_name, \ + .gpio_label = _gpio_label, \ + .gpio = _gpio, \ + } + +#define SAW_VREG_INIT(_id, _name, _min_uV, _max_uV) \ + { \ + .constraints = { \ + .name = _name, \ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_##_id), \ + .consumer_supplies = vreg_consumers_##_id, \ + } + +#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \ + _peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \ + _force_mode, _sleep_set_force_mode, _power_mode, _state, \ + _sleep_selectable, _always_on, _supply_regulator, _system_uA) \ + { \ + .init_data = { \ + .constraints = { \ + .valid_modes_mask = _modes, \ + .valid_ops_mask = _ops, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .input_uV = _min_uV, \ + .apply_uV = _apply_uV, \ + .always_on = _always_on, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(vreg_consumers_##_id), \ + .consumer_supplies = vreg_consumers_##_id, \ + .supply_regulator = _supply_regulator, \ + }, \ + .id = RPM_VREG_ID_PM8921_##_id, \ + .default_uV = _default_uV, \ + .peak_uA = _peak_uA, \ + .avg_uA = _avg_uA, \ + .pull_down_enable = _pull_down, \ + .pin_ctrl = _pin_ctrl, \ + .freq = RPM_VREG_FREQ_##_freq, \ + .pin_fn = _pin_fn, \ + .force_mode = _force_mode, \ + .sleep_set_force_mode = _sleep_set_force_mode, \ + .power_mode = _power_mode, \ + .state = _state, \ + .sleep_selectable = _sleep_selectable, \ + .system_uA = _system_uA, \ + } + +#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \ + _supply_regulator, _system_uA, _init_peak_uA) \ + RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \ + | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \ + | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \ + | REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \ + RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \ + RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \ + _supply_regulator, _system_uA) + +#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \ + _supply_regulator, _system_uA, _freq, _force_mode, \ + _sleep_set_force_mode) \ + RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \ + | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \ + | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \ + | REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \ + RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_##_force_mode, \ + RPM_VREG_FORCE_MODE_8960_##_sleep_set_force_mode, \ + RPM_VREG_POWER_MODE_8960_PWM, RPM_VREG_STATE_OFF, \ + _sleep_selectable, _always_on, _supply_regulator, _system_uA) + +#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \ + RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \ + RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \ + RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \ + _supply_regulator, 0) + +#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \ + _supply_regulator, _freq) \ + RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \ + | REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \ + RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, \ + RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \ + RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \ + _supply_regulator, 0) + +/* Pin control initialization */ +#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \ + { \ + .init_data = { \ + .constraints = { \ + .valid_ops_mask = REGULATOR_CHANGE_STATUS, \ + .always_on = _always_on, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(vreg_consumers_##_id##_PC), \ + .consumer_supplies = vreg_consumers_##_id##_PC, \ + .supply_regulator = _supply_regulator, \ + }, \ + .id = RPM_VREG_ID_PM8921_##_id##_PC, \ + .pin_fn = RPM_VREG_PIN_FN_8960_##_pin_fn, \ + .pin_ctrl = _pin_ctrl, \ + } + +struct gpio_regulator_platform_data +mpq8064_gpio_regulator_pdata[] __devinitdata = { + GPIO_VREG(FRC_5V, "frc_5v", "frc_5v_en", SX150X_GPIO(4, 10), NULL), + GPIO_VREG(AVC_1P2V, "avc_1p2v", "avc_1p2v_en", SX150X_GPIO(4, 2), NULL), + GPIO_VREG(AVC_1P8V, "avc_1p8v", "avc_1p8v_en", SX150X_GPIO(4, 4), NULL), + GPIO_VREG(AVC_2P2V, "avc_2p2v", "avc_2p2v_en", + SX150X_GPIO(4, 14), NULL), + GPIO_VREG(AVC_5V, "avc_5v", "avc_5v_en", SX150X_GPIO(4, 3), NULL), + GPIO_VREG(AVC_3P3V, "avc_3p3v", "avc_3p3v_en", + SX150X_GPIO(4, 15), "avc_5v"), +}; + +/* SAW regulator constraints */ +struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5 = + /* ID vreg_name min_uV max_uV */ + SAW_VREG_INIT(S5, "8921_s5", 950000, 1300000); +struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6 = + SAW_VREG_INIT(S6, "8921_s6", 950000, 1300000); + +struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0 = + /* ID vreg_name min_uV max_uV */ + SAW_VREG_INIT(8821_S0, "8821_s0", 950000, 1300000); +struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1 = + SAW_VREG_INIT(8821_S1, "8821_s1", 950000, 1300000); + +/* PM8921 regulator constraints */ +struct pm8xxx_regulator_platform_data +msm8064_pm8921_regulator_pdata[] __devinitdata = { + /* + * ID name always_on pd min_uV max_uV en_t supply + * system_uA reg_ID + */ + PM8XXX_NLDO1200(L26, "8921_l26", 0, 1, 375000, 1050000, 200, "8921_s7", + 0, 1), +}; + +static struct rpm_regulator_init_data +apq8064_rpm_regulator_init_data[] __devinitdata = { + /* ID a_on pd ss min_uV max_uV supply sys_uA freq fm ss_fm */ + RPM_SMPS(S1, 1, 1, 0, 1225000, 1225000, NULL, 100000, 3p20, NONE, NONE), + RPM_SMPS(S2, 0, 1, 0, 1300000, 1300000, NULL, 0, 1p60, NONE, NONE), + RPM_SMPS(S3, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, NONE, NONE), + RPM_SMPS(S4, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60, AUTO, AUTO), + RPM_SMPS(S7, 0, 1, 0, 1300000, 1300000, NULL, 100000, 3p20, NONE, NONE), +#if defined(CONFIG_IMX091) + RPM_SMPS(S8, 0, 1, 0, 1800000, 1800000, NULL, 100000, 1p60, NONE, NONE), +#else + RPM_SMPS(S8, 0, 1, 0, 2200000, 2200000, NULL, 0, 1p60, NONE, NONE), +#endif + /* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */ + RPM_LDO(L1, 1, 1, 0, 1100000, 1100000, "8921_s4", 0, 1000), + RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0), + /* HSUSB 3p3: max 3.5v */ + RPM_LDO(L3, 0, 1, 0, 3075000, 3500000, NULL, 0, 0), + RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 0, 10000), + RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0), + RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0), + RPM_LDO(L7, 0, 1, 0, 1850000, 2950000, NULL, 0, 0), + RPM_LDO(L8, 0, 1, 0, 2800000, 3000000, NULL, 0, 0), + RPM_LDO(L9, 0, 1, 0, 3000000, 3000000, NULL, 0, 0), + RPM_LDO(L10, 0, 1, 0, 2900000, 2900000, NULL, 0, 0), + RPM_LDO(L11, 0, 1, 0, 2850000, 2850000, NULL, 0, 0), + RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0), + RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0), + RPM_LDO(L15, 0, 1, 0, 3300000, 3300000, NULL, 0, 19), + RPM_LDO(L16, 0, 1, 0, 2800000, 2800000, NULL, 0, 0), + RPM_LDO(L17, 0, 1, 0, 2800000, 2800000, NULL, 0, 0), + RPM_LDO(L18, 0, 1, 0, 1100000, 1300000, NULL, 0, 0), +#if defined(CONFIG_IMX091) + RPM_LDO(L21, 0, 1, 0, 1800000, 1800000, "8921_s8", 0, 0), +#else + RPM_LDO(L21, 0, 1, 0, 1050000, 1050000, NULL, 0, 0), +#endif + RPM_LDO(L22, 0, 1, 0, 1800000, 1800000, NULL, 0, 0), + RPM_LDO(L23, 0, 1, 0, 1800000, 1800000, NULL, 0, 0), + RPM_LDO(L24, 0, 1, 1, 750000, 1150000, "8921_s1", 10000, 10000), + RPM_LDO(L25, 1, 1, 0, 1225000, 1225000, "8921_s1", 10000, 10000), + RPM_LDO(L27, 0, 1, 0, 1100000, 1100000, "8921_s7", 0, 0), + RPM_LDO(L28, 0, 1, 0, 1050000, 1050000, "8921_s7", 0, 0), + RPM_LDO(L29, 0, 1, 0, 2000000, 2000000, NULL, 0, 0), + + /* ID a_on pd ss supply */ + RPM_VS(LVS1, 0, 1, 0, "8921_s4"), + RPM_VS(LVS2, 0, 1, 0, "8921_s1"), + RPM_VS(LVS3, 0, 1, 0, "8921_s4"), + RPM_VS(LVS4, 0, 1, 0, "8921_s4"), + RPM_VS(LVS5, 0, 1, 0, "8921_s4"), + RPM_VS(LVS6, 0, 1, 0, "8921_s4"), + RPM_VS(LVS7, 0, 1, 1, "8921_s4"), + + /* ID a_on ss min_uV max_uV supply freq */ + RPM_NCP(NCP, 0, 0, 1800000, 1800000, "8921_l6", 1p60), +}; + +int msm8064_pm8921_regulator_pdata_len __devinitdata = + ARRAY_SIZE(msm8064_pm8921_regulator_pdata); + +struct rpm_regulator_platform_data apq8064_rpm_regulator_pdata __devinitdata = { + .init_data = apq8064_rpm_regulator_init_data, + .num_regulators = ARRAY_SIZE(apq8064_rpm_regulator_init_data), + .version = RPM_VREG_VERSION_8960, + .vreg_id_vdd_mem = RPM_VREG_ID_PM8921_L24, + .vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3, +}; diff --git a/arch/arm/mach-msm/lge/mako/board-mako-sound.c b/arch/arm/mach-msm/lge/mako/board-mako-sound.c new file mode 100644 index 000000000000..9099a028221d --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-sound.c @@ -0,0 +1,218 @@ +/* Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include "devices.h" + +#include "board-8064.h" + +#ifdef CONFIG_SWITCH_FSA8008 +#include "../../../../sound/soc/codecs/wcd9310.h" +#endif + +#ifdef CONFIG_LGE_AUDIO_TPA2028D +#include +#endif + +#include "board-mako.h" + + +#define TPA2028D_ADDRESS (0xB0>>1) +#define MSM_AMP_EN (PM8921_GPIO_PM_TO_SYS(19)) +#define AGC_COMPRESIION_RATE 0 +#define AGC_OUTPUT_LIMITER_DISABLE 1 +#define AGC_FIXED_GAIN 12 + + +#define GPIO_EAR_SENSE_N 82 +#define GPIO_EAR_MIC_EN PM8921_GPIO_PM_TO_SYS(31) +#define GPIO_EARPOL_DETECT PM8921_GPIO_PM_TO_SYS(32) +#define GPIO_EAR_KEY_INT 83 + + +#define I2C_SURF 1 +#define I2C_FFA (1 << 1) +#define I2C_RUMI (1 << 2) +#define I2C_SIM (1 << 3) +#define I2C_LIQUID (1 << 4) +#define I2C_J1V (1 << 5) + +struct i2c_registry { + u8 machs; + int bus; + struct i2c_board_info *info; + int len; +}; + + +struct fsa8008_platform_data { + const char *switch_name; /* switch device name */ + const char *keypad_name; /* keypad device name */ + + unsigned int key_code; /* key code for hook */ + + unsigned int gpio_detect; /* DET : to detect jack inserted or not */ + unsigned int gpio_mic_en; /* EN : to enable mic */ + unsigned int gpio_jpole; /* JPOLE : 3pole or 4pole */ + unsigned int gpio_key; /* S/E button */ + + /* callback function which is initialized while probing */ + void (*set_headset_mic_bias)(int enable); + + /* latency for pole (3 or 4)detection (in ms) */ + unsigned int latency_for_detection; +}; + +#ifdef CONFIG_LGE_AUDIO_TPA2028D +int amp_power(bool on) +{ + return 0; +} + +int amp_enable(int on_state) +{ + int err = 0; + static int init_status = 0; + struct pm_gpio param = { + .direction = PM_GPIO_DIR_OUT, + .output_buffer = PM_GPIO_OUT_BUF_CMOS, + .output_value = 1, + .pull = PM_GPIO_PULL_NO, + .vin_sel = PM_GPIO_VIN_S4, + .out_strength = PM_GPIO_STRENGTH_MED, + .function = PM_GPIO_FUNC_NORMAL, + }; + + if (init_status == 0) { + err = gpio_request(MSM_AMP_EN, "AMP_EN"); + if (err) + pr_err("%s: Error requesting GPIO %d\n", + __func__, MSM_AMP_EN); + + err = pm8xxx_gpio_config(MSM_AMP_EN, ¶m); + if (err) + pr_err("%s: Failed to configure gpio %d\n", + __func__, MSM_AMP_EN); + else + init_status++; + } + + switch (on_state) { + case 0: + err = gpio_direction_output(MSM_AMP_EN, 0); + printk(KERN_INFO "%s: AMP_EN is set to 0\n", __func__); + break; + case 1: + err = gpio_direction_output(MSM_AMP_EN, 1); + printk(KERN_INFO "%s: AMP_EN is set to 1\n", __func__); + break; + case 2: + printk(KERN_INFO "%s: amp enable bypass(%d)\n", __func__, on_state); + err = 0; + break; + + default: + pr_err("amp enable fail\n"); + err = 1; + break; + } + return err; +} + +static struct audio_amp_platform_data amp_platform_data = { + .enable = amp_enable, + .power = amp_power, + .agc_compression_rate = AGC_COMPRESIION_RATE, + .agc_output_limiter_disable = AGC_OUTPUT_LIMITER_DISABLE, + .agc_fixed_gain = AGC_FIXED_GAIN, +}; +#endif + +static struct i2c_board_info msm_i2c_audiosubsystem_info[] = { +#ifdef CONFIG_LGE_AUDIO_TPA2028D + { + I2C_BOARD_INFO("tpa2028d_amp", TPA2028D_ADDRESS), + .platform_data = &_platform_data, + } +#endif +}; + + +static struct i2c_registry msm_i2c_audiosubsystem __initdata = { + /* Add the I2C driver for Audio Amp */ + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + msm_i2c_audiosubsystem_info, + ARRAY_SIZE(msm_i2c_audiosubsystem_info), +}; + + +static void __init lge_add_i2c_tpa2028d_devices(void) +{ + /* Run the array and install devices as appropriate */ + i2c_register_board_info(msm_i2c_audiosubsystem.bus, + msm_i2c_audiosubsystem.info, + msm_i2c_audiosubsystem.len); +} + + +#ifdef CONFIG_SWITCH_FSA8008 +static struct fsa8008_platform_data lge_hs_pdata = { + .switch_name = "h2w", + .keypad_name = "hs_detect", + + .key_code = KEY_MEDIA, + + .gpio_detect = GPIO_EAR_SENSE_N, + .gpio_mic_en = GPIO_EAR_MIC_EN, + .gpio_jpole = GPIO_EARPOL_DETECT, + .gpio_key = GPIO_EAR_KEY_INT, + + .latency_for_detection = 75, + .set_headset_mic_bias = tabla_codec_micbias2_ctl, +}; + +static struct platform_device lge_hsd_device = { + .name = "fsa8008", + .id = -1, + .dev = { + .platform_data = &lge_hs_pdata, + }, +}; + +static int __init lge_hsd_fsa8008_init(void) +{ + printk(KERN_INFO "lge_hsd_fsa8008_init\n"); + return platform_device_register(&lge_hsd_device); +} + +static void __exit lge_hsd_fsa8008_exit(void) +{ + printk(KERN_INFO "lge_hsd_fsa8008_exit\n"); + platform_device_unregister(&lge_hsd_device); +} +#endif + +void __init lge_add_sound_devices(void) +{ + lge_add_i2c_tpa2028d_devices(); + +#ifdef CONFIG_SWITCH_FSA8008 + lge_hsd_fsa8008_init(); +#endif + +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako-storage.c b/arch/arm/mach-msm/lge/mako/board-mako-storage.c new file mode 100644 index 000000000000..df310f179ed7 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako-storage.c @@ -0,0 +1,290 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" +#include "board-mako.h" +#include "board-storage-common-a.h" + + +/* APQ8064 has 4 SDCC controllers */ +enum sdcc_controllers { + SDCC1, + SDCC2, + SDCC3, + SDCC4, + MAX_SDCC_CONTROLLER +}; + +/* All SDCC controllers require VDD/VCC voltage */ +static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = { + /* SDCC1 : eMMC card connected */ + [SDCC1] = { + .name = "sdc_vdd", + .high_vol_level = 2950000, + .low_vol_level = 2950000, + .always_on = 1, + .lpm_sup = 1, + .lpm_uA = 9000, + .hpm_uA = 200000, /* 200mA */ + }, + /* SDCC3 : External card slot connected */ + [SDCC3] = { + .name = "sdc_vdd", + .high_vol_level = 2950000, + .low_vol_level = 2950000, + .hpm_uA = 800000, /* 800mA */ + } +}; + +/* SDCC controllers may require voting for VDD IO voltage */ +static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = { + /* SDCC1 : eMMC card connected */ + [SDCC1] = { + .name = "sdc_vdd_io", + .always_on = 1, + .high_vol_level = 1800000, + .low_vol_level = 1800000, + .hpm_uA = 200000, /* 200mA */ + }, + /* SDCC3 : External card slot connected */ + [SDCC3] = { + .name = "sdc_vdd_io", + .high_vol_level = 2950000, + .low_vol_level = 1850000, + .always_on = 1, + .lpm_sup = 1, + /* Max. Active current required is 16 mA */ + .hpm_uA = 16000, + /* + * Sleep current required is ~300 uA. But min. vote can be + * in terms of mA (min. 1 mA). So let's vote for 2 mA + * during sleep. + */ + .lpm_uA = 2000, + } +}; + +static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = { + /* SDCC1 : eMMC card connected */ + [SDCC1] = { + .vdd_data = &mmc_vdd_reg_data[SDCC1], + .vdd_io_data = &mmc_vdd_io_reg_data[SDCC1], + }, + /* SDCC3 : External card slot connected */ + [SDCC3] = { + .vdd_data = &mmc_vdd_reg_data[SDCC3], + .vdd_io_data = &mmc_vdd_io_reg_data[SDCC3], + } +}; + +/* SDC1 pad data */ +static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = { + {TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA}, + {TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA}, + {TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA} +}; + +static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = { + {TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA}, + {TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA}, + {TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA} +}; + +static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = { + {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, + {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP}, + {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP} +}; + +static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = { + {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, + {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP}, + {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP} +}; + +/* SDC3 pad data */ +static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = { + {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA}, + {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA}, + {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA} +}; + +static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = { + {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA}, + {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA}, + {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA} +}; + +static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = { + {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL}, + {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP}, + {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP} +}; + +static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = { + {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL}, + {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP}, + {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP} +}; + +static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = { + [SDCC1] = { + .on = sdc1_pad_pull_on_cfg, + .off = sdc1_pad_pull_off_cfg, + .size = ARRAY_SIZE(sdc1_pad_pull_on_cfg) + }, + [SDCC3] = { + .on = sdc3_pad_pull_on_cfg, + .off = sdc3_pad_pull_off_cfg, + .size = ARRAY_SIZE(sdc3_pad_pull_on_cfg) + }, +}; + +static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = { + [SDCC1] = { + .on = sdc1_pad_drv_on_cfg, + .off = sdc1_pad_drv_off_cfg, + .size = ARRAY_SIZE(sdc1_pad_drv_on_cfg) + }, + [SDCC3] = { + .on = sdc3_pad_drv_on_cfg, + .off = sdc3_pad_drv_off_cfg, + .size = ARRAY_SIZE(sdc3_pad_drv_on_cfg) + }, +}; + +static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = { + [SDCC1] = { + .pull = &mmc_pad_pull_data[SDCC1], + .drv = &mmc_pad_drv_data[SDCC1] + }, + [SDCC3] = { + .pull = &mmc_pad_pull_data[SDCC3], + .drv = &mmc_pad_drv_data[SDCC3] + }, +}; + +static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = { + [SDCC1] = { + .pad_data = &mmc_pad_data[SDCC1], + }, + [SDCC3] = { + .pad_data = &mmc_pad_data[SDCC3], + }, +}; + +#define MSM_MPM_PIN_SDC1_DAT1 17 +#define MSM_MPM_PIN_SDC3_DAT1 21 + +#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT +static unsigned int sdc1_sup_clk_rates[] = { + 400000, 24000000, 48000000, 96000000 +}; + +static struct mmc_platform_data sdc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, +#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT + .mmc_bus_width = MMC_CAP_8_BIT_DATA, +#else + .mmc_bus_width = MMC_CAP_4_BIT_DATA, +#endif + .sup_clk_table = sdc1_sup_clk_rates, + .sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates), + .pclk_src_dfab = 1, + .nonremovable = 1, + .pin_data = &mmc_slot_pin_data[SDCC1], + .vreg_data = &mmc_slot_vreg_data[SDCC1], + .uhs_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50, + .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1, + .msm_bus_voting_data = &sps_to_ddr_bus_voting_data, +}; +static struct mmc_platform_data *apq8064_sdc1_pdata = &sdc1_data; +#else +static struct mmc_platform_data *apq8064_sdc1_pdata; +#endif + +#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT +static unsigned int sdc3_sup_clk_rates[] = { + 400000, 24000000, 48000000, 96000000, 192000000 +}; + +static struct mmc_platform_data sdc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .mmc_bus_width = MMC_CAP_4_BIT_DATA, + .sup_clk_table = sdc3_sup_clk_rates, + .sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates), + .pclk_src_dfab = 1, + .pin_data = &mmc_slot_pin_data[SDCC3], + .vreg_data = &mmc_slot_vreg_data[SDCC3], + .status_gpio = 26, + .status_irq = MSM_GPIO_TO_INT(26), + .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + .is_status_gpio_active_low = 1, + .xpc_cap = 1, + .uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | + MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | + MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800), + .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1, + .msm_bus_voting_data = &sps_to_ddr_bus_voting_data, +}; +static struct mmc_platform_data *apq8064_sdc3_pdata = &sdc3_data; +#else +static struct mmc_platform_data *apq8064_sdc3_pdata; +#endif + +void __init apq8064_init_mmc(void) +{ + if ((machine_is_apq8064_rumi3()) || machine_is_apq8064_sim()) { + if (apq8064_sdc1_pdata) { + if (machine_is_apq8064_sim()) + apq8064_sdc1_pdata->disable_bam = true; + apq8064_sdc1_pdata->disable_runtime_pm = true; + apq8064_sdc1_pdata->disable_cmd23 = true; + } + if (apq8064_sdc3_pdata) { + if (machine_is_apq8064_sim()) + apq8064_sdc3_pdata->disable_bam = true; + apq8064_sdc3_pdata->disable_runtime_pm = true; + apq8064_sdc3_pdata->disable_cmd23 = true; + } + } + + if (apq8064_sdc1_pdata) + apq8064_add_sdcc(1, apq8064_sdc1_pdata); + + if (apq8064_sdc3_pdata) { + if (!machine_is_apq8064_cdp()) { + apq8064_sdc3_pdata->wpswitch_gpio = 0; + apq8064_sdc3_pdata->wpswitch_polarity = 0; + } + if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv()) { + apq8064_sdc3_pdata->status_gpio = + PM8921_GPIO_PM_TO_SYS(31); + apq8064_sdc3_pdata->status_irq = + PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 31); + } + apq8064_add_sdcc(3, apq8064_sdc3_pdata); + } +} diff --git a/arch/arm/mach-msm/lge/mako/board-mako.c b/arch/arm/mach-msm/lge/mako/board-mako.c new file mode 100644 index 000000000000..4883c40e38aa --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako.c @@ -0,0 +1,2522 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012, LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#ifdef CONFIG_SMB349_CHARGER +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SENSORS_EPM_ADC +#include +#endif +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "timer.h" +#include "devices.h" +#include +#include +#include +#ifdef CONFIG_ANDROID_PMEM +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_MSM_RTB +#include +#endif +#ifdef CONFIG_SND_SOC_CS8427 +#include +#endif +#ifdef CONFIG_IR_GPIO_CIR +#include +#endif +#include +#include +#include + +#include +#ifdef CONFIG_USB_G_LGE_ANDROID +#include +#endif + +#include "msm_watchdog.h" +#include "board-mako.h" +#include "acpuclock.h" +#include "spm.h" +#include +#include "rpm_resources.h" +#include "pm.h" +#include "pm-boot.h" +#include "devices-msm8x60.h" +#include "smd_private.h" + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) +#include +#endif + +#define MSM_PMEM_ADSP_SIZE 0x7800000 +#define MSM_PMEM_AUDIO_SIZE 0x4CF000 +#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */ + +#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION +#define MSM_PMEM_KERNEL_EBI1_SIZE 0x65000 +#ifdef CONFIG_MSM_IOMMU + +#define MSM_ION_MM_SIZE 0x3800000 +#define MSM_ION_SF_SIZE 0 +#define MSM_ION_QSECOM_SIZE 0x780000 /* (7.5MB) */ +#define MSM_ION_HEAP_NUM 7 +#else +#define MSM_ION_MM_SIZE MSM_PMEM_ADSP_SIZE +#define MSM_ION_SF_SIZE MSM_PMEM_SIZE +#define MSM_ION_QSECOM_SIZE 0x600000 /* (6MB) */ +#define MSM_ION_HEAP_NUM 8 +#endif +#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */ +#define MSM_ION_MFC_SIZE SZ_8K +#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE +#else +#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000 +#define MSM_ION_HEAP_NUM 1 +#endif + +#define APQ8064_FIXED_AREA_START 0xa0000000 +#define MAX_FIXED_AREA_SIZE 0x10000000 +#define MSM_MM_FW_SIZE 0x200000 +#define APQ8064_FW_START (APQ8064_FIXED_AREA_START - MSM_MM_FW_SIZE) + +/* PCIe power enable pmic gpio */ +#define PCIE_PWR_EN_PMIC_GPIO 13 +#define PCIE_RST_N_PMIC_MPP 1 + +#ifdef CONFIG_KERNEL_PMEM_EBI_REGION +static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE; +static int __init pmem_kernel_ebi1_size_setup(char *p) +{ + pmem_kernel_ebi1_size = memparse(p, NULL); + return 0; +} +early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup); +#endif + +#ifdef CONFIG_ANDROID_PMEM +static unsigned pmem_size = MSM_PMEM_SIZE; +static int __init pmem_size_setup(char *p) +{ + pmem_size = memparse(p, NULL); + return 0; +} +early_param("pmem_size", pmem_size_setup); + +static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE; + +static int __init pmem_adsp_size_setup(char *p) +{ + pmem_adsp_size = memparse(p, NULL); + return 0; +} +early_param("pmem_adsp_size", pmem_adsp_size_setup); + +static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE; + +static int __init pmem_audio_size_setup(char *p) +{ + pmem_audio_size = memparse(p, NULL); + return 0; +} +early_param("pmem_audio_size", pmem_audio_size_setup); +#endif + +#ifdef CONFIG_ANDROID_PMEM +#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem", + .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING, + .cached = 1, + .memory_type = MEMTYPE_EBI1, +}; + +static struct platform_device apq8064_android_pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = {.platform_data = &android_pmem_pdata}, +}; + +static struct android_pmem_platform_data android_pmem_adsp_pdata = { + .name = "pmem_adsp", + .allocator_type = PMEM_ALLOCATORTYPE_BITMAP, + .cached = 0, + .memory_type = MEMTYPE_EBI1, +}; +static struct platform_device apq8064_android_pmem_adsp_device = { + .name = "android_pmem", + .id = 2, + .dev = { .platform_data = &android_pmem_adsp_pdata }, +}; + +static struct android_pmem_platform_data android_pmem_audio_pdata = { + .name = "pmem_audio", + .allocator_type = PMEM_ALLOCATORTYPE_BITMAP, + .cached = 0, + .memory_type = MEMTYPE_EBI1, +}; + +static struct platform_device apq8064_android_pmem_audio_device = { + .name = "android_pmem", + .id = 4, + .dev = { .platform_data = &android_pmem_audio_pdata }, +}; +#endif /* CONFIG_MSM_MULTIMEDIA_USE_ION */ +#endif + +struct fmem_platform_data apq8064_fmem_pdata = { +}; + +static struct memtype_reserve apq8064_reserve_table[] __initdata = { + [MEMTYPE_SMI] = { + }, + [MEMTYPE_EBI0] = { + .flags = MEMTYPE_FLAGS_1M_ALIGN, + }, + [MEMTYPE_EBI1] = { + .flags = MEMTYPE_FLAGS_1M_ALIGN, + }, +}; + +static void __init reserve_rtb_memory(void) +{ +#if defined(CONFIG_MSM_RTB) + apq8064_reserve_table[MEMTYPE_EBI1].size += apq8064_rtb_pdata.size; +#endif +} + + +static void __init size_pmem_devices(void) +{ +#ifdef CONFIG_ANDROID_PMEM +#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION + android_pmem_adsp_pdata.size = pmem_adsp_size; + android_pmem_pdata.size = pmem_size; + android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE; +#endif +#endif /*CONFIG_ANDROID_PMEM*/ +} + +#ifdef CONFIG_ANDROID_PMEM +#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION +static void __init reserve_memory_for(struct android_pmem_platform_data *p) +{ + apq8064_reserve_table[p->memory_type].size += p->size; +} +#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/ +#endif /*CONFIG_ANDROID_PMEM*/ + +static void __init reserve_pmem_memory(void) +{ +#ifdef CONFIG_ANDROID_PMEM +#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION + reserve_memory_for(&android_pmem_adsp_pdata); + reserve_memory_for(&android_pmem_pdata); + reserve_memory_for(&android_pmem_audio_pdata); +#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/ + apq8064_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size; +#endif +} + +static int apq8064_paddr_to_memtype(unsigned int paddr) +{ + return MEMTYPE_EBI1; +} + +#define FMEM_ENABLED 1 + +#ifdef CONFIG_ION_MSM +#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION +static struct ion_cp_heap_pdata cp_mm_apq8064_ion_pdata = { + .permission_type = IPT_TYPE_MM_CARVEOUT, + .align = PAGE_SIZE, + .reusable = FMEM_ENABLED, + .mem_is_fmem = FMEM_ENABLED, + .fixed_position = FIXED_MIDDLE, +}; + +static struct ion_cp_heap_pdata cp_mfc_apq8064_ion_pdata = { + .permission_type = IPT_TYPE_MFC_SHAREDMEM, + .align = PAGE_SIZE, + .reusable = 0, + .mem_is_fmem = FMEM_ENABLED, + .fixed_position = FIXED_HIGH, +}; + +static struct ion_co_heap_pdata co_apq8064_ion_pdata = { + .adjacent_mem_id = INVALID_HEAP_ID, + .align = PAGE_SIZE, + .mem_is_fmem = 0, +}; + +static struct ion_co_heap_pdata fw_co_apq8064_ion_pdata = { + .adjacent_mem_id = ION_CP_MM_HEAP_ID, + .align = SZ_128K, + .mem_is_fmem = FMEM_ENABLED, + .fixed_position = FIXED_LOW, +}; +#endif + +/** + * These heaps are listed in the order they will be allocated. Due to + * video hardware restrictions and content protection the FW heap has to + * be allocated adjacent (below) the MM heap and the MFC heap has to be + * allocated after the MM heap to ensure MFC heap is not more than 256MB + * away from the base address of the FW heap. + * However, the order of FW heap and MM heap doesn't matter since these + * two heaps are taken care of by separate code to ensure they are adjacent + * to each other. + * Don't swap the order unless you know what you are doing! + */ +static struct ion_platform_data apq8064_ion_pdata = { + .nr = MSM_ION_HEAP_NUM, + .heaps = { + { + .id = ION_SYSTEM_HEAP_ID, + .type = ION_HEAP_TYPE_SYSTEM, + .name = ION_VMALLOC_HEAP_NAME, + }, +#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION + { + .id = ION_CP_MM_HEAP_ID, + .type = ION_HEAP_TYPE_CP, + .name = ION_MM_HEAP_NAME, + .size = MSM_ION_MM_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &cp_mm_apq8064_ion_pdata, + }, + { + .id = ION_MM_FIRMWARE_HEAP_ID, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = ION_MM_FIRMWARE_HEAP_NAME, + .size = MSM_ION_MM_FW_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &fw_co_apq8064_ion_pdata, + }, + { + .id = ION_CP_MFC_HEAP_ID, + .type = ION_HEAP_TYPE_CP, + .name = ION_MFC_HEAP_NAME, + .size = MSM_ION_MFC_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &cp_mfc_apq8064_ion_pdata, + }, +#ifndef CONFIG_MSM_IOMMU + { + .id = ION_SF_HEAP_ID, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = ION_SF_HEAP_NAME, + .size = MSM_ION_SF_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &co_apq8064_ion_pdata, + }, +#endif + { + .id = ION_IOMMU_HEAP_ID, + .type = ION_HEAP_TYPE_IOMMU, + .name = ION_IOMMU_HEAP_NAME, + }, + { + .id = ION_QSECOM_HEAP_ID, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = ION_QSECOM_HEAP_NAME, + .size = MSM_ION_QSECOM_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &co_apq8064_ion_pdata, + }, + { + .id = ION_AUDIO_HEAP_ID, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = ION_AUDIO_HEAP_NAME, + .size = MSM_ION_AUDIO_SIZE, + .memory_type = ION_EBI_TYPE, + .extra_data = (void *) &co_apq8064_ion_pdata, + }, +#endif + } +}; + +static struct platform_device apq8064_ion_dev = { + .name = "ion-msm", + .id = 1, + .dev = { .platform_data = &apq8064_ion_pdata }, +}; +#endif + +static struct platform_device apq8064_fmem_device = { + .name = "fmem", + .id = 1, + .dev = { .platform_data = &apq8064_fmem_pdata }, +}; + +static void __init reserve_mem_for_ion(enum ion_memory_types mem_type, + unsigned long size) +{ + apq8064_reserve_table[mem_type].size += size; +} + +static void __init apq8064_reserve_fixed_area(unsigned long fixed_area_size) +{ +#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION) + int ret; + + if (fixed_area_size > MAX_FIXED_AREA_SIZE) + panic("fixed area size is larger than %dM\n", + MAX_FIXED_AREA_SIZE >> 20); + + reserve_info->fixed_area_size = fixed_area_size; + reserve_info->fixed_area_start = APQ8064_FW_START; + + ret = memblock_remove(reserve_info->fixed_area_start, + reserve_info->fixed_area_size); + BUG_ON(ret); +#endif +} + +/** + * Reserve memory for ION and calculate amount of reusable memory for fmem. + * We only reserve memory for heaps that are not reusable. However, we only + * support one reusable heap at the moment so we ignore the reusable flag for + * other than the first heap with reusable flag set. Also handle special case + * for video heaps (MM,FW, and MFC). Video requires heaps MM and MFC to be + * at a higher address than FW in addition to not more than 256MB away from the + * base address of the firmware. This means that if MM is reusable the other + * two heaps must be allocated in the same region as FW. This is handled by the + * mem_is_fmem flag in the platform data. In addition the MM heap must be + * adjacent to the FW heap for content protection purposes. + */ +static void __init reserve_ion_memory(void) +{ +#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION) + unsigned int i; + unsigned int reusable_count = 0; + unsigned int fixed_size = 0; + unsigned int fixed_low_size, fixed_middle_size, fixed_high_size; + unsigned long fixed_low_start, fixed_middle_start, fixed_high_start; + + apq8064_fmem_pdata.size = 0; + apq8064_fmem_pdata.reserved_size_low = 0; + apq8064_fmem_pdata.reserved_size_high = 0; + apq8064_fmem_pdata.align = PAGE_SIZE; + fixed_low_size = 0; + fixed_middle_size = 0; + fixed_high_size = 0; + + /* We only support 1 reusable heap. Check if more than one heap + * is specified as reusable and set as non-reusable if found. + */ + for (i = 0; i < apq8064_ion_pdata.nr; ++i) { + const struct ion_platform_heap *heap = + &(apq8064_ion_pdata.heaps[i]); + + if (heap->type == ION_HEAP_TYPE_CP && heap->extra_data) { + struct ion_cp_heap_pdata *data = heap->extra_data; + + reusable_count += (data->reusable) ? 1 : 0; + + if (data->reusable && reusable_count > 1) { + pr_err("%s: Too many heaps specified as " + "reusable. Heap %s was not configured " + "as reusable.\n", __func__, heap->name); + data->reusable = 0; + } + } + } + + for (i = 0; i < apq8064_ion_pdata.nr; ++i) { + const struct ion_platform_heap *heap = + &(apq8064_ion_pdata.heaps[i]); + + if (heap->extra_data) { + int fixed_position = NOT_FIXED; + int mem_is_fmem = 0; + + switch (heap->type) { + case ION_HEAP_TYPE_CP: + mem_is_fmem = ((struct ion_cp_heap_pdata *) + heap->extra_data)->mem_is_fmem; + fixed_position = ((struct ion_cp_heap_pdata *) + heap->extra_data)->fixed_position; + break; + case ION_HEAP_TYPE_CARVEOUT: + mem_is_fmem = ((struct ion_co_heap_pdata *) + heap->extra_data)->mem_is_fmem; + fixed_position = ((struct ion_co_heap_pdata *) + heap->extra_data)->fixed_position; + break; + default: + break; + } + + if (fixed_position != NOT_FIXED) + fixed_size += heap->size; + else + reserve_mem_for_ion(MEMTYPE_EBI1, heap->size); + + if (fixed_position == FIXED_LOW) + fixed_low_size += heap->size; + else if (fixed_position == FIXED_MIDDLE) + fixed_middle_size += heap->size; + else if (fixed_position == FIXED_HIGH) + fixed_high_size += heap->size; + + if (mem_is_fmem) + apq8064_fmem_pdata.size += heap->size; + } + } + + if (!fixed_size) + return; + + if (apq8064_fmem_pdata.size) { + apq8064_fmem_pdata.reserved_size_low = fixed_low_size; + apq8064_fmem_pdata.reserved_size_high = fixed_high_size; + } + + /* Since the fixed area may be carved out of lowmem, + * make sure the length is a multiple of 1M. + */ + fixed_size = (fixed_size + MSM_MM_FW_SIZE + SECTION_SIZE - 1) + & SECTION_MASK; + apq8064_reserve_fixed_area(fixed_size); + + fixed_low_start = APQ8064_FIXED_AREA_START; + fixed_middle_start = fixed_low_start + fixed_low_size; + fixed_high_start = fixed_middle_start + fixed_middle_size; + + for (i = 0; i < apq8064_ion_pdata.nr; ++i) { + struct ion_platform_heap *heap = &(apq8064_ion_pdata.heaps[i]); + + if (heap->extra_data) { + int fixed_position = NOT_FIXED; + + switch (heap->type) { + case ION_HEAP_TYPE_CP: + fixed_position = ((struct ion_cp_heap_pdata *) + heap->extra_data)->fixed_position; + break; + case ION_HEAP_TYPE_CARVEOUT: + fixed_position = ((struct ion_co_heap_pdata *) + heap->extra_data)->fixed_position; + break; + default: + break; + } + + switch (fixed_position) { + case FIXED_LOW: + heap->base = fixed_low_start; + break; + case FIXED_MIDDLE: + heap->base = fixed_middle_start; + break; + case FIXED_HIGH: + heap->base = fixed_high_start; + break; + default: + break; + } + } + } +#endif +} + +static void __init reserve_mdp_memory(void) +{ + apq8064_mdp_writeback(apq8064_reserve_table); +} + +static void __init apq8064_calculate_reserve_sizes(void) +{ + size_pmem_devices(); + reserve_pmem_memory(); + reserve_ion_memory(); + reserve_mdp_memory(); + reserve_rtb_memory(); +} + +static struct reserve_info apq8064_reserve_info __initdata = { + .memtype_reserve_table = apq8064_reserve_table, + .calculate_reserve_sizes = apq8064_calculate_reserve_sizes, + .reserve_fixed_area = apq8064_reserve_fixed_area, + .paddr_to_memtype = apq8064_paddr_to_memtype, +}; + +static int apq8064_memory_bank_size(void) +{ + return 1<<29; +} + +static void __init locate_unstable_memory(void) +{ + struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1]; + unsigned long bank_size; + unsigned long low, high; + + bank_size = apq8064_memory_bank_size(); + low = meminfo.bank[0].start; + high = mb->start + mb->size; + + /* Check if 32 bit overflow occured */ + if (high < mb->start) + high = -PAGE_SIZE; + + low &= ~(bank_size - 1); + + if (high - low <= bank_size) + goto no_dmm; + +#ifdef CONFIG_ENABLE_DMM + apq8064_reserve_info.low_unstable_address = mb->start - + MIN_MEMORY_BLOCK_SIZE + mb->size; + apq8064_reserve_info.max_unstable_size = MIN_MEMORY_BLOCK_SIZE; + + apq8064_reserve_info.bank_size = bank_size; + pr_info("low unstable address %lx max size %lx bank size %lx\n", + apq8064_reserve_info.low_unstable_address, + apq8064_reserve_info.max_unstable_size, + apq8064_reserve_info.bank_size); + return; +#endif +no_dmm: + apq8064_reserve_info.low_unstable_address = high; + apq8064_reserve_info.max_unstable_size = 0; +} + +static int apq8064_change_memory_power(u64 start, u64 size, + int change_type) +{ + return soc_change_memory_power(start, size, change_type); +} + +static char prim_panel_name[PANEL_NAME_MAX_LEN]; +static char ext_panel_name[PANEL_NAME_MAX_LEN]; +static int __init prim_display_setup(char *param) +{ + if (strnlen(param, PANEL_NAME_MAX_LEN)) + strlcpy(prim_panel_name, param, PANEL_NAME_MAX_LEN); + return 0; +} +early_param("prim_display", prim_display_setup); + +static int __init ext_display_setup(char *param) +{ + if (strnlen(param, PANEL_NAME_MAX_LEN)) + strlcpy(ext_panel_name, param, PANEL_NAME_MAX_LEN); + return 0; +} +early_param("ext_display", ext_display_setup); + +static void __init apq8064_reserve(void) +{ + msm_reserve(); + if (apq8064_fmem_pdata.size) { +#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION) + if (reserve_info->fixed_area_size) { + apq8064_fmem_pdata.phys = + reserve_info->fixed_area_start + MSM_MM_FW_SIZE; + pr_info("mm fw at %lx (fixed) size %x\n", + reserve_info->fixed_area_start, MSM_MM_FW_SIZE); + pr_info("fmem start %lx (fixed) size %lx\n", + apq8064_fmem_pdata.phys, + apq8064_fmem_pdata.size); + } +#endif + } +} + +static void __init place_movable_zone(void) +{ +#ifdef CONFIG_ENABLE_DMM + movable_reserved_start = apq8064_reserve_info.low_unstable_address; + movable_reserved_size = apq8064_reserve_info.max_unstable_size; + pr_info("movable zone start %lx size %lx\n", + movable_reserved_start, movable_reserved_size); +#endif +} + +static void __init apq8064_early_reserve(void) +{ + reserve_info = &apq8064_reserve_info; + locate_unstable_memory(); + place_movable_zone(); +} +#ifdef CONFIG_USB_EHCI_MSM_HSIC +/* Bandwidth requests (zero) if no vote placed */ +static struct msm_bus_vectors hsic_init_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_SPS, + .ab = 0, + .ib = 0, + }, +}; + +/* Bus bandwidth requests in Bytes/sec */ +static struct msm_bus_vectors hsic_max_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 60000000, /* At least 480Mbps on bus. */ + .ib = 960000000, /* MAX bursts rate */ + }, + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_SPS, + .ab = 0, + .ib = 512000000, /*vote for 64Mhz dfab clk rate*/ + }, +}; + +static struct msm_bus_paths hsic_bus_scale_usecases[] = { + { + ARRAY_SIZE(hsic_init_vectors), + hsic_init_vectors, + }, + { + ARRAY_SIZE(hsic_max_vectors), + hsic_max_vectors, + }, +}; + +static struct msm_bus_scale_pdata hsic_bus_scale_pdata = { + hsic_bus_scale_usecases, + ARRAY_SIZE(hsic_bus_scale_usecases), + .name = "hsic", +}; + +static struct msm_hsic_host_platform_data msm_hsic_pdata = { + .strobe = 88, + .data = 89, + .bus_scale_table = &hsic_bus_scale_pdata, +}; +#else +static struct msm_hsic_host_platform_data msm_hsic_pdata; +#endif + +#define PID_MAGIC_ID 0x71432909 +#define SERIAL_NUM_MAGIC_ID 0x61945374 +#define SERIAL_NUMBER_LENGTH 127 +#define DLOAD_USB_BASE_ADD 0x2A03F0C8 + +struct magic_num_struct { + uint32_t pid; + uint32_t serial_num; +}; + +struct dload_struct { + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; + uint16_t reserved4; + uint16_t pid; + char serial_number[SERIAL_NUMBER_LENGTH]; + uint16_t reserved5; + struct magic_num_struct magic_struct; +}; + +static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum) +{ + struct dload_struct __iomem *dload = 0; + + dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload)); + if (!dload) { + pr_err("%s: cannot remap I/O memory region: %08x\n", + __func__, DLOAD_USB_BASE_ADD); + return -ENXIO; + } + + pr_debug("%s: dload:%p pid:%x serial_num:%s\n", + __func__, dload, pid, snum); + /* update pid */ + dload->magic_struct.pid = PID_MAGIC_ID; + dload->pid = pid; + + /* update serial number */ + dload->magic_struct.serial_num = 0; + if (!snum) { + memset(dload->serial_number, 0, SERIAL_NUMBER_LENGTH); + goto out; + } + + dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID; + strlcpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH); +out: + iounmap(dload); + return 0; +} + +static struct android_usb_platform_data android_usb_pdata = { + .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num, +}; + +static struct platform_device android_usb_device = { + .name = "android_usb", + .id = -1, + .dev = { + .platform_data = &android_usb_pdata, + }, +}; + +#ifdef CONFIG_USB_G_LGE_ANDROID +static int get_factory_cable(void) +{ + struct chg_cable_info info; + enum lge_boot_mode_type boot_mode; + int res; + + /* get cable infomation */ + res = lge_pm_get_cable_info(&info); + if (res < 0) { + pr_err("Error get cable information from PMIC %d\n", res); + return 0; + } + + switch(info.cable_type) { + /* It is factory cable */ + case CABLE_56K: + res = LGEUSB_FACTORY_56K; + break; + case CABLE_130K: + res = LGEUSB_FACTORY_130K; + break; + case CABLE_910K: + res = LGEUSB_FACTORY_910K; + break; + /* It is normal cable */ + default: + res = 0; + break; + } + + /* if boot mode is factory, + * cable must be factory cable. + */ + boot_mode = lge_get_boot_mode(); + switch(boot_mode) { + case LGE_BOOT_MODE_FACTORY: + res = LGEUSB_FACTORY_130K; + break; + case LGE_BOOT_MODE_FACTORY2: + //case LGE_BOOT_MODE_PIFBOOT: + res = LGEUSB_FACTORY_56K; + break; + default: + break; + } + + return res; +} + +struct lge_android_usb_platform_data lge_android_usb_pdata = { + .vendor_id = 0x1004, + .factory_pid = 0x6000, + .iSerialNumber = 0, + .product_name = "LGE Android Phone", + .manufacturer_name = "LG Electronics Inc.", + .factory_composition = "acm,diag", + .get_factory_cable = get_factory_cable, +}; + +struct platform_device lge_android_usb_device = { + .name = "lge_android_usb", + .id = -1, + .dev = { + .platform_data = &lge_android_usb_pdata, + }, +}; +#endif /* CONFIG_USB_G_LGE_ANDROID */ + +/* Bandwidth requests (zero) if no vote placed */ +static struct msm_bus_vectors usb_init_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 0, + .ib = 0, + }, +}; + +/* Bus bandwidth requests in Bytes/sec */ +static struct msm_bus_vectors usb_max_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ab = 60000000, /* At least 480Mbps on bus. */ + .ib = 960000000, /* MAX bursts rate */ + }, +}; + +static struct msm_bus_paths usb_bus_scale_usecases[] = { + { + ARRAY_SIZE(usb_init_vectors), + usb_init_vectors, + }, + { + ARRAY_SIZE(usb_max_vectors), + usb_max_vectors, + }, +}; + +static struct msm_bus_scale_pdata usb_bus_scale_pdata = { + usb_bus_scale_usecases, + ARRAY_SIZE(usb_bus_scale_usecases), + .name = "usb", +}; + +static int phy_init_seq[] = { + 0x38, 0x81, /* update DC voltage level */ + 0x24, 0x82, /* set pre-emphasis and rise/fall time */ + 0x33, 0x83, /* set source impedance adjusment */ + -1 +}; + +static struct msm_otg_platform_data msm_otg_pdata = { + .mode = USB_OTG, + .otg_control = OTG_PMIC_CONTROL, + .phy_type = SNPS_28NM_INTEGRATED_PHY, + .pmic_id_irq = PM8921_USB_ID_IN_IRQ(PM8921_IRQ_BASE), + .power_budget = 750, + .bus_scale_table = &usb_bus_scale_pdata, + .phy_init_seq = phy_init_seq, +}; + +static struct msm_usb_host_platform_data msm_ehci_host_pdata3 = { + .power_budget = 500, +}; + +#ifdef CONFIG_USB_EHCI_MSM_HOST4 +static struct msm_usb_host_platform_data msm_ehci_host_pdata4; +#endif + +static void __init apq8064_ehci_host_init(void) +{ + if (machine_is_apq8064_liquid() || machine_is_mpq8064_cdp() || + machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()) { + if (machine_is_apq8064_liquid()) + msm_ehci_host_pdata3.dock_connect_irq = + PM8921_MPP_IRQ(PM8921_IRQ_BASE, 9); + + apq8064_device_ehci_host3.dev.platform_data = + &msm_ehci_host_pdata3; + platform_device_register(&apq8064_device_ehci_host3); + +#ifdef CONFIG_USB_EHCI_MSM_HOST4 + apq8064_device_ehci_host4.dev.platform_data = + &msm_ehci_host_pdata4; + platform_device_register(&apq8064_device_ehci_host4); +#endif + } +} +#ifdef CONFIG_SMB349_CHARGER +static struct smb349_platform_data smb349_data __initdata = { + .en_n_gpio = PM8921_GPIO_PM_TO_SYS(37), + .chg_susp_gpio = PM8921_GPIO_PM_TO_SYS(30), + .chg_current_ma = 2200, +}; + +static struct i2c_board_info smb349_charger_i2c_info[] __initdata = { + { + I2C_BOARD_INFO(SMB349_NAME, 0x1B), + .platform_data = &smb349_data, + }, +}; +#endif + +struct sx150x_platform_data apq8064_sx150x_data[] = { + [SX150X_EPM] = { + .gpio_base = GPIO_EPM_EXPANDER_BASE, + .oscio_is_gpo = false, + .io_pullup_ena = 0x0, + .io_pulldn_ena = 0x0, + .io_open_drain_ena = 0x0, + .io_polarity = 0, + .irq_summary = -1, + }, +}; + +#ifdef CONFIG_SENSORS_EPM_ADC +static struct epm_chan_properties ads_adc_channel_data[] = { + {10, 100}, {500, 50}, {1, 1}, {1, 1}, + {20, 50}, {10, 100}, {1, 1}, {1, 1}, + {10, 100}, {10, 100}, {100, 100}, {200, 100}, + {100, 50}, {2000, 50}, {1000, 50}, {200, 50}, + {200, 100}, {1, 1}, {20, 50}, {500, 50}, + {50, 50}, {200, 100}, {500, 100}, {20, 50}, + {200, 50}, {2000, 100}, {1000, 50}, {100, 50}, + {200, 100}, {500, 50}, {1000, 100}, {200, 50}, + {1000, 50}, {50, 50}, {100, 50}, {100, 50}, + {1, 1}, {1, 1}, {20, 100}, {20, 50}, + {500, 100}, {1000, 100}, {100, 50}, {1000, 50}, + {100, 50}, {1000, 100}, {100, 50}, {100, 50}, +}; + +static struct epm_adc_platform_data epm_adc_pdata = { + .channel = ads_adc_channel_data, + .bus_id = 0x0, + .epm_i2c_board_info = { + .type = "sx1509q", + .addr = 0x3e, + .platform_data = &apq8064_sx150x_data[SX150X_EPM], + }, + .gpio_expander_base_addr = GPIO_EPM_EXPANDER_BASE, +}; + +static struct platform_device epm_adc_device = { + .name = "epm_adc", + .id = -1, + .dev = { + .platform_data = &epm_adc_pdata, + }, +}; + +static void __init apq8064_epm_adc_init(void) +{ + epm_adc_pdata.num_channels = 32; + epm_adc_pdata.num_adc = 2; + epm_adc_pdata.chan_per_adc = 16; + epm_adc_pdata.chan_per_mux = 8; +}; +#endif + +/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement + * 4 micbiases are used to power various analog and digital + * microphones operating at 1800 mV. Technically, all micbiases + * can source from single cfilter since all microphones operate + * at the same voltage level. The arrangement below is to make + * sure all cfilters are exercised. LDO_H regulator ouput level + * does not need to be as high as 2.85V. It is choosen for + * microphone sensitivity purpose. + */ + +static struct wcd9xxx_pdata apq8064_tabla20_platform_data = { + .slimbus_slave_device = { + .name = "tabla-slave", + .e_addr = {0, 0, 0x60, 0, 0x17, 2}, + }, + .irq = MSM_GPIO_TO_INT(42), + .irq_base = TABLA_INTERRUPT_BASE, + .num_irqs = NR_WCD9XXX_IRQS, + .reset_gpio = PM8921_GPIO_PM_TO_SYS(34), + .micbias = { + .ldoh_v = TABLA_LDOH_2P85_V, + .cfilt1_mv = 1800, + .cfilt2_mv = 1800, + .cfilt3_mv = 1800, + .bias1_cfilt_sel = TABLA_CFILT1_SEL, + .bias2_cfilt_sel = TABLA_CFILT2_SEL, + .bias3_cfilt_sel = TABLA_CFILT3_SEL, + .bias4_cfilt_sel = TABLA_CFILT3_SEL, + }, + .regulator = { + { + .name = "CDC_VDD_CP", + .min_uV = 1800000, + .max_uV = 1800000, + .optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX, + }, + { + .name = "CDC_VDDA_RX", + .min_uV = 1800000, + .max_uV = 1800000, + .optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX, + }, + { + .name = "CDC_VDDA_TX", + .min_uV = 1800000, + .max_uV = 1800000, + .optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX, + }, + { + .name = "VDDIO_CDC", + .min_uV = 1800000, + .max_uV = 1800000, + .optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX, + }, + { + .name = "VDDD_CDC_D", + .min_uV = 1225000, + .max_uV = 1225000, + .optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX, + }, + { + .name = "CDC_VDDA_A_1P2V", + .min_uV = 1225000, + .max_uV = 1225000, + .optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX, + }, + }, +}; + +static struct slim_device apq8064_slim_tabla20 = { + .name = "tabla2x-slim", + .e_addr = {0, 1, 0x60, 0, 0x17, 2}, + .dev = { + .platform_data = &apq8064_tabla20_platform_data, + }, +}; + +#ifdef CONFIG_SND_SOC_CS8427 +/* enable the level shifter for cs8427 to make sure the I2C + * clock is running at 100KHz and voltage levels are at 3.3 + * and 5 volts + */ +static int enable_100KHz_ls(int enable) +{ + int ret = 0; + if (enable) { + ret = gpio_request(SX150X_GPIO(1, 10), + "cs8427_100KHZ_ENABLE"); + if (ret) { + pr_err("%s: Failed to request gpio %d\n", __func__, + SX150X_GPIO(1, 10)); + return ret; + } + gpio_direction_output(SX150X_GPIO(1, 10), 1); + } else + gpio_free(SX150X_GPIO(1, 10)); + return ret; +} + +static struct cs8427_platform_data cs8427_i2c_platform_data = { + .irq = SX150X_GPIO(1, 4), + .reset_gpio = SX150X_GPIO(1, 6), + .enable = enable_100KHz_ls, +}; + +static struct i2c_board_info cs8427_device_info[] __initdata = { + { + I2C_BOARD_INFO("cs8427", CS8427_ADDR4), + .platform_data = &cs8427_i2c_platform_data, + }, +}; +#endif + +/* configuration data for mxt1386e using V2.1 firmware */ +static const u8 mxt1386e_config_data_v2_1[] = { + /* T6 Object */ + 0, 0, 0, 0, 0, 0, + /* T38 Object */ + 14, 2, 0, 24, 5, 12, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + /* T7 Object */ + 100, 10, 50, + /* T8 Object */ + 25, 0, 20, 20, 0, 0, 0, 0, 0, 0, + /* T9 Object */ + 139, 0, 0, 26, 42, 0, 32, 80, 2, 5, + 0, 5, 5, 0, 10, 30, 10, 10, 255, 2, + 85, 5, 0, 5, 9, 5, 12, 35, 70, 40, + 20, 5, 0, 0, 0, + /* T18 Object */ + 0, 0, + /* T24 Object */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* T25 Object */ + 1, 0, 60, 115, 156, 99, + /* T27 Object */ + 0, 0, 0, 0, 0, 0, 0, + /* T40 Object */ + 0, 0, 0, 0, 0, + /* T42 Object */ + 0, 0, 255, 0, 255, 0, 0, 0, 0, 0, + /* T43 Object */ + 0, 0, 0, 0, 0, 0, 0, 64, 0, 8, + 16, + /* T46 Object */ + 68, 0, 16, 16, 0, 0, 0, 0, 0, + /* T47 Object */ + 0, 0, 0, 0, 0, 0, 3, 64, 66, 0, + /* T48 Object */ + 1, 64, 64, 0, 0, 0, 0, 0, 0, 0, + 32, 40, 0, 10, 10, 0, 0, 100, 10, 90, + 0, 0, 0, 0, 0, 0, 0, 10, 1, 10, + 52, 10, 12, 0, 33, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + /* T56 Object */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, +}; + +#define MSM_WCNSS_PHYS 0x03000000 +#define MSM_WCNSS_SIZE 0x280000 + +static struct resource resources_wcnss_wlan[] = { + { + .start = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ, + .end = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ, + .name = "wcnss_wlanrx_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ, + .end = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ, + .name = "wcnss_wlantx_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_WCNSS_PHYS, + .end = MSM_WCNSS_PHYS + MSM_WCNSS_SIZE - 1, + .name = "wcnss_mmio", + .flags = IORESOURCE_MEM, + }, + { + .start = 64, + .end = 68, + .name = "wcnss_gpios_5wire", + .flags = IORESOURCE_IO, + }, +}; + +static struct qcom_wcnss_opts qcom_wcnss_pdata = { + .has_48mhz_xo = 1, +}; + +static struct platform_device msm_device_wcnss_wlan = { + .name = "wcnss_wlan", + .id = 0, + .num_resources = ARRAY_SIZE(resources_wcnss_wlan), + .resource = resources_wcnss_wlan, + .dev = {.platform_data = &qcom_wcnss_pdata}, +}; + +#ifdef CONFIG_RADIO_IRIS +static struct platform_device msm_device_iris_fm __devinitdata = { + .name = "iris_fm", + .id = -1, +}; +#endif + +#ifdef CONFIG_QSEECOM +/* qseecom bus scaling */ +static struct msm_bus_vectors qseecom_clks_init_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ib = 0, + .ab = 0, + }, + { + .src = MSM_BUS_MASTER_SPDM, + .dst = MSM_BUS_SLAVE_SPDM, + .ib = 0, + .ab = 0, + }, +}; + +static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ib = (492 * 8) * 1000000UL, + .ab = (492 * 8) * 100000UL, + }, + { + .src = MSM_BUS_MASTER_SPDM, + .dst = MSM_BUS_SLAVE_SPDM, + .ib = 0, + .ab = 0, + }, +}; + +static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = { + { + .src = MSM_BUS_MASTER_SPS, + .dst = MSM_BUS_SLAVE_EBI_CH0, + .ib = 0, + .ab = 0, + }, + { + .src = MSM_BUS_MASTER_SPDM, + .dst = MSM_BUS_SLAVE_SPDM, + .ib = (64 * 8) * 1000000UL, + .ab = (64 * 8) * 100000UL, + }, +}; + +static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = { + { + ARRAY_SIZE(qseecom_clks_init_vectors), + qseecom_clks_init_vectors, + }, + { + ARRAY_SIZE(qseecom_enable_dfab_vectors), + qseecom_enable_sfpb_vectors, + }, + { + ARRAY_SIZE(qseecom_enable_sfpb_vectors), + qseecom_enable_sfpb_vectors, + }, +}; + +static struct msm_bus_scale_pdata qseecom_bus_pdata = { + qseecom_hw_bus_scale_usecases, + ARRAY_SIZE(qseecom_hw_bus_scale_usecases), + .name = "qsee", +}; + +static struct platform_device qseecom_device = { + .name = "qseecom", + .id = 0, + .dev = { + .platform_data = &qseecom_bus_pdata, + }, +}; +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + +#define QCE_SIZE 0x10000 +#define QCE_0_BASE 0x11000000 + +#define QCE_HW_KEY_SUPPORT 0 +#define QCE_SHA_HMAC_SUPPORT 1 +#define QCE_SHARE_CE_RESOURCE 3 +#define QCE_CE_SHARED 0 + +static struct resource qcrypto_resources[] = { + [0] = { + .start = QCE_0_BASE, + .end = QCE_0_BASE + QCE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "crypto_channels", + .start = DMOV8064_CE_IN_CHAN, + .end = DMOV8064_CE_OUT_CHAN, + .flags = IORESOURCE_DMA, + }, + [2] = { + .name = "crypto_crci_in", + .start = DMOV8064_CE_IN_CRCI, + .end = DMOV8064_CE_IN_CRCI, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "crypto_crci_out", + .start = DMOV8064_CE_OUT_CRCI, + .end = DMOV8064_CE_OUT_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource qcedev_resources[] = { + [0] = { + .start = QCE_0_BASE, + .end = QCE_0_BASE + QCE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "crypto_channels", + .start = DMOV8064_CE_IN_CHAN, + .end = DMOV8064_CE_OUT_CHAN, + .flags = IORESOURCE_DMA, + }, + [2] = { + .name = "crypto_crci_in", + .start = DMOV8064_CE_IN_CRCI, + .end = DMOV8064_CE_IN_CRCI, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "crypto_crci_out", + .start = DMOV8064_CE_OUT_CRCI, + .end = DMOV8064_CE_OUT_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) + +static struct msm_ce_hw_support qcrypto_ce_hw_suppport = { + .ce_shared = QCE_CE_SHARED, + .shared_ce_resource = QCE_SHARE_CE_RESOURCE, + .hw_key_support = QCE_HW_KEY_SUPPORT, + .sha_hmac = QCE_SHA_HMAC_SUPPORT, + .bus_scale_table = NULL, +}; + +static struct platform_device qcrypto_device = { + .name = "qcrypto", + .id = 0, + .num_resources = ARRAY_SIZE(qcrypto_resources), + .resource = qcrypto_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &qcrypto_ce_hw_suppport, + }, +}; +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + +static struct msm_ce_hw_support qcedev_ce_hw_suppport = { + .ce_shared = QCE_CE_SHARED, + .shared_ce_resource = QCE_SHARE_CE_RESOURCE, + .hw_key_support = QCE_HW_KEY_SUPPORT, + .sha_hmac = QCE_SHA_HMAC_SUPPORT, + .bus_scale_table = NULL, +}; + +static struct platform_device qcedev_device = { + .name = "qce", + .id = 0, + .num_resources = ARRAY_SIZE(qcedev_resources), + .resource = qcedev_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &qcedev_ce_hw_suppport, + }, +}; +#endif + +static struct mdm_platform_data mdm_platform_data = { + .mdm_version = "3.0", + .ramdump_delay_ms = 2000, + .early_power_on = 1, + .sfr_query = 1, + .peripheral_platform_device = &apq8064_device_hsic_host, +}; + +static struct tsens_platform_data apq_tsens_pdata = { + .tsens_factor = 1000, + .hw_type = APQ_8064, + .tsens_num_sensor = 11, + .slope = {1176, 1176, 1154, 1176, 1111, + 1132, 1132, 1199, 1132, 1199, 1132}, +}; + +static struct platform_device msm_tsens_device = { + .name = "tsens8960-tm", + .id = -1, +}; + +#define MSM_SHARED_RAM_PHYS 0x80000000 +static void __init apq8064_map_io(void) +{ + msm_shared_ram_phys = MSM_SHARED_RAM_PHYS; + msm_map_apq8064_io(); + if (socinfo_init() < 0) + pr_err("socinfo_init() failed!\n"); +} + +static void __init apq8064_init_irq(void) +{ + struct msm_mpm_device_data *data = NULL; + +#ifdef CONFIG_MSM_MPM + data = &apq8064_mpm_dev_data; +#endif + + msm_mpm_irq_extn_init(data); + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); +} + +static struct platform_device msm8064_device_saw_regulator_core0 = { + .name = "saw-regulator", + .id = 0, + .dev = { + .platform_data = &msm8064_saw_regulator_pdata_8921_s5, + }, +}; + +static struct platform_device msm8064_device_saw_regulator_core1 = { + .name = "saw-regulator", + .id = 1, + .dev = { + .platform_data = &msm8064_saw_regulator_pdata_8921_s6, + }, +}; + +static struct platform_device msm8064_device_saw_regulator_core2 = { + .name = "saw-regulator", + .id = 2, + .dev = { + .platform_data = &msm8064_saw_regulator_pdata_8821_s0, + }, +}; + +static struct platform_device msm8064_device_saw_regulator_core3 = { + .name = "saw-regulator", + .id = 3, + .dev = { + .platform_data = &msm8064_saw_regulator_pdata_8821_s1, + + }, +}; + +static struct msm_rpmrs_level msm_rpmrs_levels[] = { + { + MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT, + MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE), + true, + 1, 784, 180000, 100, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE, + MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE), + true, + 1300, 228, 1200000, 2000, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE), + false, + 2000, 138, 1208400, 3200, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(ON, HSFS_OPEN, ACTIVE, RET_HIGH), + false, + 6000, 119, 1850300, 9000, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE), + false, + 9200, 68, 2839200, 16400, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE), + false, + 10300, 63, 3128000, 18200, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH), + false, + 18000, 10, 4602600, 27000, + }, + + { + MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW), + false, + 20000, 2, 5752000, 32000, + }, +}; + +static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = { + .mode = MSM_PM_BOOT_CONFIG_TZ, +}; + +static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = { + .levels = &msm_rpmrs_levels[0], + .num_levels = ARRAY_SIZE(msm_rpmrs_levels), + .vdd_mem_levels = { + [MSM_RPMRS_VDD_MEM_RET_LOW] = 750000, + [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000, + [MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000, + [MSM_RPMRS_VDD_MEM_MAX] = 1150000, + }, + .vdd_dig_levels = { + [MSM_RPMRS_VDD_DIG_RET_LOW] = 500000, + [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000, + [MSM_RPMRS_VDD_DIG_ACTIVE] = 950000, + [MSM_RPMRS_VDD_DIG_MAX] = 1150000, + }, + .vdd_mask = 0x7FFFFF, + .rpmrs_target_id = { + [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK, + [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST, + [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0, + [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1, + [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0, + [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1, + [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL, + }, +}; + +static uint8_t spm_wfi_cmd_sequence[] __initdata = { + 0x03, 0x0f, +}; + +static uint8_t spm_power_collapse_without_rpm[] __initdata = { + 0x00, 0x24, 0x54, 0x10, + 0x09, 0x03, 0x01, + 0x10, 0x54, 0x30, 0x0C, + 0x24, 0x30, 0x0f, +}; + +static uint8_t spm_power_collapse_with_rpm[] __initdata = { + 0x00, 0x24, 0x54, 0x10, + 0x09, 0x07, 0x01, 0x0B, + 0x10, 0x54, 0x30, 0x0C, + 0x24, 0x30, 0x0f, +}; + +static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = { + [0] = { + .mode = MSM_SPM_MODE_CLOCK_GATING, + .notify_rpm = false, + .cmd = spm_wfi_cmd_sequence, + }, + [1] = { + .mode = MSM_SPM_MODE_POWER_COLLAPSE, + .notify_rpm = false, + .cmd = spm_power_collapse_without_rpm, + }, + [2] = { + .mode = MSM_SPM_MODE_POWER_COLLAPSE, + .notify_rpm = true, + .cmd = spm_power_collapse_with_rpm, + }, +}; + +static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = { + 0x00, 0x20, 0x03, 0x20, + 0x00, 0x0f, +}; + +static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = { + 0x00, 0x20, 0x34, 0x64, + 0x48, 0x07, 0x48, 0x20, + 0x50, 0x64, 0x04, 0x34, + 0x50, 0x0f, +}; +static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = { + 0x00, 0x10, 0x34, 0x64, + 0x48, 0x07, 0x48, 0x10, + 0x50, 0x64, 0x04, 0x34, + 0x50, 0x0F, +}; + +static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = { + [0] = { + .mode = MSM_SPM_L2_MODE_RETENTION, + .notify_rpm = false, + .cmd = l2_spm_wfi_cmd_sequence, + }, + [1] = { + .mode = MSM_SPM_L2_MODE_GDHS, + .notify_rpm = true, + .cmd = l2_spm_gdhs_cmd_sequence, + }, + [2] = { + .mode = MSM_SPM_L2_MODE_POWER_COLLAPSE, + .notify_rpm = true, + .cmd = l2_spm_power_off_cmd_sequence, + }, +}; + + +static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = { + [0] = { + .reg_base_addr = MSM_SAW_L2_BASE, + .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020, + .modes = msm_spm_l2_seq_list, + .num_modes = ARRAY_SIZE(msm_spm_l2_seq_list), + }, +}; + +static struct msm_spm_platform_data msm_spm_data[] __initdata = { + [0] = { + .reg_base_addr = MSM_SAW0_BASE, + .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F, +#if defined(CONFIG_MSM_AVS_HW) + .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00, + .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00, +#endif + .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C, + .vctl_timeout_us = 50, + .num_modes = ARRAY_SIZE(msm_spm_seq_list), + .modes = msm_spm_seq_list, + }, + [1] = { + .reg_base_addr = MSM_SAW1_BASE, + .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F, +#if defined(CONFIG_MSM_AVS_HW) + .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00, + .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00, +#endif + .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C, + .vctl_timeout_us = 50, + .num_modes = ARRAY_SIZE(msm_spm_seq_list), + .modes = msm_spm_seq_list, + }, + [2] = { + .reg_base_addr = MSM_SAW2_BASE, + .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F, +#if defined(CONFIG_MSM_AVS_HW) + .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00, + .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00, +#endif + .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C, + .vctl_timeout_us = 50, + .num_modes = ARRAY_SIZE(msm_spm_seq_list), + .modes = msm_spm_seq_list, + }, + [3] = { + .reg_base_addr = MSM_SAW3_BASE, + .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F, +#if defined(CONFIG_MSM_AVS_HW) + .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00, + .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00, +#endif + .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C, + .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C, + .vctl_timeout_us = 50, + .num_modes = ARRAY_SIZE(msm_spm_seq_list), + .modes = msm_spm_seq_list, + }, +}; + +static struct msm_pm_sleep_status_data msm_pm_slp_sts_data = { + .base_addr = MSM_ACC0_BASE + 0x08, + .cpu_offset = MSM_ACC1_BASE - MSM_ACC0_BASE, + .mask = 1UL << 13, +}; + +#define GSBI_I2C_MODE_CODE 0x20 +#define GSBI_DUAL_MODE_CODE 0x60 +#define MSM_GSBI1_PHYS 0x12440000 +#define MSM_GSBI4_PHYS 0x16300000 + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) +#define MSM_GSBI6_PHYS 0x16500000 +static struct msm_serial_hslite_platform_data apq8064_felica_gsbi6_pdata = { + .config_gpio = 1, + .uart_tx_gpio = 14, + .uart_rx_gpio = 15, + .line = 2, +}; +#endif + +static void __init apq8064_init_buses(void) +{ +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) + void __iomem *gsbi6_mem; +#endif + + msm_bus_rpm_set_mt_mask(); + msm_bus_8064_apps_fabric_pdata.rpm_enabled = 1; + msm_bus_8064_sys_fabric_pdata.rpm_enabled = 1; + msm_bus_8064_mm_fabric_pdata.rpm_enabled = 1; + msm_bus_8064_apps_fabric.dev.platform_data = + &msm_bus_8064_apps_fabric_pdata; + msm_bus_8064_sys_fabric.dev.platform_data = + &msm_bus_8064_sys_fabric_pdata; + msm_bus_8064_mm_fabric.dev.platform_data = + &msm_bus_8064_mm_fabric_pdata; + msm_bus_8064_sys_fpb.dev.platform_data = &msm_bus_8064_sys_fpb_pdata; + msm_bus_8064_cpss_fpb.dev.platform_data = &msm_bus_8064_cpss_fpb_pdata; + + /* Set dual mode (I2C/UART) for GSBI_4/6 */ +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) + gsbi6_mem = ioremap_nocache(MSM_GSBI6_PHYS, 4); + writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi6_mem); + wmb(); + iounmap(gsbi6_mem); + apq8064_device_felica_gsbi6.dev.platform_data = &apq8064_felica_gsbi6_pdata; +#endif +} + +/* PCIe gpios */ +static struct msm_pcie_gpio_info_t msm_pcie_gpio_info[MSM_PCIE_MAX_GPIO] = { + {"rst_n", PM8921_MPP_PM_TO_SYS(PCIE_RST_N_PMIC_MPP), 0}, + {"pwr_en", PM8921_GPIO_PM_TO_SYS(PCIE_PWR_EN_PMIC_GPIO), 1}, +}; + +static struct msm_pcie_platform msm_pcie_platform_data = { + .gpio = msm_pcie_gpio_info, +}; + +static void __init mpq8064_pcie_init(void) +{ + msm_device_pcie.dev.platform_data = &msm_pcie_platform_data; + platform_device_register(&msm_device_pcie); +} + +static struct platform_device apq8064_device_rpm_regulator __devinitdata = { + .name = "rpm-regulator", + .id = -1, + .dev = { + .platform_data = &apq8064_rpm_regulator_pdata, + }, +}; +#ifdef CONFIG_IR_GPIO_CIR +static struct gpio_ir_recv_platform_data gpio_ir_recv_pdata = { + .gpio_nr = 88, + .active_low = 1, +}; + +static struct platform_device gpio_ir_recv_pdev = { + .name = "gpio-rc-recv", + .dev = { + .platform_data = &gpio_ir_recv_pdata, + }, +}; +#endif +static struct platform_device *common_not_mpq_devices[] __initdata = { + &apq8064_device_qup_i2c_gsbi1, +#if !defined(CONFIG_MSM_DSPS) + &apq8064_device_qup_i2c_gsbi2, +#endif + &apq8064_device_qup_i2c_gsbi3, + &apq8064_device_qup_i2c_gsbi4, +}; + +static struct platform_device *common_devices[] __initdata = { + &apq8064_device_dmov, + &apq8064_device_ssbi_pmic1, + &apq8064_device_ssbi_pmic2, + &msm_device_smd_apq8064, + &apq8064_device_otg, + &apq8064_device_gadget_peripheral, + &apq8064_device_hsusb_host, + &android_usb_device, +#ifdef CONFIG_USB_G_LGE_ANDROID + &lge_android_usb_device, +#endif + &msm_device_wcnss_wlan, +#ifdef CONFIG_RADIO_IRIS + &msm_device_iris_fm, +#endif + &apq8064_fmem_device, +#ifdef CONFIG_ANDROID_PMEM +#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION + &apq8064_android_pmem_device, + &apq8064_android_pmem_adsp_device, + &apq8064_android_pmem_audio_device, +#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/ +#endif +#ifdef CONFIG_ION_MSM + &apq8064_ion_dev, +#endif + &msm8064_device_watchdog, + &msm8064_device_saw_regulator_core0, + &msm8064_device_saw_regulator_core1, + &msm8064_device_saw_regulator_core2, + &msm8064_device_saw_regulator_core3, +#if defined(CONFIG_QSEECOM) + &qseecom_device, +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) + &qcrypto_device, +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + &qcedev_device, +#endif + +#ifdef CONFIG_HW_RANDOM_MSM + &apq8064_device_rng, +#endif + &apq_pcm, + &apq_pcm_routing, + &apq_cpudai0, + &apq_cpudai1, + &mpq_cpudai_sec_i2s_rx, + &mpq_cpudai_mi2s_tx, + &apq_cpudai_hdmi_rx, + &apq_cpudai_bt_rx, + &apq_cpudai_bt_tx, + &apq_cpudai_fm_rx, + &apq_cpudai_fm_tx, + &apq_cpu_fe, + &apq_stub_codec, + &apq_voice, + &apq_voip, + &apq_lpa_pcm, + &apq_compr_dsp, + &apq_multi_ch_pcm, + &apq_pcm_hostless, + &apq_cpudai_afe_01_rx, + &apq_cpudai_afe_01_tx, + &apq_cpudai_afe_02_rx, + &apq_cpudai_afe_02_tx, + &apq_pcm_afe, + &apq_cpudai_auxpcm_rx, + &apq_cpudai_auxpcm_tx, + &apq_cpudai_stub, + &apq_cpudai_slimbus_1_rx, + &apq_cpudai_slimbus_1_tx, + &apq_cpudai_slimbus_2_tx, + &apq_cpudai_slimbus_3_rx, + &apq8064_rpm_device, + &apq8064_rpm_log_device, + &apq8064_rpm_stat_device, +#ifdef CONFIG_MSM_TZ_LOG + &msm_device_tz_log, +#endif + &msm_bus_8064_apps_fabric, + &msm_bus_8064_sys_fabric, + &msm_bus_8064_mm_fabric, + &msm_bus_8064_sys_fpb, + &msm_bus_8064_cpss_fpb, + &apq8064_msm_device_vidc, + &msm_pil_dsps, + &msm_8960_riva, + &msm_8960_q6_lpass, + &msm_pil_vidc, + &msm_gss, + &apq8064_rtb_device, + &apq8064_cpu_idle_device, + &apq8064_msm_gov_device, + &apq8064_device_cache_erp, +#ifdef CONFIG_SENSORS_EPM_ADC + &epm_adc_device, +#endif + &apq8064_qdss_device, + &msm_etb_device, + &msm_tpiu_device, + &msm_funnel_device, + &apq8064_etm_device, + &apq_cpudai_slim_4_rx, + &apq_cpudai_slim_4_tx, +#ifdef CONFIG_MSM_GEMINI + &msm8960_gemini_device, +#endif + &apq8064_iommu_domain_device, + &msm_tsens_device, +}; + +static struct platform_device *cdp_devices[] __initdata = { + &msm_device_sps_apq8064, +#ifdef CONFIG_MSM_ROTATOR + &msm_rotator_device, +#endif +}; + +static struct platform_device +mpq8064_device_ext_5v_frc_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 10), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_FRC_5V], + }, +}; + +static struct platform_device +mpq8064_device_ext_1p2_buck_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 2), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_1P2V], + }, +}; + +static struct platform_device +mpq8064_device_ext_1p8_buck_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 4), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_1P8V], + }, +}; + +static struct platform_device +mpq8064_device_ext_2p2_buck_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 14), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_2P2V], + }, +}; + +static struct platform_device +mpq8064_device_ext_5v_buck_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 3), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_5V], + }, +}; + +static struct platform_device +mpq8064_device_ext_3p3v_ldo_vreg __devinitdata = { + .name = GPIO_REGULATOR_DEV_NAME, + .id = SX150X_GPIO(4, 15), + .dev = { + .platform_data = + &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_3P3V], + }, +}; + +#ifdef CONFIG_USER_RC_INPUT +static struct platform_device rc_input_loopback_pdev = { + .name = "rc-user-input", + .id = -1, +}; +#endif + +static int rf4ce_gpio_init(void) +{ + if (!machine_is_mpq8064_cdp()) + return -EINVAL; + + /* CC2533 SRDY Input */ + if (!gpio_request(SX150X_GPIO(4, 6), "rf4ce_srdy")) { + gpio_direction_input(SX150X_GPIO(4, 6)); + gpio_export(SX150X_GPIO(4, 6), true); + } + + /* CC2533 MRDY Output */ + if (!gpio_request(SX150X_GPIO(4, 5), "rf4ce_mrdy")) { + gpio_direction_output(SX150X_GPIO(4, 5), 1); + gpio_export(SX150X_GPIO(4, 5), true); + } + + /* CC2533 Reset Output */ + if (!gpio_request(SX150X_GPIO(4, 7), "rf4ce_reset")) { + gpio_direction_output(SX150X_GPIO(4, 7), 0); + gpio_export(SX150X_GPIO(4, 7), true); + } + + return 0; +} +late_initcall(rf4ce_gpio_init); + +static struct platform_device *mpq_devices[] __initdata = { + &msm_device_sps_apq8064, +#ifdef CONFIG_MSM_ROTATOR + &msm_rotator_device, +#endif +#ifdef CONFIG_IR_GPIO_CIR + &gpio_ir_recv_pdev, +#endif + &mpq8064_device_ext_5v_frc_vreg, + &mpq8064_device_ext_1p2_buck_vreg, + &mpq8064_device_ext_1p8_buck_vreg, + &mpq8064_device_ext_2p2_buck_vreg, + &mpq8064_device_ext_5v_buck_vreg, + &mpq8064_device_ext_3p3v_ldo_vreg, +#ifdef CONFIG_MSM_VCAP + &msm8064_device_vcap, +#endif +#ifdef CONFIG_USER_RC_INPUT + &rc_input_loopback_pdev, +#endif +}; + +static struct platform_device *uart_devices[] __initdata = { + &apq8064_device_uart_gsbi4, +}; + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) +static struct platform_device *felica_uart_devices[] __initdata = { + &apq8064_device_felica_gsbi6, +}; +#endif + +static struct spi_board_info spi_board_info[] __initdata = { +#ifdef CONFIG_SENSORS_EPM_ADC + { + .modalias = "epm_adc", + .max_speed_hz = 1100000, + .bus_num = 0, + .chip_select = 3, + .mode = SPI_MODE_0, + }, +#endif +}; + +static struct slim_boardinfo apq8064_slim_devices[] = { + { + .bus_num = 1, + .slim_slave = &apq8064_slim_tabla20, + }, + /* add more slimbus slaves as needed */ +}; + +static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi1_pdata = { + .clk_freq = 400000, + .src_clk_rate = 24000000, +}; +#if !defined(CONFIG_MSM_DSPS) +static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi2_pdata = { + .clk_freq = 100000, + .src_clk_rate = 24000000, +}; +#endif + +static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi3_pdata = { + .clk_freq = 384000, + .src_clk_rate = 24000000, +}; + +static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi4_pdata = { + .clk_freq = 100000, + .src_clk_rate = 24000000, +}; + +static void __init apq8064_i2c_init(void) +{ + void __iomem *gsbi_mem; + +#if !defined(CONFIG_MSM_DSPS) + apq8064_device_qup_i2c_gsbi2.dev.platform_data = + &apq8064_i2c_qup_gsbi2_pdata; +#endif + apq8064_device_qup_i2c_gsbi1.dev.platform_data = + &apq8064_i2c_qup_gsbi1_pdata; + + gsbi_mem = ioremap_nocache(MSM_GSBI1_PHYS, 4); + writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem); + /* Ensure protocol code is written before proceeding */ + wmb(); + iounmap(gsbi_mem); + apq8064_i2c_qup_gsbi1_pdata.use_gsbi_shared_mode = 1; + apq8064_device_qup_i2c_gsbi3.dev.platform_data = + &apq8064_i2c_qup_gsbi3_pdata; + apq8064_device_qup_i2c_gsbi1.dev.platform_data = + &apq8064_i2c_qup_gsbi1_pdata; + apq8064_device_qup_i2c_gsbi4.dev.platform_data = + &apq8064_i2c_qup_gsbi4_pdata; + + /* Setting protocol code to 0x60 for dual UART/I2C in GSBI4 */ + gsbi_mem = ioremap_nocache(MSM_GSBI4_PHYS, 4); + if (lge_get_uart_mode()) { + writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem); + apq8064_i2c_qup_gsbi4_pdata.use_gsbi_shared_mode = 1; + } else { + writel_relaxed(GSBI_I2C_MODE_CODE, gsbi_mem); + } + wmb(); + iounmap(gsbi_mem); +} + +static int ethernet_init(void) +{ + return 0; +} + +/* Sensors DSPS platform data */ +#define DSPS_PIL_GENERIC_NAME "dsps" +static void __init apq8064_init_dsps(void) +{ + struct msm_dsps_platform_data *pdata = + msm_dsps_device_8064.dev.platform_data; + pdata->pil_name = DSPS_PIL_GENERIC_NAME; + pdata->gpios = NULL; + pdata->gpios_num = 0; + + platform_device_register(&msm_dsps_device_8064); +} + +#define I2C_SURF 1 +#define I2C_FFA (1 << 1) +#define I2C_RUMI (1 << 2) +#define I2C_SIM (1 << 3) +#define I2C_LIQUID (1 << 4) +#define I2C_J1V BIT(5) +#define I2C_MPQ_HRD BIT(6) +#define I2C_MPQ_DTV BIT(7) + +struct i2c_registry { + u8 machs; + int bus; + struct i2c_board_info *info; + int len; +}; + +static struct i2c_registry apq8064_i2c_devices[] __initdata = { +#ifdef CONFIG_SMB349_CHARGER + { + I2C_LIQUID, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + smb349_charger_i2c_info, + ARRAY_SIZE(smb349_charger_i2c_info) + }, +#endif +#ifdef CONFIG_SND_SOC_CS8427 + { + I2C_MPQ_CDP, + APQ_8064_GSBI5_QUP_I2C_BUS_ID, + cs8427_device_info, + ARRAY_SIZE(cs8427_device_info), + }, +#endif +}; + +#define SX150X_EXP1_INT_N PM8921_MPP_IRQ(PM8921_IRQ_BASE, 9) +#define SX150X_EXP2_INT_N MSM_GPIO_TO_INT(81) + +struct sx150x_platform_data mpq8064_sx150x_pdata[] = { + [SX150X_EXP1] = { + .gpio_base = SX150X_EXP1_GPIO_BASE, + .oscio_is_gpo = false, + .io_pullup_ena = 0x0, + .io_pulldn_ena = 0x0, + .io_open_drain_ena = 0x0, + .io_polarity = 0, + .irq_summary = SX150X_EXP1_INT_N, + .irq_base = SX150X_EXP1_IRQ_BASE, + }, + [SX150X_EXP2] = { + .gpio_base = SX150X_EXP2_GPIO_BASE, + .oscio_is_gpo = false, + .io_pullup_ena = 0x0f, + .io_pulldn_ena = 0x70, + .io_open_drain_ena = 0x0, + .io_polarity = 0, + .irq_summary = SX150X_EXP2_INT_N, + .irq_base = SX150X_EXP2_IRQ_BASE, + }, + [SX150X_EXP3] = { + .gpio_base = SX150X_EXP3_GPIO_BASE, + .oscio_is_gpo = false, + .io_pullup_ena = 0x0, + .io_pulldn_ena = 0x0, + .io_open_drain_ena = 0x0, + .io_polarity = 0, + .irq_summary = -1, + }, + [SX150X_EXP4] = { + .gpio_base = SX150X_EXP4_GPIO_BASE, + .oscio_is_gpo = false, + .io_pullup_ena = 0x0, + .io_pulldn_ena = 0x0, + .io_open_drain_ena = 0x0, + .io_polarity = 0, + .irq_summary = -1, + }, +}; + +static struct i2c_board_info sx150x_gpio_exp_info[] = { + { + I2C_BOARD_INFO("sx1509q", 0x70), + .platform_data = &mpq8064_sx150x_pdata[SX150X_EXP1], + }, + { + I2C_BOARD_INFO("sx1508q", 0x23), + .platform_data = &mpq8064_sx150x_pdata[SX150X_EXP2], + }, + { + I2C_BOARD_INFO("sx1508q", 0x22), + .platform_data = &mpq8064_sx150x_pdata[SX150X_EXP3], + }, + { + I2C_BOARD_INFO("sx1509q", 0x3E), + .platform_data = &mpq8064_sx150x_pdata[SX150X_EXP4], + }, +}; + +#define MPQ8064_I2C_GSBI5_BUS_ID 5 + +static struct i2c_registry mpq8064_i2c_devices[] __initdata = { + { + I2C_J1V, //I2C_MPQ_CDP, Fix to compile + MPQ8064_I2C_GSBI5_BUS_ID, + sx150x_gpio_exp_info, + ARRAY_SIZE(sx150x_gpio_exp_info), + }, + }; +static void __init register_i2c_devices(void) +{ + u8 mach_mask = 0; + int i; + +#ifdef CONFIG_MSM_CAMERA + struct i2c_registry apq8064_camera_i2c_devices = { + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI4_QUP_I2C_BUS_ID, + apq8064_camera_board_info.board_info, + apq8064_camera_board_info.num_i2c_board_info, + }; + /* Enabling flash LED for camera */ + struct i2c_registry apq8064_lge_camera_i2c_devices = { + I2C_SURF | I2C_FFA | I2C_RUMI | I2C_SIM | I2C_LIQUID | I2C_J1V, + APQ_8064_GSBI1_QUP_I2C_BUS_ID, + apq8064_lge_camera_board_info.board_info, + apq8064_lge_camera_board_info.num_i2c_board_info, + }; +#endif + + /* Build the matching 'supported_machs' bitmask */ + if (machine_is_apq8064_cdp()) + mach_mask = I2C_SURF; + else if (machine_is_apq8064_mtp()) + mach_mask = I2C_FFA; + else if (machine_is_apq8064_liquid()) + mach_mask = I2C_LIQUID; + else if (machine_is_apq8064_rumi3()) + mach_mask = I2C_RUMI; + else if (machine_is_apq8064_sim()) + mach_mask = I2C_SIM; + else if (PLATFORM_IS_MPQ8064()) + mach_mask = I2C_J1V; //I2C_MPQ_CDP; Fix to compile + else + pr_err("unmatched machine ID in register_i2c_devices\n"); + + /* Run the array and install devices as appropriate */ + for (i = 0; i < ARRAY_SIZE(apq8064_i2c_devices); ++i) { + if (apq8064_i2c_devices[i].machs & mach_mask) + i2c_register_board_info(apq8064_i2c_devices[i].bus, + apq8064_i2c_devices[i].info, + apq8064_i2c_devices[i].len); + } + +#ifdef CONFIG_MSM_CAMERA + if (apq8064_camera_i2c_devices.machs & mach_mask) + i2c_register_board_info(apq8064_camera_i2c_devices.bus, + apq8064_camera_i2c_devices.info, + apq8064_camera_i2c_devices.len); + /* Enabling flash LED for camera */ + if (apq8064_camera_i2c_devices.machs & mach_mask) + i2c_register_board_info(apq8064_lge_camera_i2c_devices.bus, + apq8064_lge_camera_i2c_devices.info, + apq8064_lge_camera_i2c_devices.len); +#endif + + for (i = 0; i < ARRAY_SIZE(mpq8064_i2c_devices); ++i) { + if (mpq8064_i2c_devices[i].machs & mach_mask) + i2c_register_board_info( + mpq8064_i2c_devices[i].bus, + mpq8064_i2c_devices[i].info, + mpq8064_i2c_devices[i].len); + } +} + +static void enable_avc_i2c_bus(void) +{ + int avc_i2c_en_mpp = PM8921_MPP_PM_TO_SYS(8); + int rc; + + rc = gpio_request(avc_i2c_en_mpp, "avc_i2c_en"); + if (rc) + pr_err("request for avc_i2c_en mpp failed, rc=%d\n", rc); + else + gpio_set_value_cansleep(avc_i2c_en_mpp, 1); +} + +static void __init apq8064_common_init(void) +{ + msm_tsens_early_init(&apq_tsens_pdata); + if (socinfo_init() < 0) + pr_err("socinfo_init() failed!\n"); + BUG_ON(msm_rpm_init(&apq8064_rpm_data)); + BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data)); + regulator_suppress_info_printing(); + platform_device_register(&apq8064_device_rpm_regulator); + if (msm_xo_init()) + pr_err("Failed to initialize XO votes\n"); + msm_clock_init(&apq8064_clock_init_data); + apq8064_init_gpiomux(); + apq8064_i2c_init(); + register_i2c_devices(); + register_i2c_backlight_devices(); + lge_add_sound_devices(); +#if defined(CONFIG_LGE_NFC_PN544) + lge_add_nfc_devices(); +#endif + apq8064_init_pmic(); + if (machine_is_apq8064_liquid()) + msm_otg_pdata.mhl_enable = true; + + android_usb_pdata.swfi_latency = + msm_rpmrs_levels[0].latency_us; + + apq8064_device_otg.dev.platform_data = &msm_otg_pdata; + apq8064_ehci_host_init(); + apq8064_init_buses(); + platform_add_devices(common_devices, ARRAY_SIZE(common_devices)); + if (!(machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv())) + platform_add_devices(common_not_mpq_devices, + ARRAY_SIZE(common_not_mpq_devices)); + if (machine_is_apq8064_mtp()) { + apq8064_device_hsic_host.dev.platform_data = &msm_hsic_pdata; + device_initialize(&apq8064_device_hsic_host.dev); + } + apq8064_pm8xxx_gpio_mpp_init(); + apq8064_init_mmc(); + + if (machine_is_apq8064_mtp()) { + mdm_8064_device.dev.platform_data = &mdm_platform_data; + platform_device_register(&mdm_8064_device); + } + platform_device_register(&apq8064_slim_ctrl); + slim_register_board_info(apq8064_slim_devices, + ARRAY_SIZE(apq8064_slim_devices)); + apq8064_init_dsps(); + msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data)); + acpuclk_init(&acpuclk_8064_soc_data); + msm_spm_l2_init(msm_spm_l2_data); + msm_pm_init_sleep_status_data(&msm_pm_slp_sts_data); + /**/ +#ifdef CONFIG_ANDROID_RAM_CONSOLE + lge_add_ramconsole_devices(); +#endif +#ifdef CONFIG_LGE_HANDLE_PANIC + lge_add_panic_handler_devices(); +#endif +#ifdef CONFIG_LGE_BOOT_TIME_CHECK + lge_add_boot_time_checker(); +#endif + +#ifdef CONFIG_LGE_QFPROM_INTERFACE + lge_add_qfprom_devices(); +#endif + + BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata)); +#ifdef CONFIG_SENSORS_EPM_ADC + apq8064_epm_adc_init(); +#endif +} + +static void __init apq8064_allocate_memory_regions(void) +{ + apq8064_allocate_fb_region(); +} + +static void __init apq8064_cdp_init(void) +{ + if (meminfo_init(SYS_MEMORY, SZ_256M) < 0) + pr_err("meminfo_init() failed!\n"); + apq8064_common_init(); + if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() || + machine_is_mpq8064_dtv()) { + enable_avc_i2c_bus(); + platform_add_devices(mpq_devices, ARRAY_SIZE(mpq_devices)); + mpq8064_pcie_init(); + } else { + ethernet_init(); + platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices)); + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + } + + if (lge_get_uart_mode()) + platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices)); + +#if defined(CONFIG_LGE_NFC_SONY_CXD2235AGG) + platform_add_devices(felica_uart_devices, ARRAY_SIZE(felica_uart_devices)); + pr_info("[FELICA-DEBUG] apq8064_device_uart_gsbi6.id : %d", apq8064_device_felica_gsbi6.id); +#endif + + pr_info("[NORMAL-DEBUG] apq8064_device_uart_gsbi4.id : %d", apq8064_device_uart_gsbi4.id); + pr_info("[DEBUG] uart_enable : %d", lge_get_uart_mode() ); + + apq8064_init_fb(); + apq8064_init_gpu(); + platform_add_devices(apq8064_footswitch, apq8064_num_footswitch); +#ifdef CONFIG_MSM_CAMERA + apq8064_init_cam(); +#endif + + change_memory_power = &apq8064_change_memory_power; + + apq8064_init_input(); + apq8064_init_misc(); +#ifdef CONFIG_LGE_ECO_MODE + lge_add_lge_kernel_devices(); +#endif +} + +MACHINE_START(APQ8064_MTP, "QCT APQ8064 MTP") + .map_io = apq8064_map_io, + .reserve = apq8064_reserve, + .init_irq = apq8064_init_irq, + .handle_irq = gic_handle_irq, + .timer = &msm_timer, + .init_machine = apq8064_cdp_init, + .init_early = apq8064_allocate_memory_regions, + .init_very_early = apq8064_early_reserve, +MACHINE_END diff --git a/arch/arm/mach-msm/lge/mako/board-mako.h b/arch/arm/mach-msm/lge/mako/board-mako.h new file mode 100644 index 000000000000..88debc7d62b9 --- /dev/null +++ b/arch/arm/mach-msm/lge/mako/board-mako.h @@ -0,0 +1,185 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2012 LGE Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_MSM_BOARD_APQ8064_H +#define __ARCH_ARM_MACH_MSM_BOARD_APQ8064_H + +#include +#include +#include +#include +#include +#include +#include + +/* Macros assume PMIC GPIOs and MPPs start at 1 */ +#define PM8921_GPIO_BASE NR_GPIO_IRQS +#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE) +#define PM8921_MPP_BASE (PM8921_GPIO_BASE + PM8921_NR_GPIOS) +#define PM8921_MPP_PM_TO_SYS(pm_mpp) (pm_mpp - 1 + PM8921_MPP_BASE) +#define PM8921_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS) + +#define PM8821_MPP_BASE (PM8921_MPP_BASE + PM8921_NR_MPPS) +#define PM8821_MPP_PM_TO_SYS(pm_mpp) (pm_mpp - 1 + PM8821_MPP_BASE) +#define PM8821_IRQ_BASE (PM8921_IRQ_BASE + PM8921_NR_IRQS) + +#define TABLA_INTERRUPT_BASE (PM8821_IRQ_BASE + PM8821_NR_IRQS) + +extern struct pm8xxx_regulator_platform_data + msm8064_pm8921_regulator_pdata[] __devinitdata; + +extern int msm8064_pm8921_regulator_pdata_len __devinitdata; + +#define GPIO_VREG_ID_EXT_5V 0 +#define GPIO_VREG_ID_EXT_3P3V 1 +#define GPIO_VREG_ID_EXT_TS_SW 2 +#define GPIO_VREG_ID_EXT_MPP8 3 + +#define GPIO_VREG_ID_FRC_5V 0 +#define GPIO_VREG_ID_AVC_1P2V 1 +#define GPIO_VREG_ID_AVC_1P8V 2 +#define GPIO_VREG_ID_AVC_2P2V 3 +#define GPIO_VREG_ID_AVC_5V 4 +#define GPIO_VREG_ID_AVC_3P3V 5 + +#define APQ8064_EXT_3P3V_REG_EN_GPIO 77 + +extern struct gpio_regulator_platform_data + apq8064_gpio_regulator_pdata[] __devinitdata; + +extern struct gpio_regulator_platform_data + mpq8064_gpio_regulator_pdata[] __devinitdata; + +extern struct rpm_regulator_platform_data + apq8064_rpm_regulator_pdata __devinitdata; + +extern struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5; +extern struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6; +extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0; +extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1; + +struct mmc_platform_data; +int __init apq8064_add_sdcc(unsigned int controller, + struct mmc_platform_data *plat); +extern void __init register_i2c_backlight_devices(void); +extern void __init lge_add_sound_devices(void); +void apq8064_init_mmc(void); +void apq8064_init_gpiomux(void); +void apq8064_init_pmic(void); + +extern struct msm_camera_board_info apq8064_camera_board_info; +/* Enabling flash LED for camera */ +extern struct msm_camera_board_info apq8064_lge_camera_board_info; + +void apq8064_init_cam(void); + +#define APQ_8064_GSBI1_QUP_I2C_BUS_ID 0 +#define APQ_8064_GSBI2_QUP_I2C_BUS_ID 2 +#define APQ_8064_GSBI3_QUP_I2C_BUS_ID 3 +#define APQ_8064_GSBI4_QUP_I2C_BUS_ID 4 +#define APQ_8064_GSBI5_QUP_I2C_BUS_ID 5 + +#ifndef CONFIG_MACH_LGE +unsigned char apq8064_hdmi_as_primary_selected(void); +#endif + +/* Camera GPIO Settings */ +#define GPIO_CAM_MCLK0 (5) + +/* FIXME: for old HW (LGU Rev.A,B VZW Rev.A,B ATT Rev.A) */ +#if 1 +#define GPIO_CAM_MCLK2 (2) +#define GPIO_CAM_FLASH_EN (7) +#else +#define GPIO_CAM_MCLK1 (4) +#define GPIO_CAM_FLASH_EN (2) +#endif + +#define GPIO_CAM_I2C_SDA (12) +#define GPIO_CAM_I2C_SCL (13) +#define GPIO_CAM1_RST_N (32) +#define GPIO_CAM2_RST_N (34) + +#define GPIO_CAM_FLASH_I2C_SDA (20) +#define GPIO_CAM_FLASH_I2C_SCL (21) + +#define I2C_SLAVE_ADDR_IMX111 (0x0D) +#define I2C_SLAVE_ADDR_IMX111_ACT (0x18) +#define I2C_SLAVE_ADDR_IMX091 (0x0D) +#define I2C_SLAVE_ADDR_IMX091_ACT (0x18) +#define I2C_SLAVE_ADDR_IMX119 (0x6E) +#define I2C_SLAVE_ADDR_FLASH (0xA6 >> 1) + +void apq8064_init_fb(void); +void apq8064_allocate_fb_region(void); +void apq8064_mdp_writeback(struct memtype_reserve *reserve_table); +void __init apq8064_set_display_params(char *prim_panel, char *ext_panel); + +void apq8064_init_gpu(void); +void apq8064_pm8xxx_gpio_mpp_init(void); + +#define PLATFORM_IS_MPQ8064() \ + (machine_is_mpq8064_hrd() || \ + machine_is_mpq8064_dtv() || \ + machine_is_mpq8064_cdp() \ + ) + + +#define GPIO_EXPANDER_IRQ_BASE (TABLA_INTERRUPT_BASE + \ + NR_TABLA_IRQS) +#define GPIO_EXPANDER_GPIO_BASE (PM8821_MPP_BASE + PM8821_NR_MPPS) + +#define GPIO_EPM_EXPANDER_BASE GPIO_EXPANDER_GPIO_BASE +#define SX150X_EPM_NR_GPIOS 16 +#define SX150X_EPM_NR_IRQS 8 + +#define SX150X_EXP1_GPIO_BASE (GPIO_EPM_EXPANDER_BASE + \ + SX150X_EPM_NR_GPIOS) +#define SX150X_EXP1_IRQ_BASE (GPIO_EXPANDER_IRQ_BASE + \ + SX150X_EPM_NR_IRQS) +#define SX150X_EXP1_NR_IRQS 16 +#define SX150X_EXP1_NR_GPIOS 16 + +#define SX150X_EXP2_GPIO_BASE (SX150X_EXP1_GPIO_BASE + \ + SX150X_EXP1_NR_GPIOS) +#define SX150X_EXP2_IRQ_BASE (SX150X_EXP1_IRQ_BASE + SX150X_EXP1_NR_IRQS) +#define SX150X_EXP2_NR_IRQS 8 +#define SX150X_EXP2_NR_GPIOS 8 + +#define SX150X_EXP3_GPIO_BASE (SX150X_EXP2_GPIO_BASE + \ + SX150X_EXP2_NR_GPIOS) +#define SX150X_EXP3_IRQ_BASE (SX150X_EXP2_IRQ_BASE + SX150X_EXP2_NR_IRQS) +#define SX150X_EXP3_NR_IRQS 8 +#define SX150X_EXP3_NR_GPIOS 8 + +#define SX150X_EXP4_GPIO_BASE (SX150X_EXP3_GPIO_BASE + \ + SX150X_EXP3_NR_GPIOS) +#define SX150X_EXP4_IRQ_BASE (SX150X_EXP3_IRQ_BASE + SX150X_EXP3_NR_IRQS) +#define SX150X_EXP4_NR_IRQS 16 +#define SX150X_EXP4_NR_GPIOS 16 + +#define SX150X_GPIO(_expander, _pin) (SX150X_EXP##_expander##_GPIO_BASE + _pin) + +enum { + SX150X_EPM, + SX150X_EXP1, + SX150X_EXP2, + SX150X_EXP3, + SX150X_EXP4, +}; + +extern struct msm_rtb_platform_data apq8064_rtb_pdata; + +void apq8064_init_input(void); +void __init apq8064_init_misc(void); +#endif diff --git a/include/linux/android_vibrator.h b/include/linux/android_vibrator.h new file mode 100644 index 000000000000..bfd886c89497 --- /dev/null +++ b/include/linux/android_vibrator.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2011 LGE, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_ANDROID_VIBRATOR_H +#define __LINUX_ANDROID_VIBRATOR_H + +/* android vibrator platform data */ +struct android_vibrator_platform_data { + int enable_status; + int amp; + int vibe_n_value; + int (*power_set)(int enable); /* LDO Power Set Function */ + int (*pwm_set)(int enable, int gain, int n_value); /* PWM Set Function */ + int (*ic_enable_set)(int enable); /* Motor IC Set Function */ + int (*vibrator_init)(void); +}; + + +/* Debug Mask setting */ +#define VIBRATOR_DEBUG_PRINT (1) +#define VIBRATOR_ERROR_PRINT (1) +#define VIBRATOR_INFO_PRINT (0) + +#if (VIBRATOR_INFO_PRINT) +#define INFO_MSG(fmt, args...) \ + printk(KERN_INFO "[%s] " \ + fmt, __FUNCTION__, ##args); +#else +#define INFO_MSG(fmt, args...) +#endif + +#if (VIBRATOR_DEBUG_PRINT) +#define DEBUG_MSG(fmt, args...) \ + printk(KERN_INFO "[%s %d] " \ + fmt, __FUNCTION__, __LINE__, ##args); +#else +#define DEBUG_MSG(fmt, args...) +#endif + +#if (VIBRATOR_ERROR_PRINT) +#define ERR_MSG(fmt, args...) \ + printk(KERN_ERR "[%s %d] " \ + fmt, __FUNCTION__, __LINE__, ##args); +#else +#define ERR_MSG(fmt, args...) +#endif + + +#endif + diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index 894e1143786b..874a5c8ba73c 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -148,7 +148,7 @@ config SND_SOC_MSM8960 select SND_SOC_WCD9304 select SND_SOC_MSM_HOSTLESS_PCM select SND_SOC_MSM_QDSP6_HDMI_AUDIO - select SND_SOC_CS8427 + #select SND_SOC_CS8427 default n help To add support for SoC audio on MSM8960 and APQ8064 boards