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msm: pil-riva: Shutdown RIVA via toplevel reset

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The reset bit inside the PMU may not be accessible if RIVA is in
power collapse. Therefore, don't assert the cCPU reset because
Linux may hang trying to write the PMU register. Instead, just
assert the toplevel reset that resets the entire RIVA subsystem.

Change-Id: I1f1094bc7974b3181b18c2246db5fb5a6c4ed812
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd 2012-08-03 16:27:37 -07:00
parent 74febe5219
commit ede3f1b716
1 changed files with 0 additions and 12 deletions
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12
arch/arm/mach-msm/pil-riva.c
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@ -228,18 +228,6 @@ static int pil_riva_reset(struct pil_desc *pil)
static int pil_riva_shutdown(struct pil_desc *pil)
{
struct riva_data *drv = dev_get_drvdata(pil->dev);
u32 reg;
/* Put cCPU and cCPU clock into reset */
reg = readl_relaxed(drv->base + RIVA_PMU_OVRD_VAL);
reg &= ~(RIVA_PMU_OVRD_VAL_CCPU_RESET | RIVA_PMU_OVRD_VAL_CCPU_CLK);
writel_relaxed(reg, drv->base + RIVA_PMU_OVRD_VAL);
reg = readl_relaxed(drv->base + RIVA_PMU_OVRD_EN);
reg |= RIVA_PMU_OVRD_EN_CCPU_RESET | RIVA_PMU_OVRD_EN_CCPU_CLK;
writel_relaxed(reg, drv->base + RIVA_PMU_OVRD_EN);
mb();
/* Assert reset to Riva */
writel_relaxed(1, RIVA_RESET);
mb();