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msm: kgsl: Print additional registers on IOMMU pagefault

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Print more IOMMU registers when a IOMMU pagefault happens which
report whether the pagefault is a read or write fault.

Change-Id: I27acafa9dcfd0c7de9056151ed1baef7dd2346df
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Sakshi Agrawal <sakshia@codeaurora.org>
This commit is contained in:
Sakshi Agrawal 2013-01-18 12:45:13 -08:00 committed by Iliyan Malchev
parent 542cde2a9b
commit f51d433f1e
2 changed files with 40 additions and 9 deletions
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36
drivers/gpu/msm/kgsl_iommu.c
View file

@ -43,6 +43,8 @@ static struct kgsl_iommu_register_list kgsl_iommuv1_reg[KGSL_IOMMU_REG_MAX] = {
{ 0x820, 0, 0 }, /* RESUME */
{ 0x03C, 0, 0 }, /* TLBLKCR */
{ 0x818, 0, 0 }, /* V2PUR */
{ 0x2C, 0, 0 }, /* FSYNR0 */
{ 0x2C, 0, 0 }, /* FSYNR0 */
};
static struct kgsl_iommu_register_list kgsl_iommuv2_reg[KGSL_IOMMU_REG_MAX] = {
@ -51,7 +53,11 @@ static struct kgsl_iommu_register_list kgsl_iommuv2_reg[KGSL_IOMMU_REG_MAX] = {
{ 0x28, 0x00FFFFFF, 14 }, /* TTBR1 */
{ 0x58, 0, 0 }, /* FSR */
{ 0x618, 0, 0 }, /* TLBIALL */
{ 0x008, 0, 0 } /* RESUME */
{ 0x008, 0, 0 }, /* RESUME */
{ 0, 0, 0 }, /* TLBLKCR */
{ 0, 0, 0 }, /* V2PUR */
{ 0x68, 0, 0 }, /* FSYNR0 */
{ 0x6C, 0, 0 } /* FSYNR1 */
};
struct remote_iommu_petersons_spinlock kgsl_iommu_sync_lock_vars;
@ -115,6 +121,9 @@ static int kgsl_iommu_fault_handler(struct iommu_domain *domain,
struct kgsl_device *device;
struct adreno_device *adreno_dev;
unsigned int no_page_fault_log = 0;
unsigned int pid;
unsigned int fsynr0, fsynr1;
int write;
ret = get_iommu_unit(dev, &mmu, &iommu_unit);
if (ret)
@ -134,23 +143,36 @@ static int kgsl_iommu_fault_handler(struct iommu_domain *domain,
fsr = KGSL_IOMMU_GET_CTX_REG(iommu, iommu_unit,
iommu_dev->ctx_id, FSR);
fsynr0 = KGSL_IOMMU_GET_CTX_REG(iommu, iommu_unit,
iommu_dev->ctx_id, FSYNR0);
fsynr1 = KGSL_IOMMU_GET_CTX_REG(iommu, iommu_unit,
iommu_dev->ctx_id, FSYNR1);
if (!msm_soc_version_supports_iommu_v1())
write = ((fsynr1 & (KGSL_IOMMU_FSYNR1_AWRITE_MASK <<
KGSL_IOMMU_FSYNR1_AWRITE_SHIFT)) ? 1 : 0);
else
write = ((fsynr0 & (KGSL_IOMMU_V1_FSYNR0_WNR_MASK <<
KGSL_IOMMU_V1_FSYNR0_WNR_SHIFT)) ? 1 : 0);
if (adreno_dev->ft_pf_policy & KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE)
no_page_fault_log = kgsl_mmu_log_fault_addr(mmu, ptbase, addr);
pid = kgsl_mmu_get_ptname_from_ptbase(mmu, ptbase);
if (!no_page_fault_log) {
KGSL_MEM_CRIT(iommu_dev->kgsldev,
"GPU PAGE FAULT: addr = %lX pid = %d\n",
addr, kgsl_mmu_get_ptname_from_ptbase(mmu, ptbase));
KGSL_MEM_CRIT(iommu_dev->kgsldev, "context = %d FSR = %X\n",
iommu_dev->ctx_id, fsr);
"GPU PAGE FAULT: addr = %lX pid = %d\n", addr, pid);
KGSL_MEM_CRIT(iommu_dev->kgsldev,
"context = %d FSR = %X FSYNR0 = %X FSYNR1 = %X(%s fault)\n",
iommu_dev->ctx_id, fsr, fsynr0, fsynr1,
write ? "write" : "read");
}
mmu->fault = 1;
iommu_dev->fault = 1;
trace_kgsl_mmu_pagefault(iommu_dev->kgsldev, addr,
kgsl_mmu_get_ptname_from_ptbase(mmu, ptbase), 0);
trace_kgsl_mmu_pagefault(iommu_dev->kgsldev, addr, pid,
write ? "write" : "read");
/*
* We do not want the h/w to resume fetching data from an iommu unit

13
drivers/gpu/msm/kgsl_iommu.h
View file

@ -19,7 +19,7 @@
#define KGSL_IOMMU_CTX_OFFSET_V2 0x8000
#define KGSL_IOMMU_CTX_SHIFT 12
/* TLBLKCR feilds */
/* TLBLKCR fields */
#define KGSL_IOMMU_TLBLKCR_LKE_MASK 0x00000001
#define KGSL_IOMMU_TLBLKCR_LKE_SHIFT 0
#define KGSL_IOMMU_TLBLKCR_TLBIALLCFG_MASK 0x00000001
@ -33,12 +33,19 @@
#define KGSL_IOMMU_TLBLKCR_VICTIM_MASK 0x000000FF
#define KGSL_IOMMU_TLBLKCR_VICTIM_SHIFT 16
/* V2PXX feilds */
/* V2PXX fields */
#define KGSL_IOMMU_V2PXX_INDEX_MASK 0x000000FF
#define KGSL_IOMMU_V2PXX_INDEX_SHIFT 0
#define KGSL_IOMMU_V2PXX_VA_MASK 0x000FFFFF
#define KGSL_IOMMU_V2PXX_VA_SHIFT 12
/* FSYNR1 V0 fields */
#define KGSL_IOMMU_FSYNR1_AWRITE_MASK 0x00000001
#define KGSL_IOMMU_FSYNR1_AWRITE_SHIFT 8
/* FSYNR0 V1 fields */
#define KGSL_IOMMU_V1_FSYNR0_WNR_MASK 0x00000001
#define KGSL_IOMMU_V1_FSYNR0_WNR_SHIFT 4
enum kgsl_iommu_reg_map {
KGSL_IOMMU_GLOBAL_BASE = 0,
KGSL_IOMMU_CTX_TTBR0,
@ -48,6 +55,8 @@ enum kgsl_iommu_reg_map {
KGSL_IOMMU_CTX_RESUME,
KGSL_IOMMU_CTX_TLBLKCR,
KGSL_IOMMU_CTX_V2PUR,
KGSL_IOMMU_CTX_FSYNR0,
KGSL_IOMMU_CTX_FSYNR1,
KGSL_IOMMU_REG_MAX
};