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https://github.com/followmsi/android_kernel_google_msm.git
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[PATCH] msi: sanely support hardware level msi disabling
In some cases when we are not using msi we need a way to ensure that the hardware does not have an msi capability enabled. Currently the code has been calling disable_msi_mode to try and achieve that. However disable_msi_mode has several other side effects and is only available when msi support is compiled in so it isn't really appropriate. Instead this patch implements pci_msi_off which disables all msi and msix capabilities unconditionally with no additional side effects. pci_disable_device was redundantly clearing the bus master enable flag and clearing the msi enable bit. A device that is not allowed to perform bus mastering operations cannot generate intx or msi interrupt messages as those are essentially a special case of dma, and require bus mastering. So the call in pci_disable_device to disable msi capabilities was redundant. quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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parent
58a53b246b
commit
f5f2b13129
7 changed files with 35 additions and 16 deletions
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@ -968,7 +968,6 @@ void pci_scan_msi_device(struct pci_dev *dev) {}
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int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) {return -1;}
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void pci_disable_msix(struct pci_dev *dev) {}
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void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
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void disable_msi_mode(struct pci_dev *dev, int pos, int type) {}
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void pci_no_msi(void) {}
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EXPORT_SYMBOL(pci_enable_msix);
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EXPORT_SYMBOL(pci_disable_msix);
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@ -211,7 +211,7 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
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pci_intx(dev, 0); /* disable intx */
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}
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void disable_msi_mode(struct pci_dev *dev, int pos, int type)
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static void disable_msi_mode(struct pci_dev *dev, int pos, int type)
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{
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u16 control;
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@ -881,13 +881,6 @@ pci_disable_device(struct pci_dev *dev)
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if (atomic_sub_return(1, &dev->enable_cnt) != 0)
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return;
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if (dev->msi_enabled)
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disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
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PCI_CAP_ID_MSI);
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if (dev->msix_enabled)
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disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
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PCI_CAP_ID_MSIX);
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pci_read_config_word(dev, PCI_COMMAND, &pci_command);
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if (pci_command & PCI_COMMAND_MASTER) {
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pci_command &= ~PCI_COMMAND_MASTER;
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@ -1277,6 +1270,33 @@ pci_intx(struct pci_dev *pdev, int enable)
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}
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}
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/**
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* pci_msi_off - disables any msi or msix capabilities
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* @pdev: the PCI device to operate on
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*
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* If you want to use msi see pci_enable_msi and friends.
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* This is a lower level primitive that allows us to disable
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* msi operation at the device level.
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*/
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void pci_msi_off(struct pci_dev *dev)
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{
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int pos;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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}
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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}
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}
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#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
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/*
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* These can be overridden by arch-specific implementations
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@ -46,10 +46,8 @@ extern struct rw_semaphore pci_bus_sem;
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extern unsigned int pci_pm_d3_delay;
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#ifdef CONFIG_PCI_MSI
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void disable_msi_mode(struct pci_dev *dev, int pos, int type);
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void pci_no_msi(void);
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#else
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static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { }
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static inline void pci_no_msi(void) { }
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#endif
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@ -1438,8 +1438,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
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*/
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static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
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{
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disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
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PCI_CAP_ID_MSI);
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pci_msi_off(dev);
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dev->no_msi = 1;
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printk(KERN_WARNING "PCI: PXH quirk detected, "
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@ -543,6 +543,7 @@ void pci_set_master(struct pci_dev *dev);
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int __must_check pci_set_mwi(struct pci_dev *dev);
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void pci_clear_mwi(struct pci_dev *dev);
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void pci_intx(struct pci_dev *dev, int enable);
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void pci_msi_off(struct pci_dev *dev);
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int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
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int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
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void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
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@ -292,9 +292,10 @@
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
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/* MSI-X registers (these are at offset PCI_MSI_FLAGS) */
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
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#define PCI_MSIX_FLAGS 2
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
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