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https://github.com/followmsi/android_kernel_google_msm.git
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msm: vidc: Handle mgen2maxi interrupt in video driver
Handle interrupt generated by mgen2maxi h/w and avoid unknown interrupts storm which results in target reset issues. Change-Id: Ida24cb2dde15c9cd4a4c1d9ca336b1a4b662c4d1 Signed-off-by: Maheshwar Ajja <majja@codeaurora.org> Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
This commit is contained in:
Maheshwar Ajja
Artem Borisov
parent
f675bfaac7
commit
fc9cab72cb
5 changed files with 192 additions and 5 deletions
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@ -880,7 +880,7 @@ static void ddl_edfu_callback(struct ddl_context *ddl_context)
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struct ddl_client_context *ddl;
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u32 channel_inst_id;
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DDL_MSG_MED("ddl_edfu_callback");
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DDL_MSG_ERROR("ddl_edfu_callback");
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vidc_1080p_get_returned_channel_inst_id(&channel_inst_id);
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vidc_1080p_clear_returned_channel_inst_id();
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ddl = ddl_get_current_ddl_client_for_channel_id(ddl_context,
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@ -960,6 +960,39 @@ static u32 ddl_slice_done_callback(struct ddl_context *ddl_context)
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return return_status;
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}
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static u32 ddl_handle_mgen2axi_error(struct ddl_context *ddl_context)
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{
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u32 axi_error_info_a;
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u32 axi_error_info_b;
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struct vidc_1080P_axi_status axi_a_status;
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struct vidc_1080P_axi_status axi_b_status;
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struct vidc_1080P_axi_ctrl axi_ctrl;
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u32 status = false;
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vidc_1080p_get_mgenaxi_error_info(&axi_error_info_a,
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&axi_error_info_b);
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vidc_1080p_get_mgen2axi_status(&axi_a_status,
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&axi_b_status);
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if (axi_a_status.axi_error_interrupt ||
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axi_a_status.axi_watchdog_error_interrupt ||
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axi_b_status.axi_error_interrupt ||
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axi_b_status.axi_watchdog_error_interrupt) {
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vidc_1080p_get_mgen2maxi_ctrl(&axi_ctrl);
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axi_ctrl.axi_interrupt_clr = 1;
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vidc_1080p_set_mgen2maxi_ctrl(&axi_ctrl);
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DDL_MSG_HIGH("%s: Wait for 20ms to clear mgen2axi intr",
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__func__);
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usleep(20*1000);
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axi_ctrl.axi_interrupt_clr = 0;
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vidc_1080p_set_mgen2maxi_ctrl(&axi_ctrl);
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vidc_1080p_get_mgen2axi_status(&axi_a_status,
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&axi_b_status);
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status = true;
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}
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return status;
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}
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static u32 ddl_process_intr_status(struct ddl_context *ddl_context,
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u32 intr_status)
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{
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@ -1003,7 +1036,12 @@ static u32 ddl_process_intr_status(struct ddl_context *ddl_context,
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ddl_dpb_buffers_set_done_callback(ddl_context);
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break;
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default:
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DDL_MSG_LOW("UNKWN_INTR");
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return_status = ddl_handle_mgen2axi_error(ddl_context);
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if (return_status) {
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return_status = false;
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DDL_MSG_ERROR("Cleared Mgen2axi interrupt");
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} else
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DDL_MSG_ERROR("UNKWN_INTR");
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break;
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}
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return return_status;
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@ -316,22 +316,41 @@
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#define VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_BMSK 0x40
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#define VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_SHFT 6
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#define DDL_SHARED_MEM_11BIT_RIGHT_SHIFT 11
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#ifdef VIDC_REGISTER_LOG
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static void DDL_MEM_WRITE_32(struct ddl_buf_addr *shared_mem, u32 offset,
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u32 val)
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{
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u32 *addr;
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VIDC_REG_OUT("\nShared mem write :REG 0x%08x: write 0x%08x",
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offset, val);
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addr = (u32 *)((u8 *)(shared_mem)->align_virtual_addr + (offset));
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*addr = val;
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}
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static u32 DDL_MEM_READ_32(struct ddl_buf_addr *shared_mem, u32 offset)
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{
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u32 val;
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val = *((u32 *)((u8 *)(shared_mem)->align_virtual_addr + (offset)));
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VIDC_REG_IN("\nShared mem read :REG 0x%08x: read 0x%08x",
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offset, val);
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return val;
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}
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#else
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#define DDL_MEM_WRITE_32(base, offset, val) ddl_mem_write_32(\
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(u32 *) ((u8 *) (base)->align_virtual_addr + (offset)), (val))
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#define DDL_MEM_READ_32(base, offset) ddl_mem_read_32(\
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(u32 *) ((u8 *) (base)->align_virtual_addr + (offset)))
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#define DDL_SHARED_MEM_11BIT_RIGHT_SHIFT 11
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static void ddl_mem_write_32(u32 *addr, u32 data)
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{
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*addr = data;
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}
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static u32 ddl_mem_read_32(u32 *addr)
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{
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return *addr;
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}
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#endif
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void vidc_sm_get_extended_decode_status(struct ddl_buf_addr *shared_mem,
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u32 *more_field_needed,
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@ -194,6 +194,95 @@ void vidc_1080p_get_risc2host_cmd_status(u32 err_status,
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}
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void vidc_1080p_get_mgenaxi_error_info(u32 *axi_error_info_a,
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u32 *axi_error_info_b)
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{
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VIDC_HWIO_IN(REG_736158, axi_error_info_a);
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VIDC_HWIO_IN(REG_598415, axi_error_info_b);
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}
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void vidc_1080p_get_mgen2axi_status(struct vidc_1080P_axi_status *axi_a_status,
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struct vidc_1080P_axi_status *axi_b_status)
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{
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u32 status;
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VIDC_HWIO_IN(REG_437878, &status);
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axi_a_status->axi_error_interrupt = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_A_ERR_INTR_BMSK,
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HWIO_REG_437878_AXI_A_ERR_INTR_SHFT);
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axi_a_status->axi_halt_ack = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_A_HALT_ACK_BMSK,
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HWIO_REG_437878_AXI_A_HALT_ACK_SHFT);
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axi_a_status->axi_idle = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_A_IDLE_BMSK,
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HWIO_REG_437878_AXI_A_IDLE_SHFT);
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axi_a_status->axi_watchdog_error_interrupt = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_A_WDTIMEOUT_INTR_BMSK,
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HWIO_REG_437878_AXI_A_WDTIMEOUT_INTR_SHFT);
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axi_b_status->axi_error_interrupt = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_B_ERR_INTR_BMSK,
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HWIO_REG_437878_AXI_B_ERR_INTR_SHFT);
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axi_b_status->axi_halt_ack = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_B_HALT_ACK_BMSK,
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HWIO_REG_437878_AXI_B_HALT_ACK_SHFT);
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axi_b_status->axi_idle = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_B_IDLE_BMSK,
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HWIO_REG_437878_AXI_B_IDLE_SHFT);
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axi_b_status->axi_watchdog_error_interrupt = VIDC_GETFIELD(status,
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HWIO_REG_437878_AXI_B_WDTIMEOUT_INTR_BMSK,
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HWIO_REG_437878_AXI_B_WDTIMEOUT_INTR_SHFT);
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}
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void vidc_1080p_get_mgen2maxi_ctrl(struct vidc_1080P_axi_ctrl *ctrl)
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{
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u32 ctrl_value;
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VIDC_HWIO_IN(REG_471159, &ctrl_value);
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ctrl->axi_halt_req = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_HALT_REQ_BMSK,
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HWIO_REG_471159_AXI_HALT_REQ_SHFT);
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ctrl->axi_reset = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_RESET_BMSK,
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HWIO_REG_471159_AXI_RESET_SHFT);
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ctrl->axi_halt_on_readerror = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_HALT_ON_RD_ERR_BMSK,
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HWIO_REG_471159_AXI_HALT_ON_RD_ERR_SHFT);
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ctrl->axi_halt_on_writeerror = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_HALT_ON_WR_ERR_BMSK,
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HWIO_REG_471159_AXI_HALT_ON_WR_ERR_SHFT);
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ctrl->axi_halt_on_watchdog_timeout = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_HALT_ON_WDTIMEOUT_BMSK,
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HWIO_REG_471159_AXI_HALT_ON_WDTIMEOUT_SHFT);
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ctrl->axi_watchdog_timeout_value = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_WDTIMEOUT_LOG2_BMSK,
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HWIO_REG_471159_AXI_WDTIMEOUT_LOG2_SHFT);
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ctrl->axi_interrupt_clr = VIDC_GETFIELD(ctrl_value,
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HWIO_REG_471159_AXI_INTR_CLR_BMSK,
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HWIO_REG_471159_AXI_INTR_CLR_SHFT);
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}
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void vidc_1080p_set_mgen2maxi_ctrl(struct vidc_1080P_axi_ctrl *ctrl)
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{
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u32 ctrl_value;
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ctrl_value = VIDC_SETFIELD(ctrl->axi_halt_req,
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HWIO_REG_471159_AXI_HALT_REQ_SHFT,
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HWIO_REG_471159_AXI_HALT_REQ_BMSK);
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ctrl_value |= VIDC_SETFIELD(ctrl->axi_reset,
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HWIO_REG_471159_AXI_RESET_SHFT,
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HWIO_REG_471159_AXI_RESET_BMSK);
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ctrl_value |= VIDC_SETFIELD(ctrl->axi_halt_on_readerror,
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HWIO_REG_471159_AXI_HALT_ON_RD_ERR_SHFT,
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HWIO_REG_471159_AXI_HALT_ON_RD_ERR_BMSK);
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ctrl_value |= VIDC_SETFIELD(ctrl->axi_halt_on_writeerror,
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HWIO_REG_471159_AXI_HALT_ON_WR_ERR_SHFT,
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HWIO_REG_471159_AXI_HALT_ON_WR_ERR_BMSK);
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ctrl_value |= VIDC_SETFIELD(ctrl->axi_halt_on_watchdog_timeout,
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HWIO_REG_471159_AXI_HALT_ON_WDTIMEOUT_SHFT,
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HWIO_REG_471159_AXI_HALT_ON_WDTIMEOUT_BMSK);
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ctrl_value |= VIDC_SETFIELD(ctrl->axi_interrupt_clr,
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HWIO_REG_471159_AXI_INTR_CLR_SHFT,
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HWIO_REG_471159_AXI_INTR_CLR_BMSK);
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VIDC_HWIO_OUT(REG_471159, ctrl_value);
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}
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void vidc_1080p_clear_risc2host_cmd(void)
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{
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VIDC_HWIO_OUT(REG_695082, VIDC_1080P_RISC2HOST_CMD_EMPTY);
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@ -429,6 +429,23 @@ struct vidc_1080p_enc_slice_batch_out_param {
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struct vidc_1080p_enc_slice_info slice_info
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[VIDC_1080P_SLICE_BATCH_MAX_STRM_BFR];
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};
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struct vidc_1080P_axi_ctrl {
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u32 axi_halt_req;
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u32 axi_reset;
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u32 axi_halt_on_readerror;
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u32 axi_halt_on_writeerror;
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u32 axi_halt_on_watchdog_timeout;
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u32 axi_watchdog_timeout_value;
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u32 axi_interrupt_clr;
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};
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struct vidc_1080P_axi_status {
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u32 axi_halt_ack;
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u32 axi_idle;
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u32 axi_error_interrupt;
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u32 axi_watchdog_error_interrupt;
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};
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struct vidc_1080p_dec_disp_info{
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u32 disp_resl_change;
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u32 dec_resl_change;
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@ -473,6 +490,12 @@ void vidc_1080p_get_risc2host_cmd(u32 *pn_risc2host_command,
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u32 *pn_risc2host_arg3, u32 *pn_risc2host_arg4);
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void vidc_1080p_get_risc2host_cmd_status(u32 err_status,
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u32 *dec_err_status, u32 *disp_err_status);
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void vidc_1080p_get_mgen2maxi_ctrl(struct vidc_1080P_axi_ctrl *ctrl);
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void vidc_1080p_set_mgen2maxi_ctrl(struct vidc_1080P_axi_ctrl *ctrl);
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void vidc_1080p_get_mgenaxi_error_info(u32 *axi_error_info_a,
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u32 *axi_error_info_b);
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void vidc_1080p_get_mgen2axi_status(struct vidc_1080P_axi_status *axi_a_status,
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struct vidc_1080P_axi_status *axi_b_status);
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void vidc_1080p_clear_risc2host_cmd(void);
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void vidc_1080p_get_fw_version(u32 *pn_fw_version);
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void vidc_1080p_get_fw_status(u32 *pn_fw_status);
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@ -3993,6 +3993,7 @@ extern u8 *VIDC_BASE_PTR;
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HWIO_REG_437878_ADDR, HWIO_REG_437878_RMSK)
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#define HWIO_REG_437878_INM(m) \
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in_dword_masked(HWIO_REG_437878_ADDR, m)
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#define HWIO_REG_437878_AXI_WDTIMEOUT_INTR_BMSK 0x3000
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#define HWIO_REG_437878_AXI_WDTIMEOUT_INTR_SHFT 0xc
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#define HWIO_REG_437878_AXI_ERR_INTR_BMSK 0x300
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@ -4002,6 +4003,23 @@ extern u8 *VIDC_BASE_PTR;
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#define HWIO_REG_437878_AXI_HALT_ACK_BMSK 0x3
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#define HWIO_REG_437878_AXI_HALT_ACK_SHFT 0
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#define HWIO_REG_437878_AXI_B_WDTIMEOUT_INTR_BMSK 0x2000
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#define HWIO_REG_437878_AXI_B_WDTIMEOUT_INTR_SHFT 0xd
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#define HWIO_REG_437878_AXI_A_WDTIMEOUT_INTR_BMSK 0x1000
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#define HWIO_REG_437878_AXI_A_WDTIMEOUT_INTR_SHFT 0xc
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#define HWIO_REG_437878_AXI_B_ERR_INTR_BMSK 0x200
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#define HWIO_REG_437878_AXI_B_ERR_INTR_SHFT 0x9
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#define HWIO_REG_437878_AXI_A_ERR_INTR_BMSK 0x100
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#define HWIO_REG_437878_AXI_A_ERR_INTR_SHFT 0x8
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#define HWIO_REG_437878_AXI_B_IDLE_BMSK 0x20
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#define HWIO_REG_437878_AXI_B_IDLE_SHFT 0x5
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#define HWIO_REG_437878_AXI_A_IDLE_BMSK 0x10
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#define HWIO_REG_437878_AXI_A_IDLE_SHFT 0x4
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#define HWIO_REG_437878_AXI_B_HALT_ACK_BMSK 0x2
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#define HWIO_REG_437878_AXI_B_HALT_ACK_SHFT 0x1
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#define HWIO_REG_437878_AXI_A_HALT_ACK_BMSK 0x1
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#define HWIO_REG_437878_AXI_A_HALT_ACK_SHFT 0
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#define HWIO_REG_736158_ADDR \
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(VIDC_MGEN2MAXI_REG_BASE + 0x0000001c)
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#define HWIO_REG_736158_PHYS \
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