commit 157f38f993919b648187ba341bfb05d0e91ad2f6 upstream.
Fix parent-device reference leak due to SPI-core taking an unnecessary
reference to the parent when allocating the master structure, a
reference that was never released.
Note that driver core takes its own reference to the parent when the
master device is registered.
Fixes: 49dce689ad ("spi doesn't need class_device")
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit a394d635193b641f2c86ead5ada5b115d57c51f8 upstream.
Actually, spi_master_put() after spi_alloc_master() must _not_ be followed
by kfree(). The memory is already freed with the call to spi_master_put()
through spi_master_class, which registers a release function. Calling both
spi_master_put() and kfree() results in often nasty (and delayed) crashes
elsewhere in the kernel, often in the networking stack.
This reverts commit eb4af0f534.
Link to patch and concerns: https://lkml.org/lkml/2012/9/3/269
or
http://lkml.iu.edu/hypermail/linux/kernel/1209.0/00790.html
Alexey Klimov: This revert becomes valid after
94c69f765f when spi-imx.c
has been fixed and there is no need to call kfree() so comment
for spi_alloc_master() should be fixed.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 02bc933ebb59208f42c2e6305b2c17fd306f695d upstream.
On Intel Baytrail, there is case when interrupt handler get called, no SPI
message is captured. The RX FIFO is indeed empty when RX timeout pending
interrupt (SSSR_TINT) happens.
Use the BIOS version where both HSUART and SPI are on the same IRQ. Both
drivers are using IRQF_SHARED when calling the request_irq function. When
running two separate and independent SPI and HSUART application that
generate data traffic on both components, user will see messages like
below on the console:
pxa2xx-spi pxa2xx-spi.0: bad message state in interrupt handler
This commit will fix this by first checking Receiver Time-out Interrupt,
if it is disabled, ignore the request and return without servicing.
Signed-off-by: Tan, Jui Nee <jui.nee.tan@intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit f20fbaad7620af2df36a1f9d1c9ecf48ead5b747 upstream.
`spidev_message()` sums the lengths of the individual SPI transfers to
determine the overall SPI message length. It restricts the total
length, returning an error if too long, but it does not check for
arithmetic overflow. For example, if the SPI message consisted of two
transfers and the first has a length of 10 and the second has a length
of (__u32)(-1), the total length would be seen as 9, even though the
second transfer is actually very long. If the second transfer specifies
a null `rx_buf` and a non-null `tx_buf`, the `copy_from_user()` could
overrun the spidev's pre-allocated tx buffer before it reaches an
invalid user memory address. Fix it by checking that neither the total
nor the individual transfer lengths exceed the maximum allowed value.
Thanks to Dan Carpenter for reporting the potential integer overflow.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Mark Brown <broonie@kernel.org>
[Ian Abbott: Note: original commit compares the lengths to INT_MAX instead
of bufsiz due to changes in earlier commits.]
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 9d239d353c319f9ff884c287ce47feb7cdf60ddc upstream.
The commit d297933cc7fc (spi: dw: Fix detecting FIFO depth) tries to fix the
logic of the FIFO detection based on the description on the comments. However,
there is a slight difference between numbers in TX Level and TX FIFO size.
So, by specification the FIFO size would be in a range 2-256 bytes. From TX
Level prospective it means we can set threshold in the range 0-(FIFO size - 1)
bytes. Hence there are currently two issues:
a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
either 0 or 1 byte;
b) FIFO size is incorrectly decreased by 1 which already done by meaning of
TX Level register.
This patch fixes it eventually right.
Fixes: d297933cc7fc (spi: dw: Fix detecting FIFO depth)
Reviewed-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 67bf9cda4b498b8cea4a40be67a470afe57d2e88 upstream.
The FIFO size is 40 accordingly to the specifications, but this means 0x40,
i.e. 64 bytes. This patch fixes the typo and enables FIFO size autodetection
for Intel MID devices.
Fixes: 7063c0d942 (spi/dw_spi: add DMA support)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit d297933cc7fcfbaaf2d37570baac73287bf0357d upstream.
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
to test fifo == 257. In the case fifo is 257, it means the latest valid
setting is fifo = 256. So after the for loop iteration, we should check
fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-and-tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
[lizf: Backported to 3.4: adjust context]
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 0a8727e697 upstream.
An IOCTL call that calls spi_setup() and then dw_spi_setup() will
overwrite the persisted last transfer speed. On each transfer, the
SPI speed is compared to the last transfer speed to determine if the
clock divider registers need to be updated (did the speed change?).
This bug was observed with the spidev driver using spi-config to
update the max transfer speed.
This fix: Don't overwrite the persisted last transaction clock speed
when updating the SPI parameters in dw_spi_setup(). On the next
transaction, the new speed won't match the persisted last speed
and the hardware registers will be updated.
On initialization, the persisted last transaction clock
speed will be 0 but will be updated after the first SPI
transaction.
Move zeroed clock divider check into clock change test because
chip->clk_div is zero on startup and would cause a divide-by-zero
error. The calculation was wrong as well (can't support odd #).
Reported-by: Vlastimil Setka <setka@vsis.cz>
Signed-off-by: Vlastimil Setka <setka@vsis.cz>
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 3ffa6158f0 upstream.
When mapped RX DMA entries are unmapped in an error condition when DMA
is firstly configured in the driver, the number of TX DMA entries was
passed in, which is incorrect
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 8e45ef682c upstream.
Do full clean up at exit, means terminate all ongoing DMA transfers.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
[lizf: Backported to 3.4: adjust context]
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit b41583e729 upstream.
In case of 8 bit mode and DMA usage we end up with every second byte written as
0. We have to respect bits_per_word settings what this patch actually does.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
commit 1f802f8249 upstream.
This reverts commit e120cc0dcf.
It causes a NULL pointer dereference with drivers using the generic
spi_transfer_one_message(), which always calls
spi_finalize_current_message(), which zeroes master->cur_msg.
Drivers implementing transfer_one_message() theirselves must always call
spi_finalize_current_message(), even if the transfer failed:
* @transfer_one_message: the subsystem calls the driver to transfer a single
* message while queuing transfers that arrive in the meantime. When the
* driver is finished with this message, it must call
* spi_finalize_current_message() so the subsystem can issue the next
* transfer
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit e120cc0dcf upstream.
This corrects a problem in spi_pump_messages() that leads to an spi
message hanging forever when a call to transfer_one_message() fails.
This failure occurs in my MCP2210 driver when the cs_change bit is set
on the last transfer in a message, an operation which the hardware does
not support.
Rationale
Since the transfer_one_message() returns an int, we must presume that it
may fail. If transfer_one_message() should never fail, it should return
void. Thus, calls to transfer_one_message() should properly manage a
failure.
Fixes: ffbbdd2132 (spi: create a message queueing infrastructure)
Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 1ad849aee5 upstream.
Some SPI slave devices require asserted chip select signal across
multiple transfer segments of an SPI message. Currently the driver
always de-asserts the internal SS signal for every single transfer
segment of the message and ignores the 'cs_change' flag of the
transfer description. Disable the internal chip select (SS) only
if this is needed and indicated by the 'cs_change' flag.
Without this change, each partial transfer of a surrounding
multi-part SPI transaction might erroneously change the SS
signal, which might prevent slaves from answering the request
that was sent in a previous transfer segment because the
transaction could be considered aborted (SS was de-asserted
before reading the response).
Reported-by: Gerhard Sittig <gerhard.sittig@ifm.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 375981f2e1 upstream.
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt handler to read the status register and
clear the corresponding pending bit in the clear pending register.
Modified the hwInit function to clear all the pending interrupts.
Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Client has ability to request delay per transfer through SPI
framework. SPI controller driver needs to put this delay after every
transfer. However, this also means that multiple transfers per message
cannot be combined to be able to insert this delay per transfer.
CS will be de-asserted after completion of each transfer
on older version of QUP/SPI core.
CRs-fixed: 416186
Change-Id: Id9266ce7043e020fa7e1233c66baba30ba3d496c
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
(cherry picked from commit 525593d47c425c666bdbe73c592fd5ff37cf622e)
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Support to transfer 64K bytes in a single SPI
transfer in DMA mode on targets which support
16 bits in QUP_MX_OUTPUT_CNT register. Earlier
if the application sends more than 4K data it is
split up in to 4K chunks, irrespective of the size
of the QUP_MX_OUTPUT_CNT register.
CRs-Fixed: 383120
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
(cherry picked from commit c5fbd7f2dccf52e95e6c1504a28b19d1dc622028)
Change-Id: Idb27c651e0a81a4efe363feabc44e26c5b61fb0f
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Configure the spi clk, mosi, miso, cs gpio's on per
transaction basis and unconfigure otherwise.
It will remove the conflicts if same gpio's are
being used by different modules if no SPI device
is present.
CRs-Fixed: 387043
Change-Id: Ib5c3bfbd13681f4aee0c4a815b19f423c586e160
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
(cherry picked from commit 66554a1317d40fbacd1a7e1e3210de8fb947ad57)
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
When using device tree, the bus number needs to be set based on the
cell-index property rather than the 'id' from the platform device.
This makes sure that the SPI bus number is set correctly.
Change-Id: I4489c28363a7fd79f3bc3db76207a1bc8ef507cb
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
If infinite mode is not supported, chip select goes
high after every 4k bytes. Make sure the same behavior
does not happen on targets that support infinite mode.
CRs-Fixed: 361961
Change-Id: I5cfea96202718214a8edd060e06fbb7fb2fa90a2
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
The spidev module is not being removed cleanly since
the SPI device is not being unregistered.
Change-Id: I1f97163b3eef585b420a474cdd2aacc7657e6254
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Change-Id: I4d5d611a64d8fac4c643e8eb454056ab939eff99
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding a seperate rx buffer for spidev. This allows errors
in transmission to be noticed.
Change-Id: I02258bccf1a4a5543b94c30f51294185498c3c40
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding parameters to spidev module, to allow it to be
added dynamically to the SPI bus. This allows a test
application to insmod it whenever needed and test the
SPI core.
Change-Id: Ifdb7b0c7a67f58d46ebcdc1032f0a654b6c53080
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Including the following patches:
commit 0f7723bb09440ae69743fed38cf558a838aa9bdf
Author: Bryan Huntsman <bryanh@codeaurora.org>
Date: Thu Oct 6 23:13:56 2011 -0700
Revert "spi_qsd: GPIO configuration changes for SPI chip-select line"
This reverts commit 7eaa08b75995289a91c7dd1f3616f79227f5f923.
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
commit 7eaa08b75995289a91c7dd1f3616f79227f5f923
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 28 16:26:39 2011 -0600
spi_qsd: GPIO configuration changes for SPI chip-select line
The chip-select GPIO's pertaining to each slave remains in suspended
configuration until the first transfer is intiated by the slave.
Change-Id: I3aa8555289be7ce457b91a969cf03909be0965d7
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e47df9f9b932968152ab2908153e60adab4402d7
Author: Jordan Crouse <jcrouse@codeaurora.org>
Date: Mon Sep 19 11:21:16 2011 -0600
spi_qsd: Fix possible uninitialized variable
Change-Id: Ic0dedbad184046e9835cde015ad5d592f33e82a6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
commit 4ae02c76b98f2b96bfb8c4fa02f40cfda2f16f97
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Sep 20 17:28:50 2011 -0600
spi_qsd: Fix Klocwork errors in SPI driver
Change-Id: I1fe6632e68ea625966aced37a1b140b30534e101
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 52e065ba3d86977b59937693ac7e85836cf4eca8
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Sep 1 12:12:58 2011 -0600
spi_qsd: Fix for SPI Operational State Invalid error
This error is reproted randomly when the SPI core is put
into RUN state and occurs when the ACPU clock is low.
When the timer expires, we check again to ensure that the
STATE_VALID bit is set before returning.
Change-Id: Ic8912534f4924efd999b8aa1d75a9fd19749e870
CRs-fixed: 304672
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a9a8816913e5466e06b443c42cbf8ae866b95fd1
Author: Jeff Ohlstein <johlstei@codeaurora.org>
Date: Fri Sep 2 13:55:16 2011 -0700
msm: dma: remove crci conflict checking
The crci conflict checking code was designed for a system where a crci's
mux could be changed at runtime. In reality, our chips configure these
statically, so it is not necessary.
Change-Id: I4d5f32cd8728d3c78fca8f64aed0e02b57b6afba
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
commit 36c6f1bb48af3e65db281cc7ccb913a8e81a598e
Author: Matt Wagantall <mattw@codeaurora.org>
Date: Wed Aug 17 15:44:58 2011 -0700
msm: clock: Rename all I2C/SPI clocks to 'core_clk' or "iface_clk"
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name.
Change-Id: Iab12caf4eab163773d68f1b2adc1bb4c72c69e83
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
commit 55e656e68cac78eaa367341df2e693a483a53f84
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon Jun 6 14:34:38 2011 -0700
drivers: barriers: Replace dsb() with mb()
Replace explicit dsb() calls with mb(). Now that the
generic ARM implementation defines mb() to mean (at least)
dsb(), it is appropriate to switch back to the generic
kernel version of the barriers. This is also needed for
correctness on certain targets (such as 7x27) where dsb()
is insufficient and other operations (such as outer cache
sync or writing to strongly-ordered memory) are required to
ensure proper I/O operations ordering. In some cases,
remove explicit calls to outer_sync following a barrier
since the barrier will now have an explicit outer_sync
call.
Change-Id: I2c53b8534af9c3cbac4d4d77b322f897a39e7758
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit 17194a32164b868f80ce84e313f9148d1dc77e7b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 3 18:10:09 2011 -0600
spi_qsd: GPIO configuration changes
On suspend, the SPI related GPIO's enter a low power configuration
and on resume they move to an active configuration. This helps
conserving power during power collapse.
Change-Id: I0911867e10fadcfc6950f6dddf74226bd6321c16
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 1777d88688511cd59bad7674c6a2246e0c93142b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Jun 1 16:54:07 2011 -0600
spi_qsd: Remove restriction on SPI clock speed.
When multiple slaves are connected to the SPI controller,
the driver does not allow the clock to go from lower speed
to a higher speed. This restriction is not required since
there can only be one slave listening at a time. Also,
there are no hardware limitations in doing so.
Change-Id: I4ecabfb3a1515416f050c18678cf0987dcde9d1e
CRs-fixed: 290127
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 4b7c7bfc546cb02141da9d034421aefe5635f857
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 7 14:18:42 2011 -0600
spi_qsd: Add null pointer check before dereferencing
During probe, there is no cur_msg to set the status.
Change-Id: I82e00b9d74d45c36b70078b171db1bb150d1bfac
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit bf514c766fcc2bdee680f80a2ea16c7fead0be96
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon May 16 13:37:11 2011 -0700
msm: spi: Fix access to unclocked registers
Don't program the GSBI configuration until the clocks have
been turned on.
Change-Id: Idee5f5dffcb5ed0f7de18f1e508ee8c76b618894
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit d9c248213f4cd025f3d3586f0de81e4bc44a5a54
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon May 16 16:43:08 2011 -0600
spi_qsd: Fix for SPI input overrun error
This error occurs due to a bug in the controller.
This bogus error is reported when a transition from run
to reset state occurs and if the input FIFO has an odd number
of entries.
Change-Id: I555864d4855ac6d416997da69d8bc6aee7a82178
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e99ceb5b3da7bec51be853809c25df8e32b2c1e6
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Apr 14 18:36:34 2011 -0600
spi_qsd: Multi-transfer handling
When there are mulitple SPI transfers in a message, we
default to using FIFO mode for all the transfers. As special
case, we handle a WR-WR or WR-RD transfer where we choose
between FIFO mode and DM mode based on the total length of
the transaction.
Change-Id: I6fbc1a06a22f9782db5b97c9b87cc53392a8c2fa
CRs-fixed: 276666
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 8f3d3aaa51603a929027bc820fe2d3515e959779
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Apr 19 14:19:29 2011 -0600
spi_qsd: Ensure IO operation ordering
Adding memory barriers to ensure that the writes and reads
to the SPI and QUP registers happen in the correct order.
Change-Id: I86d8f63b0e9547a2339ee4ab5c713cf8864fef04
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 36b3fae5f54230cd1e4ca072d1f55cb2f79d8945
Author: Laura Abbott <lauraa@codeaurora.org>
Date: Thu Oct 14 12:48:16 2010 -0700
spi_qsd: Fix section mismatch
The function msm_spi_probe is referenced outside of the __init section.
This fixes the problem by calling platform_driver_probe instead of
platform_driver_register since this device is not hotplugable.
Change-Id: I3a563c6fc562ada959317b54ff60a38f9ce517d8
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
commit dc2e36eecefb6628031afeff28afd9d97f2f3f6f
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 29 16:58:20 2010 -0600
spi_qsd: Changes to support DM mode.
The dma_config function may not always be present.
This change makes sure the driver gets DM resources
irrespective of the dma_config function.
Change-Id: I25a2497d20e973f22b76f2b5d6f68c86bd4d5f1d
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a39bd4a398674c320925540eec91d94d2b7d53f3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Aug 19 17:48:01 2010 -0600
spi_qsd: Modify timeout mechanism to check SPI state valid bit.
In order to allow sufficient time for the SPI state
transition to occur, calculate the timeout based on
the SPI clock speed.
Change-Id: I3d6955b2a64a8bf8980590e352fbd564250210fb
CRs-fixed: 250998
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b5887b644ba9545672d637985713c7e0e2e5bb50
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Aug 3 16:57:33 2010 -0600
spi_qsd: Use FIFO mode when DM mode configuration fails.
When the Data Mover configuration fails, the driver
uses FIFO mode.
Change-Id: Iaf83e50fe725654c58260c5cd1150cdeb56f51c8
CRs-fixed: 249238
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit ced8ad320d480006643a3aa3474f5c0d77457454
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon Jun 28 16:01:33 2010 -0600
spi_qsd: Use SW timeout instead of SPI_TIME_OUT register.
Since the software timeout is already present in the driver,
the hardware SPI_TIME_OUT register is being removed.It is just
redundant and used only for debugging purposes.
Change-Id: I829cb944444fc3e5053bc810adffe2b87f511b63
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 35e9155f59317e8ef63b8ce5190f26f5cae6a8ee
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 25 16:48:25 2010 -0600
spi_qsd: Disable irqs in the probe function.
The irqs are disabled at all times in the probe function
irrespective of the use of remote lock.
Change-Id: I0997d07b93c97a12bca6d80a9bba59682b1bec3e
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e6af92d74a35ba267125bc61c2c6c18034c03af3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 22 12:20:46 2010 -0600
spi_qsd: Disable clocks and irqs when SPI bus is not in use.
The SPI clocks and irqs are enabled per workqueue and correspondingly
disabled once the workqueue is completed.
Change-Id: Ib22b7e3b946eb4c829940e43327caaf5aff7721b
CRs-fixed: 242866
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b25e4220efdacc231cb150fc263af1e3f525b165
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Jun 8 15:25:47 2010 +0300
spi_qsd: Add usage of MX_WRITE_COUNT register
Use MX_WRITE_COUNT register to reduce the amount of TX interrupts in
FIFO mode for transfers smaller than FIFO size.
Change-Id: I7208fdc85b626a31a8b781ee5c56f73beee6c427
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 7ed56f3441c5ebe7fd8107fb8468207a88bc743f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Jun 9 16:14:44 2010 +0300
spi_qsd: Minor changes to support Data Mover mode on QUPe core
Minor changes to support Data Mover made on QUPe core.
Change-Id: I54663115a43f7fd9b52a2ddee796b5499d5f239a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a85fd0ab6484eb2ef404c062adffce1ee22337f1
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Jun 3 13:57:02 2010 +0300
spi_qsd: Add support for QUPe controller
QUPe controller is a new version of Qualcomm SPI controller. The
controller also supports other peripheral protocols, however its SPI
functionality is very similar to previous SPI core, supported by spi_qsd.
Therefore the same driver is being utilized with some register address
modification and minor flow change.
Change-Id: Ic091ef2c2ed699b43f786c278b613e69a7e9039b
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit ce270f6f9198cf40ee5638b35e595da81116241e
Author: Jeff Ohlstein <johlstei@quicinc.com>
Date: Thu Apr 29 13:40:53 2010 -0700
drivers: spi: Support ADM3 in spi_qsd driver
Change-Id: I6dfa38a4c33a8e4619d56ce30787e1aeafc8356d
Signed-off-by: Jeff Ohlstein <johlstei@quicinc.com>
commit 47346fa611773ef92d12d9145ea33a7f2c79052f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 28 11:33:15 2010 +0300
spi_qsd: Add disable/enable of pclk to suspend/resume functions
Add disable/enable of pclk to suspend/resume functions to improve
power performance.
Change-Id: I871e5ac90a998f2942778bb1e8c2c9d583a9ae00
CRs-fixed: 235046
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a96eba98fbbd21ac657f5d551466909352766ead
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:40:37 2010 +0300
spi_qsd: Making irq code implicit for the core mode in use
Make code clear regarding what mode is in use in the irq.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 6a02d85f8f48cf6f86cddc38c9fce9c1179208b4
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Apr 13 21:16:45 2010 +0300
spi_qsd: Separate tx/rx/error statistics between contexts
To improve SMP safety, separate the tx/error statistics between
contexts. This protects the statistics from accidentally being
access from another context at the same time.
Change-Id: Ibc52406e7b06a4bb5142f8a09a2f35442cb9df8a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 31f301c171aab8e42f8b6abe9b7866412cb546a8
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Mar 23 14:51:00 2010 +0200
spi_qsd: Add better handling for pending transfers during suspend
To improve SMP safety, add better handling in suspend function to wait
for graceful closure of pending transfers. This graceful closure waits
for all the pending transfers to finish or timeout, while not allowing new
ones to queue up. This allows correct handling of all the resources
involved in a transfer before suspend.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 8fbf6e4c5371520b5f9de2001e2ebd15773e918b
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Mar 25 10:44:10 2010 +0200
spi_qsd: Add mutex to get exclusive access to controller registers
To improve SMP safety, add mutex to get exclusive access to controller
registers.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 9405adda67d8c6a856243e599f09d806b4bc6de5
Author: Kenneth Heitke <kheitke@quicinc.com>
Date: Thu Apr 15 16:33:16 2010 -0600
spi_qsd: Move global input_fifo_size to device context.
Fix reference to device data input_fifo_size which is missing from the
previous patch.
Change-Id: Ia469896edd0fd90d7ded2b8ec44f9075474b3ec8
Signed-off-by: Kenneth Heitke <kheitke@quicinc.com>
commit 6031094ca6a940a47437bc6a092e813b4bc41d2a
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:34:48 2010 +0300
spi_qsd: Move global input_fifo_size to device context.
To improve SMP safety move global variable input_fifo_size to device
context.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 97f585033413b1f8ae210bbffd617a4af3462982
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 14 18:35:54 2010 +0300
spi_qsd: Initial contribution of the MSM SPI driver
This adds MSM SPI controller driver. The driver is SPI master, and
allows slave connections. Current version of the driver supports
FIFO and DM modes chosen upon the message size. The driver also
supports loopback mode which can be used for testing purposes.
This is a squashed version of all the MSM SPI driver changes on the QuIC
MSM 2.6.29 kernel which can be found at www.codeaurora.org.
It also contains all relevant adaptations to SPI core changes in 2.6.32
kernel.
https://www.codeaurora.org/gitweb/quic/la/?p=kernel/msm.git;a=blob;f=drivers/spi/spi_qsd.c;h=1c8e3ec727b29040648ef9a4949396f7109528ae;hb=refs/heads/android-msm-2.6.29b
Change-Id: Ibc1e71deb662af87deed77f10dcc8a3a46a8f012
Signed-off-by: Lena Salman <esalman@qualcomm.com>
Signed-off-by: David Brown <davidb@codeaurora.org>
commit fd316941cf upstream.
Commit ffbbdd2132
"spi: create a message queueing infrastructure"
Accidentally deleted the logic to disable the port
when unused leading to higher power consumption.
Fix this up.
Cc: Vinit Shenoy <vinit.shenoy@st.com>
Signed-off-by: Virupax Sadashivpetimath <virupax.sadashivpetimath@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 067aa4815a upstream.
Commit 178db7d3, "spi: Fix device unregistration when unregistering
the bus master", changed spi device initialization of dev.parent pointer
to be the master's device pointer instead of his parent.
This introduced a bug in spi-fsl-spi, since its usage of spi device
pointer was not updated accordingly. This was later fixed by commit
5039a86, "spi/mpc83xx: fix NULL pdata dereference bug", but it missed
another spot on fsl_spi_cs_control function where we also need to update
usage of spi device pointer. This change address that.
Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch ensures that the last bit of a transfer gets correctly
flushed out of the register.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This condition is used to determine 8 bits or 16 and 32 bits transfer.
Obviously it is reversed.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Since the member was dropped from the common Blackfin header, we need
to stop using it in the SPORT driver too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
No other SPI controller has this field, and SPI clients should be setting
this up in their own drivers. So drop it from the Blackfin controller to
keep people from using it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Each transfer may have its own bits per word.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This controller is only for blackfin 5xx soc, so rename it to BFIN5XX
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Currently, if we request for frequency greater than maximum possible, spi driver
returns error.
For example, if the spi block src frequency is 333/4 MHz, i.e. 83.33.. MHz,
maximum frequency programmable would be src/2. Which would come around 41.6...
It is difficult to pass frequency in these figures. We normally try to program
in round figures, like 42 MHz and it should get programmed to <=
requested_frequency, i.e. 41.6...
For this to happen, we must not return error even if requested freq is higher
than max possible. But should program it to max possible.
Reported-by: Vinit Kamalaksha Shenoy <vinit.shenoy@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
We were not properly advertising the MODE bits supported by this driver, fix
that.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
We do not need to use a flag to indicate if the master driver is stopping
it is sufficient to perform spi master unregistering in the platform
driver's remove function.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This patch converts the bcm63xx SPI driver to use the SPI infrastructure
pump message queue. Since we were previously sleeping in the SPI
driver's transfer() function (which is not allowed) this is now fixed as well.
To complete that conversion a certain number of changes have been made:
- the transfer len is split into multiple hardware transfers in case its
size is bigger than the hardware FIFO size
- the FIFO refill is no longer done in the interrupt context, which was a
bad idea leading to quick interrupt handler re-entrancy
Tested-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
A new enum indicating the dma channel direction was introduced by:
commit 49920bc669
dmaengine: add new enum dma_transfer_direction
The following commit changed spi-ep93xx to use the new enum:
commit a485df4b44
spi, serial: move to dma_transfer_direction
In doing so a sparse warning was introduced:
warning: mixing different enum types
int enum dma_data_direction versus
int enum dma_transfer_direction
This is produced because the 'dir' passed in ep93xx_spi_dma_prepare
is an enum dma_data_direction and is being used to set the
dma_slave_config 'direction' which is now an enum dma_transfer_direction.
Fix this by converting spi-ep93xx to use the new enum type in all
places.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
calculate_effective_freq() was still not optimized and there were cases when it
returned without error and with values of cpsr and scr as zero.
Also, the variable named found is not used well.
This patch targets to optimize and correct this routine. Tested for SPEAr.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Tested-by: Vinit Kamalaksha Shenoy <vinit.shenoy@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
pl022 ssp controller supports word lengths from 4 to 16 (or 32) bits.
Currently implemented checks were incorrect. It has following check
if (pl022->vendor->max_bpw >= 32)
which must be checking for <=.
Also error print message is incorrect, that prints "range is from 1 to
16".
Fix both these issues.
Signed-off-by: Vinit Shenoy <vinit.shenoy@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Pull ARM fixes from Russell King:
"Nothing too disasterous, the biggest thing being the removal of the
regulator support for vcore in the AMBA driver; only one SoC was using
this and it got broken during the last merge window, which then
started causing problems for other people. Mutual agreement was
reached for it to be removed."
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7386/1: jump_label: fixup for rename to static_key
ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEE
ARM: 7382/1: mm: truncate memory banks to fit in 4GB space for classic MMU
ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus
ARM: 7383/1: nommu: populate vectors page from paging_init
ARM: 7381/1: nommu: fix typo in mm/Kconfig
ARM: 7380/1: DT: do not add a zero-sized memory property
ARM: 7379/1: DT: fix atags_to_fdt() second call site
ARM: 7366/3: amba: Remove AMBA level regulator support
ARM: 7377/1: vic: re-read status register before dispatching each IRQ handler
ARM: 7368/1: fault.c: correct how the tsk->[maj|min]_flt gets incremented
Miscellaneous driver bug fixes. No major changes in this branch.
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Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull SPI bug fixes from Grant Likely:
"Miscellaneous driver bug fixes. No major changes in this branch."
* tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6:
spi/imx: prevent NULL pointer dereference in spi_imx_probe()
spi/imx: mark base member in spi_imx_data as __iomem
spi/mpc83xx: fix NULL pdata dereference bug
spi/davinci: Fix DMA API usage in davinci
spi/pL022: include types.h to remove compilation warnings
The AMBA bus regulator support is being used to model on/off switches
for power domains which isn't terribly idiomatic for modern kernels with
the generic power domain code and creates integration problems on platforms
which don't use regulators for their power domains as it's hard to tell
the difference between a regulator that is needed but failed to be provided
and one that isn't supposed to be there (though DT does make that easier).
Platforms that wish to use the regulator API to manage their power domains
can indirect via the power domain interface.
This feature is only used with the vape supply of the db8500 PRCMU
driver which supplies the UARTs and MMC controllers, none of which have
support for managing vcore at runtime in mainline (only pl022 SPI
controller does). Update that supply to have an always_on constraint
until the power domain support for the system is updated so that it is
enabled for these users, this is likely to have no impact on practical
systems as probably at least one of these devices will be active and
cause AMBA to hold the supply on anyway.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When no platform_data is present and either 'spi-num-chipselects' is
not defined in the DT or 'cs-gpios' has less entries than
'spi-num-chipselects' specifies, the NULL platform_data pointer is
being dereferenced.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Merge batch of fixes from Andrew Morton:
"The simple_open() cleanup was held back while I wanted for laggards to
merge things.
I still need to send a few checkpoint/restore patches. I've been
wobbly about merging them because I'm wobbly about the overall
prospects for success of the project. But after speaking with Pavel
at the LSF conference, it sounds like they're further toward
completion than I feared - apparently davem is at the "has stopped
complaining" stage regarding the net changes. So I need to go back
and re-review those patchs and their (lengthy) discussion."
* emailed from Andrew Morton <akpm@linux-foundation.org>: (16 patches)
memcg swap: use mem_cgroup_uncharge_swap fix
backlight: add driver for DA9052/53 PMIC v1
C6X: use set_current_blocked() and block_sigmask()
MAINTAINERS: add entry for sparse checker
MAINTAINERS: fix REMOTEPROC F: typo
alpha: use set_current_blocked() and block_sigmask()
simple_open: automatically convert to simple_open()
scripts/coccinelle/api/simple_open.cocci: semantic patch for simple_open()
libfs: add simple_open()
hugetlbfs: remove unregister_filesystem() when initializing module
drivers/rtc/rtc-88pm860x.c: fix rtc irq enable callback
fs/xattr.c:setxattr(): improve handling of allocation failures
fs/xattr.c:listxattr(): fall back to vmalloc() if kmalloc() failed
fs/xattr.c: suppress page allocation failure warnings from sys_listxattr()
sysrq: use SEND_SIG_FORCED instead of force_sig()
proc: fix mount -t proc -o AAA
Many users of debugfs copy the implementation of default_open() when
they want to support a custom read/write function op. This leads to a
proliferation of the default_open() implementation across the entire
tree.
Now that the common implementation has been consolidated into libfs we
can replace all the users of this function with simple_open().
This replacement was done with the following semantic patch:
<smpl>
@ open @
identifier open_f != simple_open;
identifier i, f;
@@
-int open_f(struct inode *i, struct file *f)
-{
(
-if (i->i_private)
-f->private_data = i->i_private;
|
-f->private_data = i->i_private;
)
-return 0;
-}
@ has_open depends on open @
identifier fops;
identifier open.open_f;
@@
struct file_operations fops = {
...
-.open = open_f,
+.open = simple_open,
...
};
</smpl>
[akpm@linux-foundation.org: checkpatch fixes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Commit 178db7d3, "spi: Fix device unregistration when unregistering
the bus master", changed device initialization to be children of the
bus master, not children of the bus masters parent device. The pdata
pointer used in fsl_spi_chipselect must updated to reflect the changed
initialization.
Signed-off-by: Kenth Eriksson <kenth.eriksson@transmode.com>
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
