An iommu page fault may heppen When a pipe_commit is executed
in between of frame dropped and pipe_queue during overlay play.
An mutex is necessary to mutual exclusive between pipe_commit
and overlay_play.
Change-Id: I736e821c6c648a6ebd435303a1906a40e9b75791
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
Dcs command mode BLT involves both overlay0 done interrupt
and dmap done interrupt. A transaction is start at kickoff and
end with done interrupt. At some cornor cases both overlay0 and
dmap transaction need to be completed before kickoff new transaction.
Change-Id: I5a3cc6e8255acf2c61fc627d35f990182d226f63
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
To avoid double freeing writeback at end of blt mode, let
both alloc and free writeback buffer done at do_blt().
Change-Id: Ida5d24589c19be8f6f655eca6add00badca356b2
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
There has VG1 pipe commit (pan display) happen after system
suspended. This left VG1 still staged up at mdp mixer. Once timing
generator is enabled at resume, VG1 pipe start fetching contents from
address 0 since VG1 has not yet be configured. This cause page fault.
This patch has sanity check at system suspend to make sure no any pipe
stage up at mixer after suspend.
Change-Id: Idcf974ceb4afe2a3ec55b9603b700fa497f84045
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
An earlier commit(ec5b2f)increased the number of reserved fields
in the kernel standard fb.h header changing the struct size.
This caused issues with userland applications using the corresponding
bionic header. This patch revert the earlier increas in size
and makes corresponding adjustments to the reserved field usage.
A follow up patch will remove usage of reserved fields entirely.
Fix the problem crashed while playing video clips and VT camera test.
ion_share_dma_buf is called in pr_debug.
So, it is called depends on build option and makes crash problem.
Since msm_fb_blank_sub() can be called from hdmi which has no
backlight, we should check the null pointer before to run the
get_backlight_on_status().
Change-Id: I9a91dc337b56e20fbfd82347cf429350f1a72b37
To avoid dispalying garbage during lcd on/off, the turning on
lcd should be done before backlight on and turning off backlight
should be finished before lcd off. But current implementation
doesn't guarantee these on/off sequence. This patch ensure the
sequence of lcd and backligth on/off.
Change-Id: I11771d395c1a68b4e70b63639f50c773a665b441
Signed-off-by: Iliyan Malchev <malchev@google.com>
Conflicts:
drivers/video/msm/msm_fb.c
In case of data underflow, MDP display specific color on lcd.
Due to data underflow rarely happen during display on/off,
we can see unintended blue screen at that time.
So this patch changes this underflow control color from blue to black
for hiding unintended blue image displaying during display on/off.
Change-Id: I26910065b5210a2571125d25f3f1b41a67ba1c1c
Add lcd color temperature calibration interface and apply
the calibrated value to the target using mdp lut.
Change-Id: Ibdd606a155e0d7708ba79be6f817c3d89b51a282
CABC(Content Adaptive Backlight Control) is supported by
mako lcd panel. So this patch enables it to reduce power
consumption.
Change-Id: I433281bc5fe4e638cfeba1beb9cb61e1775f3896
update lcd initial code and change power on sequence for
new initial code.
Change-Id: Ic876d5dbef3528591ca374ba0f67f073f4584534
Signed-off-by: Iliyan Malchev <malchev@google.com>
sleep 300ms until completing the backlight control. and then set
the panel_power_on and bl_updated as false
Change-Id: Ia289cdcd08ad012d192a079dd1b765d74b911be2
- set initial qcom lcdc lock up table
- interface to calibrate lcd color temperature
- interface to calibrate lcd color temperature by qlut
Change-Id: Iae2607a2ec3447211cdce5e55fac5767cc6d7fb4
If suspend event is received by MDP before panels, MDP needs to ensure
other panels are off before turning MDP clocks off. Remove handlers from
framebuffer driver and handle all suspend logic within MDP driver to
handle this scenario.
Change-Id: Idcda2dd29b28a9993edca78b7e0778985e44b664
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Current clock logic only considers panel pixel clock to calculate mdp
clock speed, MDP clock speed should also consider other factors such
as surface scaling. Bus scaling should also consider surface scaling
factor. Update logic to consider these new factors and perform these
performance updates together.
Change-Id: If274a7f40f496e1a730e1d0e8d7c35fa4384a832
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
When panel size is increased dma_alloc_coherent is not able to find
a chunk of contiguous memory big enough to hold framebuffer, this causes
framebuffer initialization to fail. Allocate buffer from ion pool which
has reserved contiguous memory at earlier stage.
Change-Id: Ibf7e3f7fc2c7ad991d69c106bbb6a9dd4c7f0e79
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
When in resume or boot time, baselayer pipes need to be committed for
mdp to play, otherwize underruns and blue screens are seen. The
previous pipe stage up func has this commit which is removed now, so
the commit calls have to be added for the cases where base pipe is
initialized.
Change-Id: I63a7d0ac3fb078b3d7f604eb646a0430326a478c
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Fix typo in code which is causing incorrect setting of vertical front
porch on timing generator settings and incorrect output to panel.
Change-Id: I4de61209443fcb284b7d4064a2039b5f546935d1
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Currently mdp clk and bw requests are predefined in a 4-entry table
passed from the board file, and the logic to decide which level to use
is mainly based on source resolution. This patch is intended to
address several issues with this approach.
One major issue is clk and bandwidth depends on seperate things, and
need to be considered seperately. e.g. with mdp composition of
multiple pipes, bw request may be high but clk requirement may still
be low. The current approach that binds these two things together
causes inefficiency of power.
Another major issue is that there is no logic to calculate mdp clk
requirement of a single pipe based upon panel clk and downscale
parameters. Further the worst case of mdp clk should be determined by
all pipe usage. Without proper logic, many underrun have been
experienced, and blt mode may not be enalbed properly.
Also mdp_clk or blt mode update must be on right timing especially
between these two pathes: overlay play and pan display. In the
situations of performance from high to low or from low to high clk and
blt must be handled properly to avoid underruns.
In a summary, to support many different panels and targets and
complicated mdp pipe usage(mdp composition), mdp driver related to clk
and bw needs to be implemented differently. This patch is to seperate
clk and bw, and maily to deal with mdp clk and blt. Later increasing
granuity of bw will be added.
Change-Id: I678fbf86d6997ed7b602ce81cf2e0fff6164d129
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Timing generator was getting started before the register flush.
Stale values were sometimes causing IOMMU page faults on bootup.
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Change-Id: Ia671c3603e383af94197a23a8e5e5f32274a9978
Since stage commit had been splited out of stage up fucnction,
it needed to be called to stage pipes into mixer befroe
kickoff mixer. Add this function into overlay writeback for WFD.
Change-Id: I11e4486d92b89a15e58531033d474b3137b5935a
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
In case ASIC 1.1 is used on 8064 platform, LVDS bit mapping
misalignment is fixed and no remapping is needed. LVDS bit
mapping should comply with VESA format to get correct panel
display.
Data line #3's bit mapping should be coded in this sequence:
DE + VS + HS + .... Change the original codes to go with this
sequence.
Change-Id: Iaebcfcea9c52207e16bac54ec37dc63e97286ff4
Signed-off-by: Lei Zhou <leizhou@codeaurora.org>
Wait for dmap done to turn off TG to avoid underruns before base
pipe setup and after constant splash during boot time.
Change-Id: I64bc3935d996af1d2d54db4c11319301ea454ced
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
We get the error message for the incorrect aspect ratio
with each frame of the video. By reducing the priority,
error message will appear only when we enable it.
Change-Id: Iacb8002383ea6c0b7ee86e9cfe14478c0e5ca5c3
Signed-off-by: Rajeshwar Kurapaty <rkurapat@codeaurora.org>
If a panel probe does not succeed, call mdp_clk_ctrl to maintain
mdp_clk_cnt counter else mismatch in counter results in mdp clock
to never go off in cases like suspend-resume.
CRs-Fixed: 385560
Change-Id: I4ca54b051af98e823dc7f3ff7b9bcb960532c7e8
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Increase the upper limit for the pixel clock that
changed with the newer version of the DSI controller.
CRs-Fixed: 380003
Change-Id: Ibbeaa478b4d12ae8f350be41f959d53a6ae6c923
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Using RGB888 as source format and rgb565 as destination pixel format,
will cause image corruption on the display. Fix this issue by
setting the destination format as RGB888 in MDP and DSI controller
pixel format as RGB565 for DSI specific panels.
CRs-Fixed: 377484
Change-Id: If58976ee9cd4825efb39437170e54796fa2213e0
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Improper yuv buffer size is being calculated using frame
height directly, which is resulting into failures during
encoding if the frame height is not aligned to 16.
With this change, yuv buffer size calculation is done
properly by using scanlines in place of frame height.
Change-Id: I22602d6a0eddfa4016f4bdc3479e5b7d9b89a4e7
CRs-Fixed: 378988
Signed-off-by: Deepak Verma <dverma@codeaurora.org>
At run time, mdp BLT (writeback) mode is enabled and disabled
base on performance level to avoid mdp underrun. Move BLT
enabled/disabled logic to pan display so that enabled/disable
is done per commit instead of per queue. Since all panels
are shared same logic, dsi video mode and lcdc panel BLT logic
have been changed accordingly.
Change-Id: I6e04bf0f7bf1c13634e19b18d8ac4368affbc4d8
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
For multi-resolution clips, the meta data offset used while
doing cache clean of meta data buffer is from the previous
resolution & resulting in kernel panic. Resetting the offset
to zero during meta data buffer initialization for new
resolution fixes the issue.
Change-Id: I06b20e10efc837fcfe44f532e90293734b4d2df8
CRs-fixed: 386245
Signed-off-by: Rajeshwar Kurapaty <rkurapat@codeaurora.org>
Need to give proper buffer size for snprintf function calls.
CRs-Fixed: 378343
Change-Id: Ia4df74c9871b26255572bb3ba226317c3076b5b6
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Base layer pipe is cloned and cached at satge array.
Retrive the real base layer pipe before used it.
Change-Id: I6fc606559684156348a57b500083ed4089fc71b5
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Free iommu buffer after pipe is committed to hardware.
Change-Id: I00506d6fd55d99fec7921c02953fd755a7536d3e
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
