New characterization data shows that vdd_dig voltage for L2@384MHz
can be lowered to 0.95v. Update the data in this patch.
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
(cherry picked from commit 7a904ecd4f43f228cd1b3ea0d8ef4054b69cdb35)
Change-Id: I7f38657930231ce8969bd16e793b57e606fcd162
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
We have an active set vote for the multimedia fpb and chip fpb so
that the registers are accessible whenever the processor is
awake. Unfortunately these requests are at the highest rate
supported which is not really necessary to ensure that the buses
are clocking. Lower the rate requests to the fastest speed that
doesn't require increasing voltages to allow the chip to hit low
voltages when the processor is awake.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 9e497f042d8525e57e11d417e9e37c2932a18dbf)
Change-Id: I3ee4926da0d953e7e31c3c64dffd11f6ee5edb72
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
while queueing requests to USB HW, waiting till EP PRIME bit
get cleared after setting it leads to wathdog timeout. Fix
this by implementing timer based solution instead of infinite
PRIME check loop.
(cherry picked from commit 9e4a5053b0f25cb18ed394fa517be620db673d44)
(cherry picked from commit dcfe03cd167f1b4916de85ce0a0a5516191741cc)
CRs-Fixed: 397907
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Change-Id: Iad7504c77c02870d9fa3b7b9decf13afcf2c9e12
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Due to higher HSIC interrupt threshold value, sometimes
driver is running short of enough rx urbs queued to HSIC
HW to receive IP packets from mdm device. In this case
driver is busy processing large number of completed rx
urbs and left with fewer pending urbs with HW. This causes
occasional throughput drops on rx data path. Hence increase
number of rx urb from 50 to 100, to keep HSIC HW busy in
pulling data from mdm device while completed urbs are getting
processed.
(cherry picked from commit e8f691f60db39b50951148c3e68ae35c89cdd397)
CRs-Fixed: 397809
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Change-Id: I590c203551c5ac83a71b8628d195f2a15840edf1
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
If MBHC GPIO IRQ for mechanical headset detection asserted while power
management's suspend call chain is being called, wcd9xxx_lock_sleep will
fail to wait for system's resume since power management interface has
to finish suspend in order to resume system.
In this case, interrupt cannot be handled as codec driver cannot
guarantee if underlying bus is awake.
Wake up system and resend the IRQ for this situation.
(cherry picked from commit ecf379cd17b7fe94e6f0df0598a472b6f1828ad5)
(cherry picked from commit bdda99b93915d217150f5484f9c718c905703f1e)
CRs-fixed: 404167
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Change-Id: Id5970b359b80e0cd1f701b30c61ade23e0f67b9e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Add necessary functions for AR6004 to control BT related GPIO.
This change will only be used by AR6004
(cherry picked from commit 9baad179a8a7996e1912de14eb6f02f17c932e03)
(cherry picked from commit 493557fce821ae201b4cc3c6a125d703ac5de60e)
Signed-off-by: Ming-yi Lin <mylin@codeaurora.org>
Change-Id: I0fb3a59761dc3e994254bdc0241281e4bbcdf402
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
SMD or any client for WCNSS SSR notification can use the same name
(wcnss) for both Pronto and Riva.
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Change-Id: I956d9623f99855402add40b3e999bfacace7d2f3
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Toggle the CHG_USB_SUSPEND bit when utilizing the VBUS boost.
This bit controls ensures that no current is being drawn from
a USB device and the charger runs off the battery.
This makes sure that when pm8921_disable_source_current is called
the correct setting is written to the suspend bit depending
on the disable flag.
(cherry picked from commit d8878596b9b19668fd1f1b226a333d955f2218c4)
CRs-Fixed: 393498
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: Iae390fd10e59d6ba1fe85743c1015eea35b06f7a
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
(cherry picked from commit 19a992314983c132d97b0d670b40e535580955da)
Signed-off-by: Jay Wang <jaywang@codeaurora.org>
Change-Id: I16af92f174ac8a9b9ac15e96cbf2b89db4de1df5
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
ID ground interrupt processing and system suspend can run in parallel.
When Id is grounded, USB is brought out of low power mode(LPM) and state
machine work is run to activate host mode. While waiting for the VBUS
valid event, device suspend callback is executed from system suspend
context. The current code put USB in LPM, without activating host mode
completely. Abort suspend when A_BUS_REQ is asserted which indicate
that host mode is active.
(cherry picked from commit cfe0539e389c52ec6c4d99cf1915d806d42f1abe)
CRs-Fixed: 412841
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Change-Id: I9ecd4f55a328d63ddbf0e415a9bcff1158874203
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
8MA drive strength is causing GSM DCS/PCS RX band desensitization.
Hence, the GSM subsystem needs the drive strength to be 2MA for this gpio.
(cherry picked from commit 7a026522ee2d2436de37b43051a6530a39b8421a)
CRs-Fixed: 401569
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Change-Id: I4c39e3c62b6eb9faa8d227d3e146b1189109ec9c
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently parity bits are defined to be used with UART_DM_MR2
register with PARITY_MODE Bit as below :
EVEN_PARTIY = 1 and ODD_PARITY = 2
With these values, UART functionality doesn't work after enabling parity.
Hence adding correct used PARITY_MODE bits value as
EVEN_PARITY = 2 and ODD_PARITY = 1
after confirming with UART hardware programming guide.
CRs-Fixed: 410377
Signed-off-by: Saket Saurabh <ssaurabh@codeaurora.org>
(cherry picked from commit fd40e5f6313fbc74e8897927be1004faa5d9df08)
Change-Id: I56f1a46ab56a7976ad00fc1329ad766b1182cb4e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
MSM8930 with PMIC8917 does not support HDMI. This change
ensures that HDMI clock domains are not set/reset as part of the
MDP GDHS sequence for this particular configuration.
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
(cherry picked from commit 66fae64b1d7f66541b75675fe2c24c69e1bd87cf)
Change-Id: Ie7ea77abf97b0857a72e32af6dbdb118038df620
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
When recording is started, it is observed that the pop level is
much higher than expected. Fix this issue by enabling the High
Pass Filter on microphone path with a cut off frequency of 150Hz
when recording starts and reprogram the cut off frequency back
after a timeout of 300 millisecond.
CRs-fixed: 380966
(cherry picked from commit f9ed163835d1634a86cabc233d85bfe857f0eacf)
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
Change-Id: If98dfaf0f9b8f14c306f2d6a59154a615752823b
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
RPM maintains PC stats for each master in MSG RAM and it allocates
256 bytes for this use. No of masters differs for different targets.
Initialize the resources for rpm_master_stat platform device.
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Change-Id: I0a44b083fd01a852ba214ecf1d2e6d953c154ed5
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
rpm maintains stats on power collapses and the list of active cores
for each master in its msg ram. Provide support to display it
through debugfs.
ex:-
mount -t debugfs none /data/debug
cd /data/debug
cat rpm_master_stats
The above commands will display no of power collapses and active cores
for each master. Sample output on 8960 is below
KPSS
num_shutdowns:0
active_cores:7
core0
core1
core2
MPSS
numshutdowns:10
activecores:0
LPASS
numshutdowns:20
activecores:1
core0
RIVA
numshutdowns:9
activecores:0
DSPS
numshutdowns:90
activecores:0
L2 cache also consider as another core in the stats.
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Change-Id: I570335c11f744663819ab040705fe715183bda8a
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
When front-end PCM session is in paused state, back-end PCM
session will be put in paused state as well if given front-end
PCM session is the only client of the given back-end. Then,
even though the application closes front-end PCM session, DPCM
framework will not allow back-end to enter into HW_FREE state,
and hence back-end will never get shutdown completely.
(cherry picked from commit 6479fa2d82c5fa8b756a4755bc84e2ce48dad850)
CRs-fixed: 411089
CRs-fixed: 409894
Signed-off-by: Banajit Goswami <bgoswa@codeaurora.org>
Change-Id: I4d4f856a0401ff96cef98d374c1d12b10e124528
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
It is possible that clients of the sysmon may call its APIs
before the associated device has probed, after it has been
removed, or while it is in the process of being added or
removed. Handle these scenarios and return -ENODEV when
external APIs are called at illegal times.
(cherry picked from commit 9319017b803cca3fd479e589db3d8d3560e19511)
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Change-Id: Idb7bfd410957efe63ab4917d9481922de25287c4
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Power key could be in pressed state during boot. Set the flag
to track the press status properly by reading press irq status.
(cherry picked from commit bd38250554df6e70657e6ff42ad63415dbd53f1a)
CRs-fixed: 404018
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
Change-Id: I1b604b63e53803483d3cc2a7bae0a5e7ed98285b
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Add support to allow drivers to specify future events
that need to be treated as hard deadlines. Upon event timer
expiry the driver will be notified by callback function
that the driver provides.
The pm code can query the earliest event and modify
the event timer accounting for the back off based on the
latency of the low power mode being entered.
(cherry picked from commit 388c308cebef8e9cdbd80608a032abc810d46e62)
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Change-Id: I461e2c31c285b93588aa56dd25905efab020e0c8
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Enable Event timer feature. This feature enables PM
code to monitor events that require the core to be ready
to handle the event.
(cherry picked from commit 19d00d50f5b09a25712133ed0b329cc9c5c3d1d8)
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Change-Id: Ib56e49edd00bea35ab7395bb038a627f43187f57
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Get the next event and setup a new timer to expire
earlier than the next event after accounting for the
latency of the low power state being entered. This
will ensure that the core is active to handle the event
when it arrives.
(cherry picked from commit dc318fd0c3d04f7af9720af50c0eb0c6ed2653e9)
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Change-Id: I6609a886df227c68ce78e270ef7d235e07725d44
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Debug symbols in installed kernel modules consume space
in the target filesystem, so strip them. Modules with
debug symbols should be present in the KERNEL_OBJ
location for debug purposes.
(cherry picked from commit bb77a75767f5dbb7327ab05f4ec4462b6ad62b10)
CRs-fixed: 400053
Signed-off-by: Nagender Telkar <ntelkar@codeaurora.org>
Change-Id: I4353e3733455e01cbe97c023d36b9bd3b7b8adf2
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
- AFE does not support sampling rate 44.1k
- This fix addresses the issue by setting backend proxy device
sampling rate to 48k
(cherry picked from commit 69ab7356a72981032d5d403ec1508dcfaeb7075f)
CRs-fixed: 413871
Signed-off-by: Jayasena Sangaraboina <jsanga@codeaurora.org>
Change-Id: Ic067178f9d4cdb51b8fee5292b960922088c8539
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently, RMNET will restart the TX queue after receiving a
low-watermark notification from SMUX. This just clears the XOFF bit,
but does not reschedule the TX thread in the Linux TCP/IP stack. This
means that the next TX operation will not take place until the thread is
scheduled by some other means which may take up to 5 seconds.
Instead, wake the queue which clears the XOFF bit and schedules the TX
thread to allow transmission to continue immediately.
(cherry picked from commit 4d8fb2ecb3a9cdab3e9d605280256c6b46773dd0)
CRs-Fixed: 412758
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Change-Id: I1f169547f3ff518baada632d5a3f766b5795c697
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
The min_dpb required for smooth streaming is set for the
max requirement of 1080p playback session. This is set in
vidc platform data in the device file.
(cherry picked from commit 885fcc57354cd309f5ed0356da486d1e130b9ad7)
CRs-fixed: 408738
Signed-off-by: Mohan Kumar Gubbihalli Lachma Naik <mgubbi@codeaurora.org>
Change-Id: I38c3c9931f573cb029871bd48fd161f2158e139e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
During playback of audio on earpiece path, the PA on the path
is the last component to be turned on. The turn on of PA can
cause a glitch in the output signal because the level of the PA
is not yet settled. Waiting for 20 msec after turning on the PA
avoids this glitch.
CRs-fixed: 417031
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
(cherry picked from commit 1fa994d4aa256a536523f116232c4822b3495400)
Change-Id: Iaa7a47526c71d8b037df3d09cf30ede296c21356
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
In one corner case, the SD card is stuck in a bad state with its DAT0
line pulled low, and SDCC is waiting on the interrupt when the line
goes back high. But due its bad state eventually the SD card is removed
from the system.
Later during re-scanning of the devices, the SD card is power-cycled and
added to the system. But now the pending interrupts for SD card is
received as the interrupt MASK register (MCI_MASK0) was not cleared.
To prevent such cases reset the interrupt MASK register (MCI_MASK0) while
powering off to prevent any pending interrupts after power-cycle.
(cherry picked from commit a3f8f793b21782c79a9fcc5f7aa1cc27fcbf246e)
CRs-Fixed: 396706
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Change-Id: Idfae18895abf47769328b0a768f83eba2ef573f7
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Setting DDR timing mode in controller before setting the clock
rate will make sure that card don't see the double clock rate
even for very small amount duration. Some eMMC cards seems to lock
up if they see clock frequency > 52MHz.
(cherry picked from commit 2877d919135791d5223a9ba94b2cfc9ba50bc3df)
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Change-Id: I7a4ace461e2def6d53863db4b768ec7e497b3095
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
In the usb_ma_table there exist two consecutive values
that have IUSB_FINE_RES bit set. Some functions
incorrectly assume that this does not happen.
Fix this by checking for consecutive values having
IUSB_FINE_IRES bit set.
(cherry picked from commit 67ebde08e12d246302d133b4510d59c8f96325d1)
CRs-Fixed: 404348
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: I6b6ca96b92ec4b9765e4812352057a0ac8cff380
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Add msm_spm_get_vdd() API to return the core active voltage
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 4133ba1e1c9384910cd6db56130b654af115651d)
Change-Id: I76bcfbcb0eefda09757e9db86ba4adb76a44f2f7
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
This workaround can be removed in favor of an alternate solution
implemented in the power-collapse path which backs up the
corruptable L2CPUCPMR and L2CPMR registers before L2 power-collase
and restores them afterwards.
CRs-Fixed: 400700
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
(cherry picked from commit aa48fc35e051363b997bd33928796e3e84d08d88)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
Change-Id: I4a9962d95a4a7a835042dde91eee6b89754ea86b
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
During power collapse, the AVSCSR register is always enabled and never
restored. This could result in AVS getting enabled on resume, when the
core is running at a frequency that doesn't support AVS.
Add new API, avs_enable, which restores the AVSCSR register based on the
saved AVSCSR register. Update the avs_disable API, to return the
AVSCSR register value prior to disabling the AVS.
(cherry picked from commit ad138da17fe08d46412d56b84309c5d17f7d5931)
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Change-Id: I2bd2e1d6aea058e0f44c474da6c3121654f1236e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently, hash (SHA1/256/hmac) operation occasionally results
in an incorrect hash value. This is due to the premature reading
of the AUTH_IV register done before the last SHA block is processed.
There needs to be enough delay (wait states) before the AUTH_IV
register is read to extract the hash value.
The current implementation has 2 wait states. Adding 2 more wait states
for hash operations, resolves the issue.
The wait states are calculated based on the inputs from the hardware
team with regards to the time taken to process the last block of 16
bytes of the data packet.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Change-Id: I82936441429560e41f25a98994d49a0113eb8de2
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
- During aac playback, multiple seek lead to target freeze.
- DSP starts decoding when internal buffer size maximum is
reached, hence, if there are corrupted frames in that buffer,
the entire set will not be decoded. This results in target freeze.
- Fix is to set the end of frame flag in the buffers that
are sent to DSP for decoding.
(cherry picked from commit 08508ac42fed7b1e3a7a9b7e098dfb4ceff8b836)
Signed-off-by: Swaminathan Sathappan <Swami@codeaurora.org>
Change-Id: Ic34272222dcb1df42d7e2fe5d028d513b8cf452f
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
LPASS clock are enabled out of reset on these SoCs, with PXO selected
as their undivided source. Because PXO rates are not present in the
frequency tables however, these clocks fail to handoff with reason
'HANDOFF_UNKNOWN_RATE'. As a result, clock_late_init() does not attempt
to disable these clocks in lateinit.
Add PXO rates to the LPASS frequency tables so that handoff succeeds
and, in lateinit, disables them if they are not used.
(cherry picked from commit ac15a37fd85089a2aef16624140a5d0a6cd1d71b)
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Change-Id: Id8d674bfa3d41316be8aa14c5cc84baa77078d23
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
The A330 GPU defines a few new registers that don't exist on
A305/A320. Define a new subset for A330 and dump it in the
postmortem and binary snapshot.
Change-Id: Ic0dedbadd0c44ee8872b99fd6b0b3dc8eb972eea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Expand the snapshot register dump helper function to support multiple
sets of registers. This will be useful for derivative GPUS that
use a global subset of registers and add a few new ones. This will
not be useful for chipsets that have extensive changes to existing
registers.
Change-Id: Ic0dedbad05bcc3b5a3a0cc933659959965ff5817
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The CP MERCIU queue can be read from the A330 GPU. Dump it into
the snapshot binary.
Change-Id: Ic0dedbadf2c61ccec6a11af103374f4aee8be727
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The A330 has a larger ROQ buffer then the A305/A320 variants so
adjust the size at runtime based on the core type.
Change-Id: Ic0dedbade62c988cfe402876bc94d91a2dd71617
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Create adreno_is_a330() to identify the GPU for A330 specific
register settings and core specific code.
Change-Id: Ic0dedbade244ffba3ba3917661a88f97108e6182
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Increase number of clocks that RBBM will wait before de-asserting
the Register Clock Active signal. This fixes kernel panics during
stability tests on multiple devices
Change-Id: I6f7f8bb17cfd9c5beed0fd21d56ab6ab9fd40195
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
For A3xx, initialize UCHE_CACHE_MODE_CONTROL_REG to
0x00000001 so that UCHE will always use 64-byte
cachelines when we boot up or reset. This value
increases performance and was previously set in the
graphics preambles, but should instead be set at
boot/reset time.
Change-Id: Iec71ffc04262ac43534fd632d8b092a48d280509
Signed-off-by: Kevin Matlage <kmatlage@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
GPU register RB_GMEM_BASE_ADDR needs to be initialized with GMEM base
address. From A330, OCMEM is utilized to be GMEM dynamically; when
OCMEM is allocated for GFX, the allocated region address may vary
every time, GPU register RB_GMEM_BASE_ADDR need to be initialized
with the allocated OCMEM region address.
Change-Id: I5cb4472a9f18759d2af160a15d83f1404378a530
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
No need to save a context if it is being destroyed since
it will no longer be used at all. This is better for
performance and also avoids the use of legacy kgsl
context save code for contexts that use preambles
Change-Id: I19a64e82188b4132f353bb61c21e4ed2281092fc
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the register offsets for IOMMU-v2 and switch off using per
process pagetables for IOMMU-v2.
Change-Id: I8b76de557c8e52b5a2a333ceb987bd743b213eb7
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Changed values written to VBIF registers for A330.
The maximum pending request from clients is increased to 24.
Disable VBIF clock gating. This potentially increases stand-by power.
Change-Id: Ic9a4f15546f4122298e140e79e4572c82e6385fc
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the IOMMU register offsets in a structure array. This
offers flexibility in defining IOMMU v2 offsets in another array
and the right array to be used can be setup during MMU
initialization.
Also, restrict the usage of IOMMU offsets only in the iommu file
by redifining the functions that return iommu information. Remove
the function to get iommu mapped register address and replace
it with a function that returns the gpuaddress of given iommu
register. Only return the valid address bits of an iommu pagetable
instead of just returning the pagetable base register value.
Change-Id: Ib88e605f57e551c7b84029647451cb20f06025a0
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Calling clk_set_rate() for both AXI & 2D core clocks without putting
them in async mode causes 2D core hang. Since AXI & 2D core clocks
are in sync mode, ensure that clk_set_rate() is called only for AXI
& 2D core clock is enabled only after it is prepared.
Change-Id: I4634e2342d62ce16ad7afc748b10b0573fbfd913
CRs-fixed: 385393
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
