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d99e455e8d
commit a3e6c1eff54878506b2dddcc202df9cc8180facb upstream. If the irq_chip does not define .irq_disable, any call to disable_irq will defer disabling the IRQ until it fires while marked as disabled. This assumes that the handler function checks for this condition, which handle_percpu_irq does not. In this case, calling disable_irq leads to an IRQ storm, if the interrupt fires while disabled. This optimization is only useful when disabling the IRQ is slow, which is not true for the MIPS CPU IRQ. Disable this optimization by implementing .irq_disable and .irq_enable Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8949/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Zefan Li <lizefan@huawei.com>
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*
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* This file define the irq handler for MIPS CPU interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Almost all MIPS CPUs define 8 interrupt sources. They are typically
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* level triggered (i.e., cannot be cleared from CPU; must be cleared from
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* device). The first two are software interrupts which we don't really
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* use or support. The last one is usually the CPU timer interrupt if
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* counter register is present or, for CPUs with an external FPU, by
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* convention it's the FPU exception interrupt.
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*
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* Don't even think about using this on SMP. You have been warned.
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*
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* This file exports one global function:
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* void mips_cpu_irq_init(void);
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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static inline void unmask_mips_irq(struct irq_data *d)
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{
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set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_enable_hazard();
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}
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static inline void mask_mips_irq(struct irq_data *d)
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{
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clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_disable_hazard();
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}
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static struct irq_chip mips_cpu_irq_controller = {
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.name = "MIPS",
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.irq_ack = mask_mips_irq,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mask_mips_irq,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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};
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/*
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* Basically the same as above but taking care of all the MT stuff
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*/
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static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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unmask_mips_irq(d);
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return 0;
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for mips_cpu_irq_end.
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*/
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static void mips_mt_cpu_irq_ack(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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mask_mips_irq(d);
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}
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static struct irq_chip mips_mt_cpu_irq_controller = {
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.name = "MIPS",
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.irq_startup = mips_mt_cpu_irq_startup,
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.irq_ack = mips_mt_cpu_irq_ack,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mips_mt_cpu_irq_ack,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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};
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void __init mips_cpu_irq_init(void)
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{
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int irq_base = MIPS_CPU_IRQ_BASE;
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int i;
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/* Mask interrupts. */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP);
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/* Software interrupts are used for MT/CMT IPI */
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for (i = irq_base; i < irq_base + 2; i++)
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irq_set_chip_and_handler(i, cpu_has_mipsmt ?
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&mips_mt_cpu_irq_controller :
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&mips_cpu_irq_controller,
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handle_percpu_irq);
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for (i = irq_base + 2; i < irq_base + 8; i++)
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irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
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handle_percpu_irq);
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}
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