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f5ca55b4c6
This is first release of otg driver for the dwc3 Synopsys USB3 core. The otg driver implements the otg final state machine and control the activation of the device controller or host controller. In this first implementation, only simple DRD mode is implemented, determine if A or B device according to the ID pin as reflected in the OSTS.ConIDSts field. Change-Id: I6533490aa2adfe3641ffa926666867c19a979217 Signed-off-by: Ido Shayevitz <idos@codeaurora.org>
27 lines
711 B
Text
27 lines
711 B
Text
config USB_DWC3
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tristate "DesignWare USB3 DRD Core Support"
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depends on (USB || USB_GADGET)
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select USB_OTG_UTILS
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select USB_GADGET_DUALSPEED
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select USB_XHCI_PLATFORM
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help
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Say Y or M here if your system has a Dual Role SuperSpeed
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USB controller based on the DesignWare USB3 IP Core.
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If you choose to build this driver is a dynamically linked
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module, the module will be called dwc3.ko.
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if USB_DWC3
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config USB_DWC3_DEBUG
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bool "Enable Debugging Messages"
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help
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Say Y here to enable debugging messages on DWC3 Driver.
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config USB_DWC3_VERBOSE
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bool "Enable Verbose Debugging Messages"
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depends on USB_DWC3_DEBUG
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help
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Say Y here to enable verbose debugging messages on DWC3 Driver.
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endif
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