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https://github.com/followmsi/android_kernel_google_msm.git
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6cd3e6cb79
MSM9625 implements ETM based on ETM version 3.5. As such the 9625 ETM registers need some additonal configuration for ETM to be functional. They also have some extra registers which need to be configured properly while some registers currently being configured by the driver are absent on 9625. Additonally, the ETMv3.5 can be configured to support data tracing, support for which is not present in the existing ETM driver. Change-Id: Ic3e61d0d1abf371653a398a28111b308747a7b6f Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
171 lines
4.6 KiB
C
171 lines
4.6 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _LINUX_CORESIGHT_H
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#define _LINUX_CORESIGHT_H
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#include <linux/device.h>
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/* Peripheral id registers (0xFD0-0xFEC) */
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#define CORESIGHT_PERIPHIDR4 (0xFD0)
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#define CORESIGHT_PERIPHIDR5 (0xFD4)
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#define CORESIGHT_PERIPHIDR6 (0xFD8)
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#define CORESIGHT_PERIPHIDR7 (0xFDC)
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#define CORESIGHT_PERIPHIDR0 (0xFE0)
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#define CORESIGHT_PERIPHIDR1 (0xFE4)
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#define CORESIGHT_PERIPHIDR2 (0xFE8)
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#define CORESIGHT_PERIPHIDR3 (0xFEC)
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/* Component id registers (0xFF0-0xFFC) */
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#define CORESIGHT_COMPIDR0 (0xFF0)
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#define CORESIGHT_COMPIDR1 (0xFF4)
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#define CORESIGHT_COMPIDR2 (0xFF8)
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#define CORESIGHT_COMPIDR3 (0xFFC)
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#define ETM_ARCH_V1_0 (0x00)
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#define ETM_ARCH_V1_2 (0x02)
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#define ETM_ARCH_V3_3 (0x23)
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#define ETM_ARCH_V3_5 (0x25)
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#define PFT_ARCH_MAJOR (0x30)
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#define PFT_ARCH_V1_1 (0x31)
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enum coresight_clk_rate {
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CORESIGHT_CLK_RATE_OFF,
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CORESIGHT_CLK_RATE_TRACE,
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CORESIGHT_CLK_RATE_HSTRACE,
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};
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enum coresight_dev_type {
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CORESIGHT_DEV_TYPE_NONE,
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CORESIGHT_DEV_TYPE_SINK,
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CORESIGHT_DEV_TYPE_LINK,
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CORESIGHT_DEV_TYPE_LINKSINK,
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CORESIGHT_DEV_TYPE_SOURCE,
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};
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enum coresight_dev_subtype_sink {
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CORESIGHT_DEV_SUBTYPE_SINK_NONE,
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CORESIGHT_DEV_SUBTYPE_SINK_PORT,
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CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
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};
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enum coresight_dev_subtype_link {
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CORESIGHT_DEV_SUBTYPE_LINK_NONE,
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CORESIGHT_DEV_SUBTYPE_LINK_MERG,
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CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
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CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
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};
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enum coresight_dev_subtype_source {
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CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
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CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
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CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
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CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
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};
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struct coresight_dev_subtype {
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enum coresight_dev_subtype_sink sink_subtype;
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enum coresight_dev_subtype_link link_subtype;
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enum coresight_dev_subtype_source source_subtype;
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};
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struct coresight_platform_data {
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int id;
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const char *name;
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int nr_inports;
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const int *outports;
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const int *child_ids;
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const int *child_ports;
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int nr_outports;
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bool default_sink;
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};
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struct coresight_desc {
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enum coresight_dev_type type;
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struct coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct coresight_platform_data *pdata;
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struct device *dev;
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const struct attribute_group **groups;
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struct module *owner;
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};
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struct coresight_connection {
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int outport;
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int child_id;
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int child_port;
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struct coresight_device *child_dev;
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struct list_head link;
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};
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struct coresight_refcnt {
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int sink_refcnt;
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int *link_refcnts;
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int source_refcnt;
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};
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struct coresight_device {
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int id;
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struct coresight_connection *conns;
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int nr_conns;
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enum coresight_dev_type type;
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struct coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct device dev;
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struct coresight_refcnt refcnt;
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struct list_head dev_link;
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struct list_head path_link;
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struct module *owner;
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bool enable;
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};
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#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
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struct coresight_ops_sink {
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int (*enable)(struct coresight_device *csdev);
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void (*disable)(struct coresight_device *csdev);
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void (*abort)(struct coresight_device *csdev);
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};
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struct coresight_ops_link {
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int (*enable)(struct coresight_device *csdev, int iport, int oport);
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void (*disable)(struct coresight_device *csdev, int iport, int oport);
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};
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struct coresight_ops_source {
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int (*enable)(struct coresight_device *csdev);
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void (*disable)(struct coresight_device *csdev);
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};
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struct coresight_ops {
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const struct coresight_ops_sink *sink_ops;
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const struct coresight_ops_link *link_ops;
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const struct coresight_ops_source *source_ops;
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};
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#ifdef CONFIG_CORESIGHT
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extern struct coresight_device *
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coresight_register(struct coresight_desc *desc);
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extern void coresight_unregister(struct coresight_device *csdev);
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extern int coresight_enable(struct coresight_device *csdev);
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extern void coresight_disable(struct coresight_device *csdev);
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extern void coresight_abort(void);
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#else
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static inline struct coresight_device *
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coresight_register(struct coresight_desc *desc) { return NULL; }
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static inline void coresight_unregister(struct coresight_device *csdev) {}
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static inline int
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coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
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static inline void coresight_disable(struct coresight_device *csdev) {}
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static inline void coresight_abort(void) {}
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#endif
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#endif
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