mirror of
https://github.com/followmsi/android_kernel_google_msm.git
synced 2024-11-06 23:17:41 +00:00
22c9f71a24
Refactor the IOMMU clock control code to always require a core clock as well as an interface clock. Add support for an optional alternate core clock and update device tree bindings accordingly. Clean up the probe function to remove needless enabling / disabling of clocks. Change-Id: I4d744ffabc1e6fb123bacfda324f64408257cb25 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
308 lines
7.3 KiB
C
308 lines
7.3 KiB
C
/* Copyright (c) 2012 Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/iommu.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/atomic.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <mach/iommu_hw-v2.h>
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#include <mach/iommu.h>
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static int msm_iommu_parse_dt(struct platform_device *pdev,
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struct msm_iommu_drvdata *drvdata)
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{
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struct device_node *child;
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int ret = 0;
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u32 nsmr;
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ret = device_move(&pdev->dev, &msm_iommu_root_dev->dev, DPM_ORDER_NONE);
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if (ret)
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goto fail;
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ret = of_property_read_u32(pdev->dev.of_node, "qcom,iommu-smt-size",
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&nsmr);
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if (ret)
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goto fail;
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if (nsmr > MAX_NUM_SMR) {
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pr_err("Invalid SMT size: %d\n", nsmr);
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ret = -EINVAL;
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goto fail;
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}
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drvdata->nsmr = nsmr;
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for_each_child_of_node(pdev->dev.of_node, child) {
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drvdata->ncb++;
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if (!of_platform_device_create(child, NULL, &pdev->dev))
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pr_err("Failed to create %s device\n", child->name);
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}
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drvdata->name = dev_name(&pdev->dev);
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fail:
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return ret;
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}
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static atomic_t msm_iommu_next_id = ATOMIC_INIT(-1);
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static int __devinit msm_iommu_probe(struct platform_device *pdev)
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{
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struct msm_iommu_drvdata *drvdata;
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struct resource *r;
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int ret, needs_alt_core_clk;
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if (msm_iommu_root_dev == pdev)
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return 0;
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if (pdev->id == -1)
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pdev->id = atomic_inc_return(&msm_iommu_next_id) - 1;
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drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r)
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return -EINVAL;
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drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!drvdata->base)
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return -ENOMEM;
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drvdata->gdsc = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(drvdata->gdsc))
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return -EINVAL;
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drvdata->pclk = devm_clk_get(&pdev->dev, "iface_clk");
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if (IS_ERR(drvdata->pclk))
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return PTR_ERR(drvdata->pclk);
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drvdata->clk = devm_clk_get(&pdev->dev, "core_clk");
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if (IS_ERR(drvdata->clk))
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return PTR_ERR(drvdata->clk);
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needs_alt_core_clk = of_property_read_bool(pdev->dev.of_node,
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"qcom,needs-alt-core-clk");
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if (needs_alt_core_clk) {
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drvdata->aclk = devm_clk_get(&pdev->dev, "alt_core_clk");
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if (IS_ERR(drvdata->aclk))
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return PTR_ERR(drvdata->aclk);
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}
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if (clk_get_rate(drvdata->clk) == 0) {
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ret = clk_round_rate(drvdata->clk, 1);
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clk_set_rate(drvdata->clk, ret);
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}
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if (drvdata->aclk && clk_get_rate(drvdata->aclk) == 0) {
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ret = clk_round_rate(drvdata->aclk, 1);
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clk_set_rate(drvdata->aclk, ret);
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}
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ret = msm_iommu_parse_dt(pdev, drvdata);
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if (ret)
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return ret;
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pr_info("device %s mapped at %p, with %d ctx banks\n",
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drvdata->name, drvdata->base, drvdata->ncb);
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platform_set_drvdata(pdev, drvdata);
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return 0;
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}
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static int __devexit msm_iommu_remove(struct platform_device *pdev)
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{
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struct msm_iommu_drvdata *drv = NULL;
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drv = platform_get_drvdata(pdev);
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if (drv) {
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if (drv->clk)
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clk_put(drv->clk);
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clk_put(drv->pclk);
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platform_set_drvdata(pdev, NULL);
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}
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return 0;
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}
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static int msm_iommu_ctx_parse_dt(struct platform_device *pdev,
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struct msm_iommu_ctx_drvdata *ctx_drvdata)
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{
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struct resource *r, rp;
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int irq, ret;
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u32 nsid;
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irq = platform_get_irq(pdev, 0);
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if (irq > 0) {
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ret = request_threaded_irq(irq, NULL,
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msm_iommu_fault_handler_v2,
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IRQF_ONESHOT | IRQF_SHARED,
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"msm_iommu_nonsecure_irq", pdev);
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if (ret) {
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pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
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return ret;
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}
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r)
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return -EINVAL;
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ret = of_address_to_resource(pdev->dev.parent->of_node, 0, &rp);
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if (ret)
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return -EINVAL;
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/* Calculate the context bank number using the base addresses. The
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* first 8 pages belong to the global address space which is followed
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* by the context banks, hence subtract by 8 to get the context bank
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* number.
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*/
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ctx_drvdata->num = ((r->start - rp.start) >> CTX_SHIFT) - 8;
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if (of_property_read_string(pdev->dev.of_node, "label",
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&ctx_drvdata->name))
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ctx_drvdata->name = dev_name(&pdev->dev);
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if (!of_get_property(pdev->dev.of_node, "qcom,iommu-ctx-sids", &nsid))
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return -EINVAL;
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if (nsid >= sizeof(ctx_drvdata->sids))
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return -EINVAL;
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if (of_property_read_u32_array(pdev->dev.of_node, "qcom,iommu-ctx-sids",
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ctx_drvdata->sids,
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nsid / sizeof(*ctx_drvdata->sids))) {
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return -EINVAL;
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}
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ctx_drvdata->nsid = nsid;
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return 0;
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}
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static int __devinit msm_iommu_ctx_probe(struct platform_device *pdev)
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{
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struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
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int ret;
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if (!pdev->dev.parent)
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return -EINVAL;
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ctx_drvdata = devm_kzalloc(&pdev->dev, sizeof(*ctx_drvdata),
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GFP_KERNEL);
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if (!ctx_drvdata)
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return -ENOMEM;
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ctx_drvdata->pdev = pdev;
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INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
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platform_set_drvdata(pdev, ctx_drvdata);
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ret = msm_iommu_ctx_parse_dt(pdev, ctx_drvdata);
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if (!ret)
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dev_info(&pdev->dev, "context %s using bank %d\n",
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ctx_drvdata->name, ctx_drvdata->num);
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return ret;
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}
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static int __devexit msm_iommu_ctx_remove(struct platform_device *pdev)
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{
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct of_device_id msm_iommu_match_table[] = {
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{ .compatible = "qcom,msm-smmu-v2", },
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{}
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};
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static struct platform_driver msm_iommu_driver = {
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.driver = {
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.name = "msm_iommu_v2",
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.of_match_table = msm_iommu_match_table,
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},
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.probe = msm_iommu_probe,
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.remove = __devexit_p(msm_iommu_remove),
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};
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static struct of_device_id msm_iommu_ctx_match_table[] = {
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{ .name = "qcom,iommu-ctx", },
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{}
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};
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static struct platform_driver msm_iommu_ctx_driver = {
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.driver = {
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.name = "msm_iommu_ctx_v2",
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.of_match_table = msm_iommu_ctx_match_table,
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},
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.probe = msm_iommu_ctx_probe,
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.remove = __devexit_p(msm_iommu_ctx_remove),
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};
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static int __init msm_iommu_driver_init(void)
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{
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struct device_node *node;
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int ret;
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node = of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v2");
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if (!node)
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return -ENODEV;
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of_node_put(node);
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msm_iommu_root_dev = platform_device_register_simple(
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"msm_iommu", -1, 0, 0);
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if (!msm_iommu_root_dev) {
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pr_err("Failed to create root IOMMU device\n");
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ret = -ENODEV;
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goto error;
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}
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atomic_inc(&msm_iommu_next_id);
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ret = platform_driver_register(&msm_iommu_driver);
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if (ret != 0) {
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pr_err("Failed to register IOMMU driver\n");
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goto error;
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}
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ret = platform_driver_register(&msm_iommu_ctx_driver);
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if (ret != 0) {
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pr_err("Failed to register IOMMU context driver\n");
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goto error;
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}
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error:
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return ret;
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}
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static void __exit msm_iommu_driver_exit(void)
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{
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platform_driver_unregister(&msm_iommu_ctx_driver);
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platform_driver_unregister(&msm_iommu_driver);
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platform_device_unregister(msm_iommu_root_dev);
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}
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subsys_initcall(msm_iommu_driver_init);
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module_exit(msm_iommu_driver_exit);
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MODULE_LICENSE("GPL v2");
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