Joerg Roedel 52462d2f5a iommu/amd: Workaround for ERBT1312 ... commit d3263bc297 upstream. Work around an IOMMU hardware bug where clearing the EVT_INT or PPR_INT bit in the status register may race with the hardware trying to set it again. When not handled the bit might not be cleared and we lose all future event or ppr interrupts. Reported-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2013-06-07 12:49:48 -07:00
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amd_iommu.c	iommu/amd: Workaround for ERBT1312	2013-06-07 12:49:48 -07:00
amd_iommu_init.c	iommu/amd: Initialize device table after dma_ops	2013-03-04 06:06:37 +08:00
amd_iommu_proto.h
amd_iommu_types.h	iommu/amd: Re-enable IOMMU event log interrupt after handling.	2013-06-07 12:49:35 -07:00
amd_iommu_v2.c	iommu/amd: Add missing spin_lock initialization	2012-08-09 08:31:31 -07:00
dmar.c
intel-iommu.c	intel/iommu: force writebuffer-flush quirk on Gen 4 Chipsets	2013-02-28 06:59:03 -08:00
intr_remapping.c	irq_remap: disable IRQ remapping if any IOAPIC lacks an IOMMU	2012-10-02 10:30:38 -07:00
intr_remapping.h
iommu.c
iova.c
Kconfig
Makefile
msm_iommu.c
msm_iommu_dev.c
omap-iommu-debug.c
omap-iommu.c
omap-iovmm.c
tegra-gart.c
tegra-smmu.c	iommu/tegra: smmu: Fix deadly typo	2012-10-28 10:14:15 -07:00