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https://github.com/followmsi/android_kernel_google_msm.git
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5e6d6c1c23
DSI dcs commands and mdp pixel stream share same dsi link. Add dcs command list to serialize sending dcs command and mdp pixel stream to avoid contention which may cause dsi controller to stall. Change-Id: Ie0e687f45be479d2137eb7b56b8d32040fba2044 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Conflicts: drivers/video/msm/mdp4.h Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
944 lines
29 KiB
C
944 lines
29 KiB
C
/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDP4_H
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#define MDP4_H
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extern struct mdp_dma_data dma2_data;
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extern struct mdp_dma_data dma_s_data;
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extern struct mdp_dma_data dma_e_data;
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extern struct mdp_dma_data dma_wb_data;
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extern unsigned int mdp_hist_frame_cnt;
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extern struct completion mdp_hist_comp;
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extern boolean mdp_is_in_isr;
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extern uint32 mdp_intr_mask;
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extern spinlock_t mdp_spin_lock;
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extern struct mdp4_statistic mdp4_stat;
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extern uint32 mdp4_extn_disp;
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extern char *mmss_cc_base; /* mutimedia sub system clock control */
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extern spinlock_t dsi_clk_lock;
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extern u32 mdp_max_clk;
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#define MDP4_OVERLAYPROC0_BASE 0x10000
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#define MDP4_OVERLAYPROC1_BASE 0x18000
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#define MDP4_OVERLAYPROC2_BASE 0x88000
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#define MDP4_VIDEO_BASE 0x20000
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#define MDP4_VIDEO_OFF 0x10000
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#define MDP4_VIDEO_CSC_OFF 0x4000
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#define MDP4_RGB_BASE 0x40000
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#define MDP4_RGB_OFF 0x10000
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/* chip select controller */
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#define CS_CONTROLLER_0 0x0707ffff
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#define CS_CONTROLLER_1 0x03073f3f
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enum {
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OVERLAY_PERF_LEVEL1 = 1,
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OVERLAY_PERF_LEVEL2,
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OVERLAY_PERF_LEVEL3,
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OVERLAY_PERF_LEVEL4
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};
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typedef int (*cmd_fxn_t)(struct platform_device *pdev);
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enum { /* display */
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PRIMARY_INTF_SEL,
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SECONDARY_INTF_SEL,
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EXTERNAL_INTF_SEL
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};
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enum {
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LCDC_RGB_INTF, /* 0 */
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DTV_INTF = LCDC_RGB_INTF, /* 0 */
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MDDI_LCDC_INTF, /* 1 */
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MDDI_INTF, /* 2 */
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EBI2_INTF, /* 3 */
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TV_INTF = EBI2_INTF, /* 3 */
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DSI_VIDEO_INTF,
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DSI_CMD_INTF
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};
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enum {
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MDDI_PRIMARY_SET,
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MDDI_SECONDARY_SET,
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MDDI_EXTERNAL_SET
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};
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enum {
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EBI2_LCD0,
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EBI2_LCD1
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};
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#define MDP4_3D_NONE 0
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#define MDP4_3D_SIDE_BY_SIDE 1
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#define MDP4_3D_TOP_DOWN 2
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#define MDP4_PANEL_MDDI BIT(0)
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#define MDP4_PANEL_LCDC BIT(1)
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#define MDP4_PANEL_DTV BIT(2)
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#define MDP4_PANEL_ATV BIT(3)
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#define MDP4_PANEL_DSI_VIDEO BIT(4)
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#define MDP4_PANEL_DSI_CMD BIT(5)
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#define MDP4_PANEL_WRITEBACK BIT(6)
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enum {
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OVERLAY_MODE_NONE,
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OVERLAY_MODE_BLT
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};
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enum {
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OVERLAY_REFRESH_ON_DEMAND,
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OVERLAY_REFRESH_VSYNC,
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OVERLAY_REFRESH_VSYNC_HALF,
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OVERLAY_REFRESH_VSYNC_QUARTER
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};
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enum {
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OVERLAY_FRAMEBUF,
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OVERLAY_DIRECTOUT
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};
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/* system interrupts */
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#define INTR_OVERLAY0_DONE BIT(0)
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#define INTR_OVERLAY1_DONE BIT(1)
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#define INTR_DMA_S_DONE BIT(2)
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#define INTR_DMA_E_DONE BIT(3)
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#define INTR_DMA_P_DONE BIT(4)
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#define INTR_VG1_HISTOGRAM BIT(5)
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#define INTR_VG2_HISTOGRAM BIT(6)
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#define INTR_PRIMARY_VSYNC BIT(7)
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#define INTR_PRIMARY_INTF_UDERRUN BIT(8)
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#define INTR_EXTERNAL_VSYNC BIT(9)
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#define INTR_EXTERNAL_INTF_UDERRUN BIT(10)
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#define INTR_PRIMARY_RDPTR BIT(11) /* read pointer */
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#define INTR_DMA_P_HISTOGRAM BIT(17)
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#define INTR_DMA_S_HISTOGRAM BIT(26)
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#define INTR_OVERLAY2_DONE BIT(30)
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#ifdef CONFIG_FB_MSM_OVERLAY
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#define MDP4_ANY_INTR_MASK (INTR_DMA_P_HISTOGRAM | \
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INTR_DMA_S_HISTOGRAM | \
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INTR_VG1_HISTOGRAM | \
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INTR_VG2_HISTOGRAM)
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#else
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#define MDP4_ANY_INTR_MASK (INTR_DMA_P_DONE| \
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INTR_DMA_P_HISTOGRAM | \
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INTR_DMA_S_HISTOGRAM | \
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INTR_VG1_HISTOGRAM | \
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INTR_VG2_HISTOGRAM)
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#endif
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enum {
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OVERLAY_PIPE_VG1, /* video/graphic */
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OVERLAY_PIPE_VG2,
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OVERLAY_PIPE_RGB1,
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OVERLAY_PIPE_RGB2,
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OVERLAY_PIPE_RGB3,
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OVERLAY_PIPE_VG3,
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OVERLAY_PIPE_VG4,
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OVERLAY_PIPE_MAX
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};
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enum {
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OVERLAY_TYPE_RGB,
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OVERLAY_TYPE_VIDEO,
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OVERLAY_TYPE_BF
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};
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enum {
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MDP4_MIXER0,
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MDP4_MIXER1,
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MDP4_MIXER2,
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MDP4_MIXER_MAX
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};
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enum {
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OVERLAY_PLANE_INTERLEAVED,
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OVERLAY_PLANE_PLANAR,
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OVERLAY_PLANE_PSEUDO_PLANAR
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};
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enum {
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MDP4_MIXER_STAGE_UNUNSED, /* pipe not used */
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MDP4_MIXER_STAGE_BASE,
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MDP4_MIXER_STAGE0, /* zorder 0 */
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MDP4_MIXER_STAGE1, /* zorder 1 */
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MDP4_MIXER_STAGE2, /* zorder 2 */
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MDP4_MIXER_STAGE3, /* zorder 3 */
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MDP4_MIXER_STAGE_MAX
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};
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enum {
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MDP4_FRAME_FORMAT_LINEAR,
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MDP4_FRAME_FORMAT_ARGB_TILE,
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MDP4_FRAME_FORMAT_VIDEO_SUPERTILE
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};
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enum {
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MDP4_CHROMA_RGB,
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MDP4_CHROMA_H2V1,
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MDP4_CHROMA_H1V2,
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MDP4_CHROMA_420
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};
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#define MDP4_BLEND_BG_TRANSP_EN BIT(9)
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#define MDP4_BLEND_FG_TRANSP_EN BIT(8)
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#define MDP4_BLEND_BG_MOD_ALPHA BIT(7)
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#define MDP4_BLEND_BG_INV_ALPHA BIT(6)
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#define MDP4_BLEND_BG_ALPHA_FG_CONST (0 << 4)
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#define MDP4_BLEND_BG_ALPHA_BG_CONST (1 << 4)
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#define MDP4_BLEND_BG_ALPHA_FG_PIXEL (2 << 4)
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#define MDP4_BLEND_BG_ALPHA_BG_PIXEL (3 << 4)
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#define MDP4_BLEND_FG_MOD_ALPHA BIT(3)
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#define MDP4_BLEND_FG_INV_ALPHA BIT(2)
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#define MDP4_BLEND_FG_ALPHA_FG_CONST (0 << 0)
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#define MDP4_BLEND_FG_ALPHA_BG_CONST (1 << 0)
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#define MDP4_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
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#define MDP4_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
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#define MDP4_FORMAT_SOLID_FILL BIT(22)
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#define MDP4_FORMAT_UNPACK_ALIGN_MSB BIT(18)
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#define MDP4_FORMAT_UNPACK_TIGHT BIT(17)
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#define MDP4_FORMAT_90_ROTATED BIT(12)
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#define MDP4_FORMAT_ALPHA_ENABLE BIT(8)
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#define MDP4_OP_DEINT_ODD_REF BIT(19)
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#define MDP4_OP_DEINT_EN BIT(18)
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#define MDP4_OP_IGC_LUT_EN BIT(16)
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#define MDP4_OP_DITHER_EN BIT(15)
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#define MDP4_OP_FLIP_UD BIT(14)
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#define MDP4_OP_FLIP_LR BIT(13)
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#define MDP4_OP_CSC_EN BIT(11)
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#define MDP4_OP_DST_DATA_YCBCR BIT(10)
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#define MDP4_OP_SRC_DATA_YCBCR BIT(9)
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#define MDP4_OP_SCALEY_FIR (0 << 4)
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#define MDP4_OP_SCALEY_MN_PHASE (1 << 4)
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#define MDP4_OP_SCALEY_PIXEL_RPT (2 << 4)
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#define MDP4_OP_SCALEX_FIR (0 << 2)
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#define MDP4_OP_SCALEX_MN_PHASE (1 << 2)
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#define MDP4_OP_SCALEX_PIXEL_RPT (2 << 2)
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#define MDP4_OP_SCALE_RGB_ENHANCED (1 << 4)
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#define MDP4_OP_SCALE_RGB_PIXEL_RPT (0 << 3)
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#define MDP4_OP_SCALE_RGB_BILINEAR (1 << 3)
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#define MDP4_OP_SCALE_ALPHA_PIXEL_RPT (0 << 2)
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#define MDP4_OP_SCALE_ALPHA_BILINEAR (1 << 2)
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#define MDP4_OP_SCALEY_EN BIT(1)
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#define MDP4_OP_SCALEX_EN BIT(0)
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#define MDP4_REV40_UP_SCALING_MAX (8)
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#define MDP4_REV41_OR_LATER_UP_SCALING_MAX (20)
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#define MDP4_PIPE_PER_MIXER 2
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#define MDP4_MAX_PLANE 4
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#define VSYNC_PERIOD 16
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struct mdp4_hsic_regs {
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int32_t params[NUM_HSIC_PARAM];
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int32_t conv_matrix[3][3];
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int32_t pre_limit[6];
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int32_t post_limit[6];
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int32_t pre_bias[3];
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int32_t post_bias[3];
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int32_t dirty;
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};
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struct mdp4_iommu_pipe_info {
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struct ion_handle *ihdl[MDP4_MAX_PLANE];
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struct ion_handle *prev_ihdl[MDP4_MAX_PLANE];
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u8 mark_unmap;
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};
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#define IOMMU_FREE_LIST_MAX 32
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struct iommu_free_list {
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int total;
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int fndx;
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struct ion_handle *ihdl[IOMMU_FREE_LIST_MAX];
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};
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struct blend_cfg {
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u32 op;
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u32 bg_alpha;
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u32 fg_alpha;
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u32 co3_sel;
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u32 transp_low0;
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u32 transp_low1;
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u32 transp_high0;
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u32 transp_high1;
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int solidfill;
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struct mdp4_overlay_pipe *solidfill_pipe;
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};
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struct mdp4_overlay_pipe {
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uint32 pipe_used;
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uint32 pipe_type; /* rgb, video/graphic */
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uint32 pipe_num;
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uint32 pipe_ndx;
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uint32 pipe_share;
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uint32 mixer_num; /* which mixer used */
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uint32 mixer_stage; /* which stage of mixer used */
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uint32 src_format;
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uint32 src_width; /* source img width */
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uint32 src_height; /* source img height */
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uint32 is_3d;
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uint32 src_width_3d; /* source img width */
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uint32 src_height_3d; /* source img height */
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uint32 src_w; /* roi */
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uint32 src_h; /* roi */
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uint32 src_x; /* roi */
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uint32 src_y; /* roi */
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uint32 dst_w; /* roi */
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uint32 dst_h; /* roi */
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uint32 dst_x; /* roi */
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uint32 dst_y; /* roi */
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uint32 flags;
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uint32 op_mode;
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uint32 transp;
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uint32 blend_op;
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uint32 phasex_step;
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uint32 phasey_step;
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uint32 alpha;
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uint32 is_fg; /* control alpha & color key */
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uint32 srcp0_addr; /* interleave, luma */
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uint32 srcp0_ystride;
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uint32 srcp1_addr; /* pseudoplanar, chroma plane */
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uint32 srcp1_ystride;
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uint32 srcp2_addr; /* planar color 2*/
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uint32 srcp2_ystride;
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uint32 srcp3_addr; /* alpha/color 3 */
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uint32 srcp3_ystride;
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uint32 fetch_plane;
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uint32 frame_format; /* video */
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uint32 chroma_site; /* video */
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uint32 chroma_sample; /* video */
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uint32 solid_fill;
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uint32 vc1_reduce; /* video */
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uint32 unpack_align_msb;/* 0 to LSB, 1 to MSB */
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uint32 unpack_tight;/* 0 for loose, 1 for tight */
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uint32 unpack_count;/* 0 = 1 component, 1 = 2 component ... */
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uint32 rotated_90; /* has been rotated 90 degree */
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uint32 bpp; /* byte per pixel */
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uint32 alpha_enable;/* source has alpha */
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/*
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* number of bits for source component,
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* 0 = 1 bit, 1 = 2 bits, 2 = 6 bits, 3 = 8 bits
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*/
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uint32 a_bit; /* component 3, alpha */
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uint32 r_bit; /* component 2, R_Cr */
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uint32 b_bit; /* component 1, B_Cb */
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uint32 g_bit; /* component 0, G_lumz */
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/*
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* unpack pattern
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* A = C3, R = C2, B = C1, G = C0
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*/
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uint32 element3; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
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uint32 element2; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
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uint32 element1; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
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uint32 element0; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
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ulong ov_blt_addr; /* blt mode addr */
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ulong dma_blt_addr; /* blt mode addr */
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ulong blt_base;
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ulong blt_offset;
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uint32 blt_cnt;
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uint32 blt_changed;
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uint32 ov_cnt;
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uint32 dmap_cnt;
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uint32 dmae_cnt;
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uint32 blt_end;
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uint32 blt_ov_koff;
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uint32 blt_ov_done;
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uint32 blt_dmap_koff;
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uint32 blt_dmap_done;
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uint32 req_clk;
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uint32 req_bw;
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uint32 luma_align_size;
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struct mdp_overlay_pp_params pp_cfg;
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struct mdp_overlay req_data;
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struct completion comp;
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struct completion dmas_comp;
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struct mdp4_iommu_pipe_info iommu;
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};
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struct mdp4_statistic {
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ulong intr_tot;
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ulong intr_dma_p;
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ulong intr_dma_s;
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ulong intr_dma_e;
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ulong intr_overlay0;
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ulong intr_overlay1;
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ulong intr_overlay2;
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ulong intr_vsync_p; /* Primary interface */
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ulong intr_underrun_p; /* Primary interface */
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ulong intr_vsync_e; /* external interface */
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ulong intr_underrun_e; /* external interface */
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ulong intr_histogram;
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ulong intr_rdptr;
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ulong dsi_mdp_start;
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ulong dsi_clk_on;
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ulong dsi_clk_off;
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ulong intr_dsi;
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ulong intr_dsi_mdp;
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ulong intr_dsi_cmd;
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ulong intr_dsi_err;
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ulong kickoff_ov0;
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ulong kickoff_ov1;
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ulong kickoff_dmap;
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ulong kickoff_dmae;
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ulong kickoff_dmas;
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ulong blt_dsi_cmd; /* blt */
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ulong blt_dsi_video; /* blt */
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ulong blt_lcdc; /* blt */
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ulong blt_dtv; /* blt */
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ulong blt_mddi; /* blt */
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ulong overlay_set[MDP4_MIXER_MAX];
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ulong overlay_unset[MDP4_MIXER_MAX];
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ulong overlay_play[MDP4_MIXER_MAX];
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ulong overlay_commit[MDP4_MIXER_MAX];
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ulong pipe[OVERLAY_PIPE_MAX];
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ulong wait4vsync0;
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ulong wait4vsync1;
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ulong iommu_map;
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ulong iommu_unmap;
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ulong iommu_drop;
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ulong dsi_clkoff;
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ulong err_mixer;
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ulong err_zorder;
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ulong err_size;
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ulong err_scale;
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ulong err_format;
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ulong err_stage;
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ulong err_play;
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ulong err_underflow;
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};
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struct vsync_update {
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int update_cnt; /* pipes to be updated */
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struct completion vsync_comp;
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struct mdp4_overlay_pipe plist[OVERLAY_PIPE_MAX];
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};
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struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx);
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void mdp4_sw_reset(unsigned long bits);
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void mdp4_display_intf_sel(int output, unsigned long intf);
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void mdp4_overlay_cfg(int layer, int blt_mode, int refresh, int direct_out);
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void mdp4_ebi2_lcd_setup(int lcd, unsigned long base, int ystride);
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void mdp4_mddi_setup(int which, unsigned long id);
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unsigned long mdp4_display_status(void);
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void mdp4_enable_clk_irq(void);
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void mdp4_disable_clk_irq(void);
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void mdp4_dma_p_update(struct msm_fb_data_type *mfd);
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void mdp4_dma_s_update(struct msm_fb_data_type *mfd);
|
|
void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state,
|
|
boolean isr);
|
|
void mdp4_pipe_kickoff(uint32 pipe, struct msm_fb_data_type *mfd);
|
|
int mdp4_lcdc_on(struct platform_device *pdev);
|
|
int mdp4_lcdc_off(struct platform_device *pdev);
|
|
void mdp4_lcdc_update(struct msm_fb_data_type *mfd);
|
|
void mdp4_intr_clear_set(ulong clear, ulong set);
|
|
void mdp4_dma_p_cfg(void);
|
|
unsigned is_mdp4_hw_reset(void);
|
|
void mdp4_overlay_cfg_init(void);
|
|
void mdp4_hw_init(void);
|
|
void mdp4_isr_read(int);
|
|
void mdp4_clear_lcdc(void);
|
|
void mdp4_mixer_blend_init(int mixer_num);
|
|
void mdp4_vg_qseed_init(int vg_num);
|
|
void mdp4_vg_csc_setup(int vp_num);
|
|
void mdp4_mixer_csc_setup(uint32 mixer);
|
|
void mdp4_dmap_csc_setup(void);
|
|
void mdp4_vg_csc_update(struct mdp_csc *p);
|
|
irqreturn_t mdp4_isr(int irq, void *ptr);
|
|
void mdp4_overlay_format_to_pipe(uint32 format, struct mdp4_overlay_pipe *pipe);
|
|
uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe);
|
|
uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe);
|
|
uint32 mdp4_overlay_op_mode(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_lcdc_base_swap(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd);
|
|
|
|
|
|
#ifdef CONFIG_FB_MSM_DTV
|
|
void mdp4_overlay_dtv_start(void);
|
|
void mdp4_overlay_dtv_ov_done_push(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_overlay_dtv_set(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_overlay_dtv_unset(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dmae_done_dtv(void);
|
|
void mdp4_dtv_wait4vsync(int cndx, long long *vtime);
|
|
void mdp4_dtv_vsync_ctrl(int cndx, int enable);
|
|
void mdp4_dtv_base_swap(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
#else
|
|
static inline void mdp4_overlay_dtv_start(void)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_overlay_dtv_ov_done_push(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline int mdp4_overlay_dtv_set(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int mdp4_overlay_dtv_unset(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void mdp4_dmae_done_dtv(void)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_dtv_wait4vsync(int cndx, long long *vtime)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_dtv_vsync_ctrl(int cndx, long long *vtime)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_dtv_overlay_blt_start(struct msm_fb_data_type *mfd)
|
|
{
|
|
return;
|
|
}
|
|
static inline void mdp4_dtv_overlay_blt_stop(struct msm_fb_data_type *mfd)
|
|
{
|
|
return;
|
|
}
|
|
static inline void mdp4_dtv_base_swap(struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
#endif /* CONFIG_FB_MSM_DTV */
|
|
|
|
void mdp4_dtv_set_black_screen(void);
|
|
|
|
int mdp4_overlay_dtv_set(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_overlay_dtv_unset(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dtv_overlay(struct msm_fb_data_type *mfd);
|
|
int mdp4_dtv_on(struct platform_device *pdev);
|
|
int mdp4_dtv_off(struct platform_device *pdev);
|
|
void mdp4_atv_overlay(struct msm_fb_data_type *mfd);
|
|
int mdp4_atv_on(struct platform_device *pdev);
|
|
int mdp4_atv_off(struct platform_device *pdev);
|
|
void mdp4_dsi_video_fxn_register(cmd_fxn_t fxn);
|
|
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd);
|
|
void mdp4_lcdc_vsync_ctrl(int cndx, int enable);
|
|
void mdp4_overlay0_done_dsi_video(int cndx);
|
|
void mdp4_overlay0_done_dsi_cmd(int cndx);
|
|
void mdp4_primary_rdptr(void);
|
|
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd);
|
|
int mdp4_overlay_commit(struct fb_info *info, int mixer);
|
|
int mdp4_dsi_video_pipe_commit(int cndx, int wait);
|
|
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait);
|
|
int mdp4_lcdc_pipe_commit(int cndx, int wait);
|
|
int mdp4_dtv_pipe_commit(int cndx, int wait);
|
|
int mdp4_dsi_cmd_update_cnt(int cndx);
|
|
void mdp4_dsi_rdptr_init(int cndx);
|
|
void mdp4_dsi_vsync_init(int cndx);
|
|
void mdp4_lcdc_vsync_init(int cndx);
|
|
void mdp4_dtv_vsync_init(int cndx);
|
|
void mdp4_overlay_dsi_state_set(int state);
|
|
int mdp4_overlay_dsi_state_get(void);
|
|
void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all);
|
|
void mdp4_mixer_blend_setup(int mixer);
|
|
struct mdp4_overlay_pipe *mdp4_overlay_stage_pipe(int mixer, int stage);
|
|
void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe, int commit);
|
|
void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe, int commit);
|
|
void mdp4_mixer_pipe_cleanup(int mixer);
|
|
int mdp4_mixer_stage_can_run(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_mddi_overlay(struct msm_fb_data_type *mfd);
|
|
int mdp4_overlay_format2type(uint32 format);
|
|
int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req);
|
|
int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req);
|
|
int mdp4_overlay_wait4vsync(struct fb_info *info, long long *vtime);
|
|
int mdp4_overlay_vsync_ctrl(struct fb_info *info, int enable);
|
|
int mdp4_overlay_unset(struct fb_info *info, int ndx);
|
|
int mdp4_overlay_unset_mixer(int mixer);
|
|
int mdp4_overlay_play_wait(struct fb_info *info,
|
|
struct msmfb_overlay_data *req);
|
|
int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req);
|
|
int mdp4_overlay_commit(struct fb_info *info, int mixer);
|
|
struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(int ptype, int mixer);
|
|
void mdp4_overlay_dma_commit(int mixer);
|
|
void mdp4_overlay_vsync_commit(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_mixer_stage_commit(int mixer);
|
|
void mdp4_dsi_cmd_do_update(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_lcdc_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dtv_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc);
|
|
void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_dmae_cfg(struct msm_fb_data_type *mfd, int atv);
|
|
void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_overlay_pipe_staged(int mixer);
|
|
void mdp4_lcdc_primary_vsyn(void);
|
|
void mdp4_overlay0_done_lcdc(int cndx);
|
|
void mdp4_overlay0_done_mddi(struct mdp_dma_data *dma);
|
|
void mdp4_dma_p_done_mddi(struct mdp_dma_data *dma);
|
|
void mdp4_dmap_done_dsi_cmd(int cndx);
|
|
void mdp4_dmap_done_dsi_video(int cndx);
|
|
void mdp4_dmap_done_lcdc(int cndx);
|
|
void mdp4_overlay1_done_dtv(void);
|
|
void mdp4_overlay1_done_atv(void);
|
|
void mdp4_primary_vsync_lcdc(void);
|
|
void mdp4_external_vsync_dtv(void);
|
|
void mdp4_lcdc_wait4vsync(int cndx, long long *vtime);
|
|
void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_mddi_overlay_dmas_restore(void);
|
|
|
|
#ifndef CONFIG_FB_MSM_MIPI_DSI
|
|
void mdp4_mddi_dma_busy_wait(struct msm_fb_data_type *mfd);
|
|
void mdp4_mddi_overlay_restore(void);
|
|
#else
|
|
static inline void mdp4_mddi_kickoff_video(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_mddi_dma_busy_wait(struct msm_fb_data_type *mfd)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_mddi_blt_dmap_busy_wait(struct msm_fb_data_type *mfd)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_mddi_overlay_restore(void)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_mddi_overlay_blt_start(struct msm_fb_data_type *mfd)
|
|
{
|
|
/*empty*/
|
|
}
|
|
static inline void mdp4_mddi_overlay_blt_stop(struct msm_fb_data_type *mfd)
|
|
{
|
|
/*empty*/
|
|
}
|
|
static inline void mdp4_mddi_overlay_blt_offset(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_mddi_overlay_blt(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req)
|
|
{
|
|
/* empty*/
|
|
}
|
|
#endif
|
|
|
|
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_rgb_igc_lut_setup(int num);
|
|
void mdp4_vg_igc_lut_setup(int num);
|
|
void mdp4_mixer_gc_lut_setup(int mixer_num);
|
|
void mdp4_fetch_cfg(uint32 clk);
|
|
uint32 mdp4_rgb_igc_lut_cvt(uint32 ndx);
|
|
void mdp4_vg_qseed_init(int);
|
|
int mdp4_overlay_blt(struct fb_info *info, struct msmfb_overlay_blt *req);
|
|
|
|
#ifdef CONFIG_FB_MSM_MIPI_DSI
|
|
void mdp4_dsi_cmd_blt_start(struct msm_fb_data_type *mfd);
|
|
void mdp4_dsi_cmd_blt_stop(struct msm_fb_data_type *mfd);
|
|
void mdp4_dsi_video_blt_start(struct msm_fb_data_type *mfd);
|
|
void mdp4_dsi_video_blt_stop(struct msm_fb_data_type *mfd);
|
|
void mdp4_dsi_cmd_overlay_blt(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
|
|
void mdp4_dsi_video_overlay_blt(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
void mdp4_dsi_video_base_swap(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
|
|
#ifdef CONFIG_FB_MSM_MDP40
|
|
static inline void mdp3_dsi_cmd_dma_busy_wait(struct msm_fb_data_type *mfd)
|
|
{
|
|
/* empty */
|
|
}
|
|
#endif
|
|
#else /* CONFIG_FB_MSM_MIPI_DSI */
|
|
int mdp4_mddi_overlay_blt_offset(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
void mdp4_mddi_overlay_blt(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
int mdp4_mddi_overlay_blt_start(struct msm_fb_data_type *mfd);
|
|
int mdp4_mddi_overlay_blt_stop(struct msm_fb_data_type *mfd);
|
|
void mdp4_mddi_blt_dmap_busy_wait(struct msm_fb_data_type *mfd);
|
|
static inline int mdp4_dsi_overlay_blt_start(struct msm_fb_data_type *mfd)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline int mdp4_dsi_overlay_blt_stop(struct msm_fb_data_type *mfd)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void mdp4_dsi_video_blt_start(struct msm_fb_data_type *mfd)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_video_blt_stop(struct msm_fb_data_type *mfd)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_overlay_blt(
|
|
struct msm_fb_data_type *mfd, struct msmfb_overlay_blt *req)
|
|
{
|
|
}
|
|
static inline int mdp4_dsi_overlay_blt_offset(
|
|
struct msm_fb_data_type *mfd, struct msmfb_overlay_blt *req)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void mdp4_dsi_video_overlay_blt(
|
|
struct msm_fb_data_type *mfd, struct msmfb_overlay_blt *req)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_cmd_overlay_blt(
|
|
struct msm_fb_data_type *mfd, struct msmfb_overlay_blt *req)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_video_base_swap(int cndx,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_dsi_cmd_blt_start(struct msm_fb_data_type *mfd)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_cmd_blt_stop(struct msm_fb_data_type *mfd)
|
|
{
|
|
}
|
|
#endif /* CONFIG_FB_MSM_MIPI_DSI */
|
|
|
|
void mdp4_lcdc_overlay_blt(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
int mdp4_lcdc_overlay_blt_offset(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_blt *req);
|
|
void mdp4_lcdc_overlay_blt_start(struct msm_fb_data_type *mfd);
|
|
void mdp4_lcdc_overlay_blt_stop(struct msm_fb_data_type *mfd);
|
|
void mdp4_dtv_overlay_blt_start(struct msm_fb_data_type *mfd);
|
|
void mdp4_dtv_overlay_blt_stop(struct msm_fb_data_type *mfd);
|
|
void mdp4_overlay_panel_mode(int mixer_num, uint32 mode);
|
|
void mdp4_overlay_panel_mode_unset(int mixer_num, uint32 mode);
|
|
int mdp4_overlay_mixer_play(int mixer_num);
|
|
uint32 mdp4_overlay_panel_list(void);
|
|
void mdp4_lcdc_overlay_kickoff(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
|
|
void mdp4_mddi_kickoff_video(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
|
|
void mdp4_mddi_read_ptr_intr(void);
|
|
|
|
void mdp4_dsi_cmd_dma_busy_check(void);
|
|
|
|
|
|
|
|
#ifdef CONFIG_FB_MSM_MIPI_DSI
|
|
void mdp_dsi_cmd_overlay_suspend(struct msm_fb_data_type *mfd);
|
|
int mdp4_dsi_cmd_on(struct platform_device *pdev);
|
|
int mdp4_dsi_cmd_off(struct platform_device *pdev);
|
|
int mdp4_dsi_video_off(struct platform_device *pdev);
|
|
int mdp4_dsi_video_on(struct platform_device *pdev);
|
|
void mdp4_primary_vsync_dsi_video(void);
|
|
void mdp4_dsi_cmd_base_swap(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dsi_cmd_wait4vsync(int cndx, long long *vtime);
|
|
void mdp4_dsi_video_wait4vsync(int cndx, long long *vtime);
|
|
void mdp4_dsi_cmd_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dsi_video_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dsi_cmd_vsync_ctrl(int cndx, int enable);
|
|
void mdp4_dsi_video_vsync_ctrl(int cndx, int enable);
|
|
#ifdef CONFIG_FB_MSM_MDP303
|
|
static inline void mdp4_dsi_cmd_del_timer(void)
|
|
{
|
|
/* empty */
|
|
}
|
|
#else /* CONFIG_FB_MSM_MIPI_DSI */
|
|
void mdp4_dsi_cmd_del_timer(void);
|
|
#endif
|
|
#else /* CONFIG_FB_MSM_MIPI_DSI */
|
|
|
|
static inline int mdp4_dsi_cmd_on(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int mdp4_dsi_cmd_off(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int mdp4_dsi_video_on(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int mdp4_dsi_video_off(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void mdp4_primary_vsync_dsi_video(void)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_cmd_base_swap(int cndx,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_cmd_wait4vsync(int cndx, long long *vtime)
|
|
{
|
|
}
|
|
static inline void mdp4_dsi_video_wait4vsync(int cndx, long long *vtime)
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|
{
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|
}
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static inline void mdp4_dsi_cmd_pipe_queue(int cndx,
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struct mdp4_overlay_pipe *pipe)
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|
{
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|
}
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static inline void mdp4_dsi_video_pipe_queue(int cndx,
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|
struct mdp4_overlay_pipe *pipe)
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|
{
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|
}
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static inline void mdp4_dsi_cmd_vsync_ctrl(int cndx, int enable)
|
|
{
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|
}
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|
static inline void mdp4_dsi_video_vsync_ctrl(int cndx, int enable)
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|
{
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|
}
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|
|
|
static inline void mdp4_overlay_dsi_video_start(void)
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|
{
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|
/* empty */
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|
}
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#ifdef CONFIG_FB_MSM_MDP40
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|
static inline void mdp_dsi_cmd_overlay_suspend(struct msm_fb_data_type *mfd)
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|
{
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|
/* empty */
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|
}
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|
#endif
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|
#endif /* CONFIG_FB_MSM_MIPI_DSI */
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|
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void mdp4_dsi_cmd_kickoff_ui(struct msm_fb_data_type *mfd,
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|
struct mdp4_overlay_pipe *pipe);
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|
void mdp4_dsi_cmd_kickoff_video(struct msm_fb_data_type *mfd,
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|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_overlay_panel_3d(int mixer_num, uint32 panel_3d);
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|
int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req);
|
|
void mdp4_dsi_cmd_3d_sbys(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_3d *r3d);
|
|
void mdp4_dsi_video_3d_sbys(struct msm_fb_data_type *mfd,
|
|
struct msmfb_overlay_3d *r3d);
|
|
|
|
int mdp4_mixer_info(int mixer_num, struct mdp_mixer_info *info);
|
|
|
|
void mdp_dmap_vsync_set(int enable);
|
|
int mdp_dmap_vsync_get(void);
|
|
void mdp_hw_cursor_done(void);
|
|
void mdp_hw_cursor_init(void);
|
|
int mdp4_mddi_overlay_cursor(struct fb_info *info, struct fb_cursor *cursor);
|
|
int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req);
|
|
void mdp4_overlay_resource_release(void);
|
|
uint32_t mdp4_ss_table_value(int8_t param, int8_t index);
|
|
void mdp4_overlay_borderfill_stage_down(struct mdp4_overlay_pipe *pipe);
|
|
|
|
#ifdef CONFIG_FB_MSM_MDP303
|
|
static inline int mdp4_overlay_borderfill_supported(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#else
|
|
int mdp4_overlay_borderfill_supported(void);
|
|
#endif
|
|
|
|
int mdp4_overlay_writeback_on(struct platform_device *pdev);
|
|
int mdp4_overlay_writeback_off(struct platform_device *pdev);
|
|
void mdp4_writeback_overlay(struct msm_fb_data_type *mfd);
|
|
void mdp4_overlay1_done_writeback(struct mdp_dma_data *dma);
|
|
|
|
int mdp4_writeback_start(struct fb_info *info);
|
|
int mdp4_writeback_stop(struct fb_info *info);
|
|
int mdp4_writeback_dequeue_buffer(struct fb_info *info,
|
|
struct msmfb_data *data);
|
|
int mdp4_writeback_queue_buffer(struct fb_info *info,
|
|
struct msmfb_data *data);
|
|
void mdp4_writeback_dma_stop(struct msm_fb_data_type *mfd);
|
|
int mdp4_writeback_init(struct fb_info *info);
|
|
int mdp4_writeback_terminate(struct fb_info *info);
|
|
|
|
uint32_t mdp_block2base(uint32_t block);
|
|
int mdp_hist_lut_config(struct mdp_hist_lut_data *data);
|
|
|
|
void mdp4_hsic_update(struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_csc_config(struct mdp_csc_cfg_data *config);
|
|
void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base);
|
|
int mdp4_csc_enable(struct mdp_csc_cfg_data *config);
|
|
int mdp4_pcc_cfg(struct mdp_pcc_cfg_data *cfg_ptr);
|
|
int mdp4_argc_cfg(struct mdp_pgc_lut_data *pgc_ptr);
|
|
int mdp4_qseed_cfg(struct mdp_qseed_cfg_data *cfg);
|
|
int mdp4_qseed_access_cfg(struct mdp_qseed_cfg *cfg, uint32_t base);
|
|
u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num);
|
|
void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num);
|
|
void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num);
|
|
|
|
int mdp4_igc_lut_config(struct mdp_igc_lut_data *cfg);
|
|
void mdp4_overlay_iommu_pipe_free(int ndx, int all);
|
|
void mdp4_overlay_iommu_free_list(int mixer, struct ion_handle *ihdl);
|
|
void mdp4_overlay_iommu_unmap_freelist(int mixer);
|
|
void mdp4_overlay_iommu_vsync_cnt(void);
|
|
void mdp4_iommu_unmap(struct mdp4_overlay_pipe *pipe);
|
|
void mdp4_iommu_attach(void);
|
|
int mdp4_v4l2_overlay_set(struct fb_info *info, struct mdp_overlay *req,
|
|
struct mdp4_overlay_pipe **ppipe);
|
|
void mdp4_v4l2_overlay_clear(struct mdp4_overlay_pipe *pipe);
|
|
int mdp4_v4l2_overlay_play(struct fb_info *info, struct mdp4_overlay_pipe *pipe,
|
|
unsigned long srcp0_addr, unsigned long srcp1_addr,
|
|
unsigned long srcp2_addr);
|
|
int mdp4_overlay_mdp_pipe_req(struct mdp4_overlay_pipe *pipe,
|
|
struct msm_fb_data_type *mfd);
|
|
int mdp4_overlay_mdp_perf_req(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *plist);
|
|
void mdp4_overlay_mdp_perf_upd(struct msm_fb_data_type *mfd, int flag);
|
|
|
|
#ifndef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
|
|
static inline void mdp4_writeback_dma_busy_wait(struct msm_fb_data_type *mfd)
|
|
{
|
|
/* empty */
|
|
}
|
|
static inline void mdp4_writeback_kickoff_video(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe)
|
|
{
|
|
/* empty */
|
|
}
|
|
#else
|
|
void mdp4_writeback_dma_busy_wait(struct msm_fb_data_type *mfd);
|
|
void mdp4_writeback_kickoff_video(struct msm_fb_data_type *mfd,
|
|
struct mdp4_overlay_pipe *pipe);
|
|
#endif
|
|
|
|
#endif /* MDP_H */
|