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eb55aa3da8
Add support for 1.7 GHz and 2.0 GHz parts and their corresponding L2 and memory bandwidth votes. Support selecting different PVS tables based upon EFUSE speed bin across all krait targets. Signed-off-by: Patrick Daly <pdaly@codeaurora.org> Conflicts: arch/arm/mach-msm/acpuclock-8064.c Change-Id: I560371c3c5476f72444a8f2a88b9c441f3451ae1 Signed-off-by: Neha Pandey <nehap@codeaurora.org>
214 lines
7.9 KiB
C
214 lines
7.9 KiB
C
/*
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* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <mach/rpm-regulator-smd.h>
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#include <mach/msm_bus_board.h>
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#include <mach/msm_bus.h>
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#include <mach/socinfo.h>
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#include "acpuclock.h"
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#include "acpuclock-krait.h"
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/* Corner type vreg VDD values */
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#define LVL_NONE RPM_REGULATOR_CORNER_NONE
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#define LVL_LOW RPM_REGULATOR_CORNER_SVS_SOC
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#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
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#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
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static struct hfpll_data hfpll_data __initdata = {
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.mode_offset = 0x00,
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.l_offset = 0x04,
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.m_offset = 0x08,
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.n_offset = 0x0C,
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.has_user_reg = true,
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.user_offset = 0x10,
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.config_offset = 0x14,
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/* TODO: Verify magic numbers when final values are available. */
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.user_val = 0x8,
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.config_val = 0x04D0405D,
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.low_vco_l_max = 65,
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.low_vdd_l_max = 52,
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.nom_vdd_l_max = 104,
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.vdd[HFPLL_VDD_NONE] = LVL_NONE,
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.vdd[HFPLL_VDD_LOW] = LVL_LOW,
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.vdd[HFPLL_VDD_NOM] = LVL_NOM,
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.vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
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};
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static struct scalable scalable[] __initdata = {
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[CPU0] = {
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.hfpll_phys_base = 0xF908A000,
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.l2cpmr_iaddr = 0x4501,
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.sec_clk_sel = 2,
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.vreg[VREG_CORE] = { "krait0", 1050000 },
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.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
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.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
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.vreg[VREG_HFPLL_A] = { "krait0_hfpll_a", 2150000 },
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.vreg[VREG_HFPLL_B] = { "krait0_hfpll_b", 1800000 },
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},
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[CPU1] = {
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.hfpll_phys_base = 0xF909A000,
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.l2cpmr_iaddr = 0x5501,
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.sec_clk_sel = 2,
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.vreg[VREG_CORE] = { "krait1", 1050000 },
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.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
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.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
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.vreg[VREG_HFPLL_A] = { "krait1_hfpll_a", 2150000 },
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.vreg[VREG_HFPLL_B] = { "krait1_hfpll_b", 1800000 },
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},
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[CPU2] = {
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.hfpll_phys_base = 0xF90AA000,
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.l2cpmr_iaddr = 0x6501,
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.sec_clk_sel = 2,
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.vreg[VREG_CORE] = { "krait2", 1050000 },
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.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
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.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
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.vreg[VREG_HFPLL_A] = { "krait2_hfpll_a", 2150000 },
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.vreg[VREG_HFPLL_B] = { "krait2_hfpll_b", 1800000 },
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},
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[CPU3] = {
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.hfpll_phys_base = 0xF90BA000,
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.l2cpmr_iaddr = 0x7501,
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.sec_clk_sel = 2,
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.vreg[VREG_CORE] = { "krait3", 1050000 },
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.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
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.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
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.vreg[VREG_HFPLL_A] = { "krait3_hfpll_a", 2150000 },
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.vreg[VREG_HFPLL_B] = { "krait3_hfpll_b", 1800000 },
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},
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[L2] = {
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.hfpll_phys_base = 0xF9016000,
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.l2cpmr_iaddr = 0x0500,
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.sec_clk_sel = 2,
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.vreg[VREG_HFPLL_A] = { "l2_hfpll_a", 2150000 },
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.vreg[VREG_HFPLL_B] = { "l2_hfpll_b", 1800000 },
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},
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};
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static struct msm_bus_paths bw_level_tbl[] __initdata = {
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[0] = BW_MBPS(552), /* At least 69 MHz on bus. */
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[1] = BW_MBPS(1112), /* At least 139 MHz on bus. */
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[2] = BW_MBPS(2224), /* At least 278 MHz on bus. */
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[3] = BW_MBPS(4448), /* At least 556 MHz on bus. */
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};
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static struct msm_bus_scale_pdata bus_scale_data __initdata = {
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.usecase = bw_level_tbl,
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.num_usecases = ARRAY_SIZE(bw_level_tbl),
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.active_only = 1,
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.name = "acpuclk-8974",
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};
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static struct l2_level l2_freq_tbl[] __initdata = {
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[0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
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[1] = { { 384000, HFPLL, 2, 40 }, LVL_NOM, 950000, 1 },
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[2] = { { 460800, HFPLL, 2, 48 }, LVL_NOM, 950000, 1 },
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[3] = { { 537600, HFPLL, 1, 28 }, LVL_NOM, 950000, 2 },
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[4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 2 },
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[5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 2 },
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[6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 2 },
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[7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 2 },
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[8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 2 },
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[9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 2 },
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[10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 3 },
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[11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 3 },
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[12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 3 },
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[13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 3 },
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[14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 3 },
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[15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 3 },
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[16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 3 },
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[17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 3 },
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[18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 3 },
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[19] = { { 1728000, HFPLL, 1, 90 }, LVL_HIGH, 1050000, 3 },
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[20] = { { 1804800, HFPLL, 1, 94 }, LVL_HIGH, 1050000, 3 },
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[21] = { { 1881600, HFPLL, 1, 98 }, LVL_HIGH, 1050000, 3 },
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[22] = { { 1958400, HFPLL, 1, 102 }, LVL_HIGH, 1050000, 3 },
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[23] = { { 2035200, HFPLL, 1, 106 }, LVL_HIGH, 1050000, 3 },
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[24] = { { 2112000, HFPLL, 1, 110 }, LVL_HIGH, 1050000, 3 },
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[25] = { { 2188800, HFPLL, 1, 114 }, LVL_HIGH, 1050000, 3 },
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{ }
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};
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static struct acpu_level acpu_freq_tbl[] __initdata = {
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{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 3200000 },
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{ 1, { 384000, HFPLL, 2, 40 }, L2(3), 950000, 3200000 },
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{ 1, { 460800, HFPLL, 2, 48 }, L2(3), 950000, 3200000 },
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{ 1, { 537600, HFPLL, 1, 28 }, L2(5), 950000, 3200000 },
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{ 1, { 576000, HFPLL, 1, 30 }, L2(5), 950000, 3200000 },
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{ 1, { 652800, HFPLL, 1, 34 }, L2(5), 950000, 3200000 },
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{ 1, { 729600, HFPLL, 1, 38 }, L2(5), 950000, 3200000 },
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{ 1, { 806400, HFPLL, 1, 42 }, L2(7), 950000, 3200000 },
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{ 1, { 883200, HFPLL, 1, 46 }, L2(7), 950000, 3200000 },
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{ 1, { 960000, HFPLL, 1, 50 }, L2(7), 950000, 3200000 },
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{ 1, { 1036800, HFPLL, 1, 54 }, L2(7), 950000, 3200000 },
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{ 1, { 1113600, HFPLL, 1, 58 }, L2(12), 1050000, 3200000 },
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{ 1, { 1190400, HFPLL, 1, 62 }, L2(12), 1050000, 3200000 },
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{ 1, { 1267200, HFPLL, 1, 66 }, L2(12), 1050000, 3200000 },
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{ 1, { 1344000, HFPLL, 1, 70 }, L2(15), 1050000, 3200000 },
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{ 1, { 1420800, HFPLL, 1, 74 }, L2(15), 1050000, 3200000 },
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{ 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
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{ 0, { 1574400, HFPLL, 1, 82 }, L2(20), 1050000, 3200000 },
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{ 0, { 1651200, HFPLL, 1, 86 }, L2(20), 1050000, 3200000 },
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{ 0, { 1728000, HFPLL, 1, 90 }, L2(20), 1050000, 3200000 },
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{ 0, { 1804800, HFPLL, 1, 94 }, L2(25), 1050000, 3200000 },
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{ 0, { 1881600, HFPLL, 1, 98 }, L2(25), 1050000, 3200000 },
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{ 0, { 1958400, HFPLL, 1, 102 }, L2(25), 1050000, 3200000 },
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{ 0, { 1996800, HFPLL, 1, 104 }, L2(25), 1050000, 3200000 },
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{ 0, { 0 } }
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};
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static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
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[0][PVS_SLOW] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
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[0][PVS_NOMINAL] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
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[0][PVS_FAST] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
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};
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static struct acpuclk_krait_params acpuclk_8974_params __initdata = {
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.scalable = scalable,
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.scalable_size = sizeof(scalable),
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.hfpll_data = &hfpll_data,
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.pvs_tables = pvs_tables,
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.l2_freq_tbl = l2_freq_tbl,
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.l2_freq_tbl_size = sizeof(l2_freq_tbl),
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.bus_scale = &bus_scale_data,
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.pte_efuse_phys = 0xFC4B80B0,
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.stby_khz = 300000,
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};
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static int __init acpuclk_8974_probe(struct platform_device *pdev)
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{
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return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
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}
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static struct of_device_id acpuclk_8974_match_table[] = {
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{ .compatible = "qcom,acpuclk-8974" },
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{}
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};
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static struct platform_driver acpuclk_8974_driver = {
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.driver = {
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.name = "acpuclk-8974",
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.of_match_table = acpuclk_8974_match_table,
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.owner = THIS_MODULE,
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},
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};
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static int __init acpuclk_8974_init(void)
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{
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return platform_driver_probe(&acpuclk_8974_driver,
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acpuclk_8974_probe);
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}
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device_initcall(acpuclk_8974_init);
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