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https://github.com/followmsi/android_kernel_google_msm.git
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7a8fee7870
Move logic for handling preamble based context switch to the core adreno code. This makes it less burdensome to implement support for newer GPU families that won't ever support legacy context switching. Change-Id: Id9ad5936ff91dcdbc9de869baf0d0b9fcf1b5170 Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
239 lines
10 KiB
C
239 lines
10 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "adreno.h"
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#include "a4xx_reg.h"
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#include "adreno_a3xx.h"
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/*
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* Set of registers to dump for A4XX on postmortem and snapshot.
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* Registers in pairs - first value is the start offset, second
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* is the stop offset (inclusive)
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*/
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const unsigned int a4xx_registers[] = {
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0x0000, 0x0002, /* RBBM_HW_VERSION - RBBM_HW_CONFIGURATION */
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0x0020, 0x0020, /* RBBM_CLOCK_CTL */
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0x0021, 0x0021, /* RBBM_SP_HYST_CNT */
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0x0023, 0x0024, /* RBBM_AHB_CTL0 - RBBM_AHB_CTL1 */
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0x0026, 0x0026, /* RBBM_RB_SUB_BLOCK_SEL_CTL */
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0x0028, 0x0034, /* RBBM_RAM_ACC_63_32 - RBBM_INTERFACE_HANG_MASK_CTL4 */
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0x0037, 0x003f, /* RBBM_INT_0_MASK - RBBM_AHB_DEBUG_CTL */
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0x0041, 0x0045, /* RBBM_VBIF_DEBUG_CTL - BLOCK_SW_RESET_CMD */
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0x0047, 0x0049, /* RBBM_RESET_CYCLES - RBBM_EXT_TRACE_BUS_CTL */
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0x009c, 0x0170, /* RBBM_PERFCTR_CP_0_LO - RBBM_PERFCTR_CTL */
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0x0174, 0x0182, /* RBBM_PERFCTR_LOAD_VALUE_LO - RBBM_CLOCK_STATUS */
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0x0189, 0x019f, /* RBBM_AHB_STATUS - RBBM_INTERFACE_RRDY_STATUS5 */
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0x0206, 0x0217, /* CP_IB1_BASE - CP_ME_RB_DONE_DATA */
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0x0219, 0x0219, /* CP_QUEUE_THRESH2 */
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0x021b, 0x021b, /* CP_MERCIU_SIZE */
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0x0228, 0x0229, /* CP_SCRATCH_UMASK - CP_SCRATCH_ADDR */
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0x022a, 0x022c, /* CP_PREEMPT - CP_CNTL */
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0x022e, 0x022e, /* CP_DEBUG */
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0x0231, 0x0232, /* CP_DEBUG_ECO_CONTROL - CP_DRAW_STATE_ADDR */
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0x0240, 0x0250, /* CP_PROTECT_REG_0 - CP_PROTECT_CTRL */
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0x04c0, 0x04ce, /* CP_ST_BASE - CP_STQ_AVAIL */
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0x04d0, 0x04d0, /* CP_MERCIU_STAT */
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0x04d2, 0x04dd, /* CP_WFI_PEND_CTR - CP_EVENTS_IN_FLIGHT */
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0x0500, 0x050b, /* CP_PERFCTR_CP_SEL_0 - CP_PERFCOMBINER_SELECT */
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0x0578, 0x058f, /* CP_SCRATCH_REG0 - CP_SCRATCH_REG23 */
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0x0c00, 0x0c03, /* VSC_BIN_SIZE - VSC_DEBUG_ECO_CONTROL */
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0x0c08, 0x0c41, /* VSC_PIPE_CONFIG_0 - VSC_PIPE_PARTIAL_POSN_1 */
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0x0c50, 0x0c51, /* VSC_PERFCTR_VSC_SEL_0 - VSC_PERFCTR_VSC_SEL_1 */
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0x0e64, 0x0e68, /* VPC_DEBUG_ECO_CONTROL - VPC_PERFCTR_VPC_SEL_3 */
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0x2140, 0x216e, /* VPC_ATTR - VPC_SO_FLUSH_WADDR_3 - ctx0 */
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0x2540, 0x256e, /* VPC_ATTR - VPC_SO_FLUSH_WADDR_3 - ctx1 */
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0x0f00, 0x0f0b, /* TPL1_DEBUG_ECO_CONTROL - TPL1_PERFCTR_TP_SEL_7 */
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/* TPL1_TP_TEX_OFFSET - TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR - ctx0 */
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0x2380, 0x23a6,
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/* TPL1_TP_TEX_OFFSET - TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR - ctx1 */
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0x2780, 0x27a6,
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0x0ec0, 0x0ecf, /* SP_VS_STATUS - SP_PERFCTR_SP_SEL_11 */
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0x22c0, 0x22c1, /* SP_SP_CTRL - SP_INSTR_CACHE_CTRL - ctx0 */
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0x22c4, 0x2360, /* SP_VS_CTRL_0 - SP_GS_LENGTH - ctx0 */
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0x26c0, 0x26c1, /* SP_SP_CTRL - SP_INSTR_CACHE_CTRL - ctx1 */
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0x26c4, 0x2760, /* SP_VS_CTRL_0 - SP_GS_LENGTH - ctx1 */
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0x0cc0, 0x0cd2, /* RB_GMEM_BASE_ADDR - RB_PERFCTR_CCU_SEL_3 */
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0x20a0, 0x213f, /* RB_MODE_CONTROL - RB_VPORT_Z_CLAMP_MAX_15 - ctx0 */
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0x24a0, 0x253f, /* RB_MODE_CONTROL - RB_VPORT_Z_CLAMP_MAX_15 - ctx1 */
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0x0e40, 0x0e4a, /* VFD_DEBUG_CONTROL - VFD_PERFCTR_VFD_SEL_7 */
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0x2200, 0x2204, /* VFD_CONTROL_0 - VFD_CONTROL_4 - ctx 0 */
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0x2208, 0x22a9, /* VFD_INDEX_OFFSET - VFD_DECODE_INSTR_31 - ctx 0 */
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0x2600, 0x2604, /* VFD_CONTROL_0 - VFD_CONTROL_4 - ctx 1 */
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0x2608, 0x26a9, /* VFD_INDEX_OFFSET - VFD_DECODE_INSTR_31 - ctx 1 */
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0x0c80, 0x0c81, /* GRAS_TSE_STATUS - GRAS_DEBUG_ECO_CONTROL */
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0x0c88, 0x0c8b, /* GRAS_PERFCTR_TSE_SEL_0 - GRAS_PERFCTR_TSE_SEL_3 */
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0x2000, 0x2004, /* GRAS_CL_CLIP_CNTL - GRAS_CL_GB_CLIP_ADJ - ctx 0 */
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/* GRAS_CL_VPORT_XOFFSET_0 - GRAS_SC_EXTENT_WINDOW_TL - ctx 0 */
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0x2008, 0x209f,
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0x2400, 0x2404, /* GRAS_CL_CLIP_CNTL - GRAS_CL_GB_CLIP_ADJ - ctx 1 */
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/* GRAS_CL_VPORT_XOFFSET_0 - GRAS_SC_EXTENT_WINDOW_TL - ctx 1 */
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0x2408, 0x249f,
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0x0e80, 0x0e84, /* UCHE_CACHE_MODE_CONTROL - UCHE_TRAP_BASE_HI */
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0x0e88, 0x0e95, /* UCHE_CACHE_STATUS - UCHE_PERFCTR_UCHE_SEL_7 */
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0x0e00, 0x0e00, /* HLSQ_TIMEOUT_THRESHOLD - HLSQ_TIMEOUT_THRESHOLD */
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0x0e04, 0x0e0e, /* HLSQ_DEBUG_ECO_CONTROL - HLSQ_PERF_PIPE_MASK */
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0x23c0, 0x23db, /* HLSQ_CONTROL_0 - HLSQ_UPDATE_CONTROL - ctx 0 */
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0x27c0, 0x27db, /* HLSQ_CONTROL_0 - HLSQ_UPDATE_CONTROL - ctx 1 */
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0x0d00, 0x0d0c, /* PC_BINNING_COMMAND - PC_DRAWCALL_SETUP_OVERRIDE */
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0x0d10, 0x0d17, /* PC_PERFCTR_PC_SEL_0 - PC_PERFCTR_PC_SEL_7 */
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0x21c0, 0x21c6, /* PC_BIN_BASE - PC_RESTART_INDEX - ctx 0 */
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0x21e5, 0x21e7, /* PC_GS_PARAM - PC_HS_PARAM - ctx 0 */
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0x25c0, 0x25c6, /* PC_BIN_BASE - PC_RESTART_INDEX - ctx 1 */
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0x25e5, 0x25e7, /* PC_GS_PARAM - PC_HS_PARAM - ctx 1 */
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};
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const unsigned int a4xx_registers_count = ARRAY_SIZE(a4xx_registers) / 2;
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static const struct adreno_vbif_data a420_vbif[] = {
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{ A4XX_VBIF_ABIT_SORT, 0x0001001F },
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{ A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
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{ A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001 },
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{ A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818 },
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{ A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018 },
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{ A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818 },
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{ A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018 },
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{ A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003 },
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{0, 0},
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};
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const struct adreno_vbif_platform a4xx_vbif_platforms[] = {
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{ adreno_is_a420, a420_vbif },
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};
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static void a4xx_start(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = &adreno_dev->dev;
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adreno_vbif_start(device, a4xx_vbif_platforms,
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ARRAY_SIZE(a4xx_vbif_platforms));
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/* Make all blocks contribute to the GPU BUSY perf counter */
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kgsl_regwrite(device, A4XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);
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/* Tune the hystersis counters for SP and CP idle detection */
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kgsl_regwrite(device, A4XX_RBBM_SP_HYST_CNT, 0x10);
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kgsl_regwrite(device, A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
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/*
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* Enable the RBBM error reporting bits. This lets us get
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* useful information on failure
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*/
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kgsl_regwrite(device, A4XX_RBBM_AHB_CTL0, 0x00000001);
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/* Enable AHB error reporting */
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kgsl_regwrite(device, A4XX_RBBM_AHB_CTL1, 0xA6FFFFFF);
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/*
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* Turn on hang detection - this spews a lot of useful information
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* into the RBBM registers on a hang
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*/
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kgsl_regwrite(device, A4XX_RBBM_INTERFACE_HANG_INT_CTL,
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(1 << 16) | 0xFFF);
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/* Set the OCMEM base address for A4XX */
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kgsl_regwrite(device, A4XX_RB_GMEM_BASE_ADDR,
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(unsigned int)(adreno_dev->ocmem_base >> 14));
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}
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/* Register offset defines for A4XX, in order of enum adreno_regs */
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static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
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ADRENO_REG_DEFINE(ADRENO_REG_CP_DEBUG, A4XX_CP_DEBUG),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_WADDR, A4XX_CP_ME_RAM_WADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_DATA, A4XX_CP_ME_RAM_DATA),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_DATA, A4XX_CP_PFP_UCODE_DATA),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_ADDR, A4XX_CP_PFP_UCODE_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_WFI_PEND_CTR, A4XX_CP_WFI_PEND_CTR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A4XX_CP_RB_BASE),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR_ADDR, A4XX_CP_RB_RPTR_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A4XX_CP_RB_RPTR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A4XX_CP_RB_WPTR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_CTRL, A4XX_CP_PROTECT_CTRL),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A4XX_CP_ME_CNTL),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A4XX_CP_RB_CNTL),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A4XX_CP_IB1_BASE),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BUFSZ, A4XX_CP_IB1_BUFSZ),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BASE, A4XX_CP_IB2_BASE),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BUFSZ, A4XX_CP_IB2_BUFSZ),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_TIMESTAMP, A4XX_CP_SCRATCH_REG0),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A4XX_CP_ME_RAM_RADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_ADDR, A4XX_CP_SCRATCH_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_UMSK, A4XX_CP_SCRATCH_UMASK),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A4XX_RBBM_STATUS),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A4XX_RBBM_PERFCTR_CTL),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,
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A4XX_RBBM_PERFCTR_LOAD_CMD0),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1,
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A4XX_RBBM_PERFCTR_LOAD_CMD1),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD2,
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A4XX_RBBM_PERFCTR_LOAD_CMD2),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_PWR_1_LO,
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A4XX_RBBM_PERFCTR_PWR_1_LO),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_MASK, A4XX_RBBM_INT_0_MASK),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_STATUS, A4XX_RBBM_INT_0_STATUS),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_AHB_ERROR_STATUS,
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A4XX_RBBM_AHB_ERROR_STATUS),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_AHB_CMD, A4XX_RBBM_AHB_CMD),
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ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_SEL,
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A4XX_VPC_DEBUG_RAM_SEL),
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ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_READ,
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A4XX_VPC_DEBUG_RAM_READ),
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ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_CLEAR_CMD,
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A4XX_RBBM_INT_CLEAR_CMD),
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ADRENO_REG_DEFINE(ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0,
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A4XX_VSC_PIPE_DATA_ADDRESS_0),
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ADRENO_REG_DEFINE(ADRENO_REG_VSC_PIPE_DATA_LENGTH_7,
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A4XX_VSC_PIPE_DATA_LENGTH_7),
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ADRENO_REG_DEFINE(ADRENO_REG_VSC_SIZE_ADDRESS, A4XX_VSC_SIZE_ADDRESS),
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ADRENO_REG_DEFINE(ADRENO_REG_VFD_CONTROL_0, A4XX_VFD_CONTROL_0),
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ADRENO_REG_DEFINE(ADRENO_REG_VFD_FETCH_INSTR_0_0,
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A4XX_VFD_FETCH_INSTR_0_0),
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ADRENO_REG_DEFINE(ADRENO_REG_VFD_FETCH_INSTR_1_F,
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A4XX_VFD_FETCH_INSTR_1_31),
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ADRENO_REG_DEFINE(ADRENO_REG_SP_VS_PVT_MEM_ADDR_REG,
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A4XX_SP_VS_PVT_MEM_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_SP_FS_PVT_MEM_ADDR_REG,
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A4XX_SP_FS_PVT_MEM_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_SP_VS_OBJ_START_REG,
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A4XX_SP_VS_OBJ_START),
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ADRENO_REG_DEFINE(ADRENO_REG_SP_FS_OBJ_START_REG,
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A4XX_SP_FS_OBJ_START),
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};
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const struct adreno_reg_offsets a4xx_reg_offsets = {
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.offsets = a4xx_register_offsets,
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.offset_0 = ADRENO_REG_REGISTER_MAX,
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};
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struct adreno_gpudev adreno_a4xx_gpudev = {
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.reg_offsets = &a4xx_reg_offsets,
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.rb_init = a3xx_rb_init,
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.irq_control = a3xx_irq_control,
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.irq_handler = a3xx_irq_handler,
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.irq_pending = a3xx_irq_pending,
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.busy_cycles = a3xx_busy_cycles,
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.start = a4xx_start,
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};
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