mirror of
https://github.com/followmsi/android_kernel_google_msm.git
synced 2024-11-06 23:17:41 +00:00
1299d2f5a3
This patch will queue multiple surfaces and commit those surfaces into mdp at same instance so that surfaces will be blended and displayed at same time. Hardware vsync event is delivered to the user space frame work via uevent. Both queue and commit are controlled by frame work and synchonized with vsync event. Therefore frame rate will match with vsync rate. Change-Id: If630a6d94fd38483ee313f575b1a71ed8bd65a52 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
505 lines
12 KiB
C
505 lines
12 KiB
C
/* Copyright (c) 2008-2009, 2012 Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/hrtimer.h>
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#include <linux/vmalloc.h>
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#include <linux/clk.h>
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#include <mach/hardware.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/mach-types.h>
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#include <linux/semaphore.h>
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#include <linux/uaccess.h>
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#include <mach/gpio.h>
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#include "mdp.h"
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#include "msm_fb.h"
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#include "mddihost.h"
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#ifdef CONFIG_FB_MSM_MDP40
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#include "mdp4.h"
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#define MDP_SYNC_CFG_0 0x100
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#define MDP_SYNC_STATUS_0 0x10c
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#define MDP_SYNC_CFG_1 0x104
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#define MDP_SYNC_STATUS_1 0x110
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#define MDP_PRIM_VSYNC_OUT_CTRL 0x118
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#define MDP_SEC_VSYNC_OUT_CTRL 0x11C
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#define MDP_VSYNC_SEL 0x124
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#define MDP_PRIM_VSYNC_INIT_VAL 0x128
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#define MDP_SEC_VSYNC_INIT_VAL 0x12C
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#else
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#define MDP_SYNC_CFG_0 0x300
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#define MDP_SYNC_STATUS_0 0x30c
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#define MDP_PRIM_VSYNC_OUT_CTRL 0x318
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#define MDP_PRIM_VSYNC_INIT_VAL 0x328
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#endif
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extern mddi_lcd_type mddi_lcd_idx;
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extern spinlock_t mdp_spin_lock;
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extern struct workqueue_struct *mdp_vsync_wq;
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extern int lcdc_mode;
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extern int vsync_mode;
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#ifdef MDP_HW_VSYNC
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int vsync_above_th = 4;
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int vsync_start_th = 1;
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int vsync_load_cnt;
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int vsync_clk_status;
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DEFINE_MUTEX(vsync_clk_lock);
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static DEFINE_SPINLOCK(vsync_timer_lock);
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static struct clk *mdp_vsync_clk;
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static struct msm_fb_data_type *vsync_mfd;
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static unsigned char timer_shutdown_flag;
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static uint32 vsync_cnt_cfg;
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void vsync_clk_enable()
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{
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if (mdp_vsync_clk)
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clk_prepare_enable(mdp_vsync_clk);
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}
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void vsync_clk_disable()
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{
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if (mdp_vsync_clk)
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clk_disable_unprepare(mdp_vsync_clk);
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}
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void mdp_hw_vsync_clk_enable(struct msm_fb_data_type *mfd)
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{
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if (vsync_clk_status == 1)
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return;
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mutex_lock(&vsync_clk_lock);
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if (mfd->use_mdp_vsync) {
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clk_prepare_enable(mdp_vsync_clk);
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vsync_clk_status = 1;
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}
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mutex_unlock(&vsync_clk_lock);
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}
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void mdp_hw_vsync_clk_disable(struct msm_fb_data_type *mfd)
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{
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if (vsync_clk_status == 0)
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return;
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mutex_lock(&vsync_clk_lock);
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if (mfd->use_mdp_vsync) {
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clk_disable_unprepare(mdp_vsync_clk);
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vsync_clk_status = 0;
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}
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mutex_unlock(&vsync_clk_lock);
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}
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static void mdp_set_vsync(unsigned long data);
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void mdp_vsync_clk_enable(void)
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{
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if (vsync_mfd) {
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mdp_hw_vsync_clk_enable(vsync_mfd);
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if (!vsync_mfd->vsync_resync_timer.function)
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mdp_set_vsync((unsigned long) vsync_mfd);
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}
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}
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void mdp_vsync_clk_disable(void)
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{
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if (vsync_mfd) {
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if (vsync_mfd->vsync_resync_timer.function) {
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spin_lock(&vsync_timer_lock);
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timer_shutdown_flag = 1;
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spin_unlock(&vsync_timer_lock);
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del_timer_sync(&vsync_mfd->vsync_resync_timer);
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spin_lock(&vsync_timer_lock);
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timer_shutdown_flag = 0;
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spin_unlock(&vsync_timer_lock);
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vsync_mfd->vsync_resync_timer.function = NULL;
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}
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mdp_hw_vsync_clk_disable(vsync_mfd);
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}
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}
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#endif
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static void mdp_set_vsync(unsigned long data)
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{
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struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)data;
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struct msm_fb_panel_data *pdata = NULL;
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pdata = (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
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vsync_mfd = mfd;
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init_timer(&mfd->vsync_resync_timer);
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if ((pdata) && (pdata->set_vsync_notifier == NULL))
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return;
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if ((mfd->panel_info.lcd.vsync_enable) && (mfd->panel_power_on)
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&& (!mfd->vsync_handler_pending)) {
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mfd->vsync_handler_pending = TRUE;
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if (!queue_work(mdp_vsync_wq, &mfd->vsync_resync_worker)) {
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MSM_FB_INFO
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("mdp_set_vsync: can't queue_work! -> needs to increase vsync_resync_timer_duration\n");
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}
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} else {
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MSM_FB_DEBUG
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("mdp_set_vsync failed! EN:%d PWR:%d PENDING:%d\n",
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mfd->panel_info.lcd.vsync_enable, mfd->panel_power_on,
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mfd->vsync_handler_pending);
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}
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spin_lock(&vsync_timer_lock);
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if (!timer_shutdown_flag) {
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mfd->vsync_resync_timer.function = mdp_set_vsync;
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mfd->vsync_resync_timer.data = data;
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mfd->vsync_resync_timer.expires =
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jiffies + mfd->panel_info.lcd.vsync_notifier_period;
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add_timer(&mfd->vsync_resync_timer);
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}
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spin_unlock(&vsync_timer_lock);
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}
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static void mdp_vsync_handler(void *data)
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{
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struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)data;
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if (vsync_clk_status == 0) {
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pr_debug("Warning: vsync clk is disabled\n");
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mfd->vsync_handler_pending = FALSE;
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return;
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}
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if (mfd->use_mdp_vsync) {
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#ifdef MDP_HW_VSYNC
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if (mfd->panel_power_on) {
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MDP_OUTP(MDP_BASE + MDP_SYNC_STATUS_0, vsync_load_cnt);
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#ifdef CONFIG_FB_MSM_MDP40
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if (mdp_hw_revision < MDP4_REVISION_V2_1)
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MDP_OUTP(MDP_BASE + MDP_SYNC_STATUS_1,
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vsync_load_cnt);
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#endif
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}
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#endif
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} else {
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mfd->last_vsync_timetick = ktime_get_real();
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}
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mfd->vsync_handler_pending = FALSE;
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}
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irqreturn_t mdp_hw_vsync_handler_proxy(int irq, void *data)
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{
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/*
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* ToDo: tried enabling/disabling GPIO MDP HW VSYNC interrupt
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* but getting inaccurate timing in mdp_vsync_handler()
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* disable_irq(MDP_HW_VSYNC_IRQ);
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*/
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mdp_vsync_handler(data);
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return IRQ_HANDLED;
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}
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#ifdef MDP_HW_VSYNC
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static void mdp_set_sync_cfg_0(struct msm_fb_data_type *mfd, int vsync_cnt)
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{
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unsigned long cfg;
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cfg = mfd->total_lcd_lines - 1;
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cfg <<= MDP_SYNCFG_HGT_LOC;
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if (mfd->panel_info.lcd.hw_vsync_mode)
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cfg |= MDP_SYNCFG_VSYNC_EXT_EN;
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cfg |= (MDP_SYNCFG_VSYNC_INT_EN | vsync_cnt);
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MDP_OUTP(MDP_BASE + MDP_SYNC_CFG_0, cfg);
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}
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#ifdef CONFIG_FB_MSM_MDP40
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static void mdp_set_sync_cfg_1(struct msm_fb_data_type *mfd, int vsync_cnt)
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{
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unsigned long cfg;
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cfg = mfd->total_lcd_lines - 1;
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cfg <<= MDP_SYNCFG_HGT_LOC;
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if (mfd->panel_info.lcd.hw_vsync_mode)
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cfg |= MDP_SYNCFG_VSYNC_EXT_EN;
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cfg |= (MDP_SYNCFG_VSYNC_INT_EN | vsync_cnt);
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MDP_OUTP(MDP_BASE + MDP_SYNC_CFG_1, cfg);
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}
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#endif
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void mdp_vsync_cfg_regs(struct msm_fb_data_type *mfd,
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boolean first_time)
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{
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/* MDP cmd block enable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON,
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FALSE);
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if (first_time)
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mdp_hw_vsync_clk_enable(mfd);
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mdp_set_sync_cfg_0(mfd, vsync_cnt_cfg);
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#ifdef CONFIG_FB_MSM_MDP40
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if (mdp_hw_revision < MDP4_REVISION_V2_1)
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mdp_set_sync_cfg_1(mfd, vsync_cnt_cfg);
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#endif
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/*
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* load the last line + 1 to be in the
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* safety zone
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*/
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vsync_load_cnt = mfd->panel_info.yres;
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/* line counter init value at the next pulse */
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MDP_OUTP(MDP_BASE + MDP_PRIM_VSYNC_INIT_VAL,
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vsync_load_cnt);
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#ifdef CONFIG_FB_MSM_MDP40
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if (mdp_hw_revision < MDP4_REVISION_V2_1) {
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MDP_OUTP(MDP_BASE + MDP_SEC_VSYNC_INIT_VAL,
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vsync_load_cnt);
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}
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#endif
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/*
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* external vsync source pulse width and
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* polarity flip
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*/
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MDP_OUTP(MDP_BASE + MDP_PRIM_VSYNC_OUT_CTRL, BIT(0));
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#ifdef CONFIG_FB_MSM_MDP40
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if (mdp_hw_revision < MDP4_REVISION_V2_1) {
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MDP_OUTP(MDP_BASE + MDP_SEC_VSYNC_OUT_CTRL, BIT(0));
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MDP_OUTP(MDP_BASE + MDP_VSYNC_SEL, 0x20);
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}
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#endif
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/* threshold */
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MDP_OUTP(MDP_BASE + 0x200, (vsync_above_th << 16) |
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(vsync_start_th));
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if (first_time)
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mdp_hw_vsync_clk_disable(mfd);
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/* MDP cmd block disable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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}
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#endif
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void mdp_config_vsync(struct platform_device *pdev,
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struct msm_fb_data_type *mfd)
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{
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/* vsync on primary lcd only for now */
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if ((mfd->dest != DISPLAY_LCD) || (mfd->panel_info.pdest != DISPLAY_1)
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|| (!vsync_mode)) {
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goto err_handle;
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}
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vsync_clk_status = 0;
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if (mfd->panel_info.lcd.vsync_enable) {
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mfd->total_porch_lines = mfd->panel_info.lcd.v_back_porch +
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mfd->panel_info.lcd.v_front_porch +
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mfd->panel_info.lcd.v_pulse_width;
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mfd->total_lcd_lines =
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mfd->panel_info.yres + mfd->total_porch_lines;
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mfd->lcd_ref_usec_time =
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100000000 / mfd->panel_info.lcd.refx100;
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mfd->vsync_handler_pending = FALSE;
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mfd->last_vsync_timetick.tv64 = 0;
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#ifdef MDP_HW_VSYNC
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if (mdp_vsync_clk == NULL)
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mdp_vsync_clk = clk_get(&pdev->dev, "vsync_clk");
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if (IS_ERR(mdp_vsync_clk)) {
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printk(KERN_ERR "error: can't get mdp_vsync_clk!\n");
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mfd->use_mdp_vsync = 0;
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} else
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mfd->use_mdp_vsync = 1;
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if (mfd->use_mdp_vsync) {
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uint32 vsync_cnt_cfg_dem;
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uint32 mdp_vsync_clk_speed_hz;
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mdp_vsync_clk_speed_hz = clk_get_rate(mdp_vsync_clk);
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if (mdp_vsync_clk_speed_hz == 0) {
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mfd->use_mdp_vsync = 0;
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} else {
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/*
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* Do this calculation in 2 steps for
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* rounding uint32 properly.
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*/
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vsync_cnt_cfg_dem =
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(mfd->panel_info.lcd.refx100 *
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mfd->total_lcd_lines) / 100;
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vsync_cnt_cfg =
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(mdp_vsync_clk_speed_hz) /
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vsync_cnt_cfg_dem;
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mdp_vsync_cfg_regs(mfd, TRUE);
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}
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}
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#else
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mfd->use_mdp_vsync = 0;
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hrtimer_init(&mfd->dma_hrtimer, CLOCK_MONOTONIC,
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HRTIMER_MODE_REL);
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mfd->dma_hrtimer.function = mdp_dma2_vsync_hrtimer_handler;
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mfd->vsync_width_boundary = vmalloc(mfd->panel_info.xres * 4);
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#endif
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#ifdef CONFIG_FB_MSM_MDDI
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mfd->channel_irq = 0;
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if (mfd->panel_info.lcd.hw_vsync_mode) {
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u32 vsync_gpio = mfd->vsync_gpio;
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u32 ret;
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if (vsync_gpio == -1) {
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MSM_FB_INFO("vsync_gpio not defined!\n");
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goto err_handle;
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}
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ret = gpio_tlmm_config(GPIO_CFG
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(vsync_gpio,
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(mfd->use_mdp_vsync) ? 1 : 0,
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GPIO_CFG_INPUT,
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GPIO_CFG_PULL_DOWN,
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GPIO_CFG_2MA),
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GPIO_CFG_ENABLE);
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if (ret)
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goto err_handle;
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/*
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* if use_mdp_vsync, then no interrupt need since
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* mdp_vsync is feed directly to mdp to reset the
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* write pointer counter. therefore no irq_handler
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* need to reset write pointer counter.
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*/
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if (!mfd->use_mdp_vsync) {
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mfd->channel_irq = MSM_GPIO_TO_INT(vsync_gpio);
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if (request_irq
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(mfd->channel_irq,
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&mdp_hw_vsync_handler_proxy,
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IRQF_TRIGGER_FALLING, "VSYNC_GPIO",
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(void *)mfd)) {
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MSM_FB_INFO
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("irq=%d failed! vsync_gpio=%d\n",
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mfd->channel_irq,
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vsync_gpio);
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goto err_handle;
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}
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}
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}
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#endif
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mdp_hw_vsync_clk_enable(mfd);
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mdp_set_vsync((unsigned long)mfd);
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}
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return;
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err_handle:
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if (mfd->vsync_width_boundary)
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vfree(mfd->vsync_width_boundary);
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mfd->panel_info.lcd.vsync_enable = FALSE;
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printk(KERN_ERR "%s: failed!\n", __func__);
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}
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void mdp_vsync_resync_workqueue_handler(struct work_struct *work)
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{
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struct msm_fb_data_type *mfd = NULL;
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int vsync_fnc_enabled = FALSE;
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struct msm_fb_panel_data *pdata = NULL;
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mfd = container_of(work, struct msm_fb_data_type, vsync_resync_worker);
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if (mfd) {
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if (mfd->panel_power_on) {
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pdata =
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(struct msm_fb_panel_data *)mfd->pdev->dev.
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platform_data;
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if (pdata->set_vsync_notifier != NULL) {
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if (pdata->clk_func && !pdata->clk_func(2)) {
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mfd->vsync_handler_pending = FALSE;
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return;
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}
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pdata->set_vsync_notifier(
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mdp_vsync_handler,
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(void *)mfd);
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vsync_fnc_enabled = TRUE;
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}
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}
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}
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if ((mfd) && (!vsync_fnc_enabled))
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mfd->vsync_handler_pending = FALSE;
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}
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boolean mdp_hw_vsync_set_handler(msm_fb_vsync_handler_type handler, void *data)
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{
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/*
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* ToDo: tried enabling/disabling GPIO MDP HW VSYNC interrupt
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* but getting inaccurate timing in mdp_vsync_handler()
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* enable_irq(MDP_HW_VSYNC_IRQ);
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*/
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return TRUE;
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}
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uint32 mdp_get_lcd_line_counter(struct msm_fb_data_type *mfd)
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{
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uint32 elapsed_usec_time;
|
|
uint32 lcd_line;
|
|
ktime_t last_vsync_timetick_local;
|
|
ktime_t curr_time;
|
|
unsigned long flag;
|
|
|
|
if ((!mfd->panel_info.lcd.vsync_enable) || (!vsync_mode))
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&mdp_spin_lock, flag);
|
|
last_vsync_timetick_local = mfd->last_vsync_timetick;
|
|
spin_unlock_irqrestore(&mdp_spin_lock, flag);
|
|
|
|
curr_time = ktime_get_real();
|
|
elapsed_usec_time = ktime_to_us(ktime_sub(curr_time,
|
|
last_vsync_timetick_local));
|
|
|
|
elapsed_usec_time = elapsed_usec_time % mfd->lcd_ref_usec_time;
|
|
|
|
/* lcd line calculation referencing to line counter = 0 */
|
|
lcd_line =
|
|
(elapsed_usec_time * mfd->total_lcd_lines) / mfd->lcd_ref_usec_time;
|
|
|
|
/* lcd line adjusment referencing to the actual line counter at vsync */
|
|
lcd_line =
|
|
(mfd->total_lcd_lines - mfd->panel_info.lcd.v_back_porch +
|
|
lcd_line) % (mfd->total_lcd_lines + 1);
|
|
|
|
if (lcd_line > mfd->total_lcd_lines) {
|
|
MSM_FB_INFO
|
|
("mdp_get_lcd_line_counter: mdp_lcd_rd_cnt >= mfd->total_lcd_lines error!\n");
|
|
}
|
|
|
|
return lcd_line;
|
|
}
|