Zhao Yakui fcb4561144 drm: Add the basic check for the detailed timing in EDID ... Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>		2009-10-28 11:23:39 +10:00
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drm	drm: Add the basic check for the detailed timing in EDID	2009-10-28 11:23:39 +10:00
vga	PCI/vgaarb: cleanup some warnings + cleanup some comments.	2009-09-09 13:29:41 -07:00
Makefile	PCI/GPU: implement VGA arbitration on Linux	2009-09-09 13:29:36 -07:00