mirror of
https://github.com/S3NEO/android_kernel_samsung_msm8226.git
synced 2024-11-07 03:47:13 +00:00
big-endian support for via-velocity
* kill bitfields * annotate * add missing conversions * fix a couple of brainos in zerocopy stuff (fortunately, it's ifdef'ed out) Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Al Viro
David S. Miller
parent
ad84243eb4
commit
4a51c0d02c
2 changed files with 129 additions and 167 deletions
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@ -8,7 +8,6 @@
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* for 64bit hardware platforms.
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*
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* TODO
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* Big-endian support
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* rx_copybreak/alignment
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* Scatter gather
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* More testing
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@ -681,7 +680,7 @@ static void velocity_rx_reset(struct velocity_info *vptr)
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* Init state, all RD entries belong to the NIC
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*/
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for (i = 0; i < vptr->options.numrx; ++i)
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vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC;
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vptr->rd_ring[i].rdesc0.len |= OWNED_BY_NIC;
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writew(vptr->options.numrx, ®s->RBRDU);
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writel(vptr->rd_pool_dma, ®s->RDBaseLo);
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@ -777,7 +776,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
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vptr->int_mask = INT_MASK_DEF;
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writel(cpu_to_le32(vptr->rd_pool_dma), ®s->RDBaseLo);
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writel(vptr->rd_pool_dma, ®s->RDBaseLo);
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writew(vptr->options.numrx - 1, ®s->RDCSize);
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mac_rx_queue_run(regs);
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mac_rx_queue_wake(regs);
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@ -785,7 +784,7 @@ static void velocity_init_registers(struct velocity_info *vptr,
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writew(vptr->options.numtx - 1, ®s->TDCSize);
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for (i = 0; i < vptr->num_txq; i++) {
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writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i]));
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writel(vptr->td_pool_dma[i], ®s->TDBaseLo[i]);
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mac_tx_queue_run(regs, i);
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}
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@ -1195,7 +1194,7 @@ static inline void velocity_give_many_rx_descs(struct velocity_info *vptr)
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dirty = vptr->rd_dirty - unusable;
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for (avail = vptr->rd_filled & 0xfffc; avail; avail--) {
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dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
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vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC;
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vptr->rd_ring[dirty].rdesc0.len |= OWNED_BY_NIC;
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}
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writew(vptr->rd_filled & 0xfffc, ®s->RBRDU);
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@ -1210,7 +1209,7 @@ static int velocity_rx_refill(struct velocity_info *vptr)
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struct rx_desc *rd = vptr->rd_ring + dirty;
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/* Fine for an all zero Rx desc at init time as well */
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if (rd->rdesc0.owner == OWNED_BY_NIC)
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if (rd->rdesc0.len & OWNED_BY_NIC)
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break;
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if (!vptr->rd_info[dirty].skb) {
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@ -1413,7 +1412,7 @@ static int velocity_rx_srv(struct velocity_info *vptr, int status)
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if (!vptr->rd_info[rd_curr].skb)
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break;
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if (rd->rdesc0.owner == OWNED_BY_NIC)
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if (rd->rdesc0.len & OWNED_BY_NIC)
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break;
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rmb();
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@ -1421,7 +1420,7 @@ static int velocity_rx_srv(struct velocity_info *vptr, int status)
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/*
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* Don't drop CE or RL error frame although RXOK is off
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*/
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if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) {
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if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
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if (velocity_receive_frame(vptr, rd_curr) < 0)
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stats->rx_dropped++;
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} else {
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@ -1433,7 +1432,7 @@ static int velocity_rx_srv(struct velocity_info *vptr, int status)
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stats->rx_dropped++;
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}
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rd->inten = 1;
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rd->size |= RX_INTEN;
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vptr->dev->last_rx = jiffies;
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@ -1554,7 +1553,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
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struct net_device_stats *stats = &vptr->stats;
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struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
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struct rx_desc *rd = &(vptr->rd_ring[idx]);
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int pkt_len = rd->rdesc0.len;
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int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
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struct sk_buff *skb;
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if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
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@ -1637,8 +1636,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
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*/
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*((u32 *) & (rd->rdesc0)) = 0;
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rd->len = cpu_to_le32(vptr->rx_buf_sz);
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rd->inten = 1;
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rd->size = cpu_to_le16(vptr->rx_buf_sz) | RX_INTEN;
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rd->pa_low = cpu_to_le32(rd_info->skb_dma);
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rd->pa_high = 0;
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return 0;
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@ -1674,7 +1672,7 @@ static int velocity_tx_srv(struct velocity_info *vptr, u32 status)
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td = &(vptr->td_rings[qnum][idx]);
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tdinfo = &(vptr->td_infos[qnum][idx]);
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if (td->tdesc0.owner == OWNED_BY_NIC)
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if (td->tdesc0.len & OWNED_BY_NIC)
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break;
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if ((works++ > 15))
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@ -1874,7 +1872,7 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_
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for (i = 0; i < tdinfo->nskb_dma; i++) {
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#ifdef VELOCITY_ZERO_COPY_SUPPORT
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pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], td->tdesc1.len, PCI_DMA_TODEVICE);
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pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE);
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#else
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pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE);
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#endif
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@ -2067,8 +2065,8 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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struct velocity_td_info *tdinfo;
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unsigned long flags;
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int index;
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int pktlen = skb->len;
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__le16 len = cpu_to_le16(pktlen);
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#ifdef VELOCITY_ZERO_COPY_SUPPORT
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if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
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@ -2083,9 +2081,8 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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td_ptr = &(vptr->td_rings[qnum][index]);
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tdinfo = &(vptr->td_infos[qnum][index]);
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td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;
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td_ptr->tdesc1.TCR = TCR0_TIC;
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td_ptr->td_buf[0].queue = 0;
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td_ptr->td_buf[0].size &= ~TD_QUEUE;
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/*
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* Pad short frames.
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@ -2093,16 +2090,16 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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if (pktlen < ETH_ZLEN) {
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/* Cannot occur until ZC support */
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pktlen = ETH_ZLEN;
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len = cpu_to_le16(ETH_ZLEN);
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skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
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memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
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tdinfo->skb = skb;
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tdinfo->skb_dma[0] = tdinfo->buf_dma;
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td_ptr->tdesc0.pktsize = pktlen;
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td_ptr->tdesc0.len = len;
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td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
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td_ptr->td_buf[0].pa_high = 0;
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td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
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td_ptr->td_buf[0].size = len; /* queue is 0 anyway */
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tdinfo->nskb_dma = 1;
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td_ptr->tdesc1.CMDZ = 2;
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} else
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#ifdef VELOCITY_ZERO_COPY_SUPPORT
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if (skb_shinfo(skb)->nr_frags > 0) {
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@ -2111,36 +2108,35 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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if (nfrags > 6) {
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skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
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tdinfo->skb_dma[0] = tdinfo->buf_dma;
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td_ptr->tdesc0.pktsize =
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td_ptr->tdesc0.len = len;
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td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
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td_ptr->td_buf[0].pa_high = 0;
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td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
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td_ptr->td_buf[0].size = len; /* queue is 0 anyway */
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tdinfo->nskb_dma = 1;
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td_ptr->tdesc1.CMDZ = 2;
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} else {
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int i = 0;
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tdinfo->nskb_dma = 0;
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tdinfo->skb_dma[i] = pci_map_single(vptr->pdev, skb->data, skb->len - skb->data_len, PCI_DMA_TODEVICE);
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tdinfo->skb_dma[i] = pci_map_single(vptr->pdev, skb->data,
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skb_headlen(skb), PCI_DMA_TODEVICE);
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td_ptr->tdesc0.pktsize = pktlen;
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td_ptr->tdesc0.len = len;
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/* FIXME: support 48bit DMA later */
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td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma);
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td_ptr->td_buf[i].pa_high = 0;
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td_ptr->td_buf[i].bufsize = skb->len->skb->data_len;
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td_ptr->td_buf[i].size = cpu_to_le16(skb_headlen(skb));
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for (i = 0; i < nfrags; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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void *addr = ((void *) page_address(frag->page + frag->page_offset));
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void *addr = (void *)page_address(frag->page) + frag->page_offset;
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tdinfo->skb_dma[i + 1] = pci_map_single(vptr->pdev, addr, frag->size, PCI_DMA_TODEVICE);
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td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
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td_ptr->td_buf[i + 1].pa_high = 0;
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td_ptr->td_buf[i + 1].bufsize = frag->size;
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td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size);
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}
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tdinfo->nskb_dma = i - 1;
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td_ptr->tdesc1.CMDZ = i;
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}
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} else
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@ -2152,18 +2148,16 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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*/
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tdinfo->skb = skb;
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tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
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td_ptr->tdesc0.pktsize = pktlen;
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td_ptr->tdesc0.len = len;
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td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
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td_ptr->td_buf[0].pa_high = 0;
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td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
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td_ptr->td_buf[0].size = len;
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tdinfo->nskb_dma = 1;
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td_ptr->tdesc1.CMDZ = 2;
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}
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td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
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if (vptr->vlgrp && vlan_tx_tag_present(skb)) {
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td_ptr->tdesc1.pqinf.VID = vlan_tx_tag_get(skb);
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td_ptr->tdesc1.pqinf.priority = 0;
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td_ptr->tdesc1.pqinf.CFI = 0;
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td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
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td_ptr->tdesc1.TCR |= TCR0_VETAG;
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}
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@ -2185,7 +2179,7 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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if (prev < 0)
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prev = vptr->options.numtx - 1;
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td_ptr->tdesc0.owner = OWNED_BY_NIC;
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td_ptr->tdesc0.len |= OWNED_BY_NIC;
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vptr->td_used[qnum]++;
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vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx;
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@ -2193,7 +2187,7 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
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netif_stop_queue(dev);
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td_ptr = &(vptr->td_rings[qnum][prev]);
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td_ptr->td_buf[0].queue = 1;
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td_ptr->td_buf[0].size |= TD_QUEUE;
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mac_tx_queue_wake(vptr->mac_regs, qnum);
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}
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dev->trans_start = jiffies;
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@ -3410,7 +3404,7 @@ static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
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velocity_save_context(vptr, &vptr->context);
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velocity_shutdown(vptr);
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velocity_set_wol(vptr);
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pci_enable_wake(pdev, 3, 1);
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pci_enable_wake(pdev, PCI_D3hot, 1);
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pci_set_power_state(pdev, PCI_D3hot);
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} else {
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velocity_save_context(vptr, &vptr->context);
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@ -70,40 +70,27 @@
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* Bits in the RSR0 register
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*/
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#define RSR_DETAG 0x0080
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#define RSR_SNTAG 0x0040
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#define RSR_RXER 0x0020
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#define RSR_RL 0x0010
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#define RSR_CE 0x0008
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#define RSR_FAE 0x0004
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#define RSR_CRC 0x0002
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#define RSR_VIDM 0x0001
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#define RSR_DETAG cpu_to_le16(0x0080)
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#define RSR_SNTAG cpu_to_le16(0x0040)
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#define RSR_RXER cpu_to_le16(0x0020)
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#define RSR_RL cpu_to_le16(0x0010)
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#define RSR_CE cpu_to_le16(0x0008)
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#define RSR_FAE cpu_to_le16(0x0004)
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#define RSR_CRC cpu_to_le16(0x0002)
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#define RSR_VIDM cpu_to_le16(0x0001)
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/*
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* Bits in the RSR1 register
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*/
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#define RSR_RXOK 0x8000 // rx OK
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#define RSR_PFT 0x4000 // Perfect filtering address match
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#define RSR_MAR 0x2000 // MAC accept multicast address packet
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#define RSR_BAR 0x1000 // MAC accept broadcast address packet
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#define RSR_PHY 0x0800 // MAC accept physical address packet
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#define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
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#define RSR_STP 0x0200 // start of packet
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#define RSR_EDP 0x0100 // end of packet
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/*
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* Bits in the RSR1 register
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*/
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#define RSR1_RXOK 0x80 // rx OK
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#define RSR1_PFT 0x40 // Perfect filtering address match
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#define RSR1_MAR 0x20 // MAC accept multicast address packet
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#define RSR1_BAR 0x10 // MAC accept broadcast address packet
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#define RSR1_PHY 0x08 // MAC accept physical address packet
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#define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
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#define RSR1_STP 0x02 // start of packet
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#define RSR1_EDP 0x01 // end of packet
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#define RSR_RXOK cpu_to_le16(0x8000) // rx OK
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#define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match
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#define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet
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#define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet
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#define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet
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#define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
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#define RSR_STP cpu_to_le16(0x0200) // start of packet
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#define RSR_EDP cpu_to_le16(0x0100) // end of packet
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/*
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* Bits in the CSM register
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@ -120,33 +107,21 @@
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* Bits in the TSR0 register
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*/
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#define TSR0_ABT 0x0080 // Tx abort because of excessive collision
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#define TSR0_OWT 0x0040 // Jumbo frame Tx abort
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#define TSR0_OWC 0x0020 // Out of window collision
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#define TSR0_COLS 0x0010 // experience collision in this transmit event
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#define TSR0_NCR3 0x0008 // collision retry counter[3]
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#define TSR0_NCR2 0x0004 // collision retry counter[2]
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#define TSR0_NCR1 0x0002 // collision retry counter[1]
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#define TSR0_NCR0 0x0001 // collision retry counter[0]
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#define TSR0_TERR 0x8000 //
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#define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
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#define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
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#define TSR0_LNKFL 0x1000 // packet serviced during link down
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#define TSR0_SHDN 0x0400 // shutdown case
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#define TSR0_CRS 0x0200 // carrier sense lost
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#define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
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/*
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* Bits in the TSR1 register
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*/
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#define TSR1_TERR 0x80 //
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#define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
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#define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
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#define TSR1_LNKFL 0x10 // packet serviced during link down
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#define TSR1_SHDN 0x04 // shutdown case
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#define TSR1_CRS 0x02 // carrier sense lost
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#define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
|
||||
#define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision
|
||||
#define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort
|
||||
#define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision
|
||||
#define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event
|
||||
#define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3]
|
||||
#define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2]
|
||||
#define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1]
|
||||
#define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0]
|
||||
#define TSR0_TERR cpu_to_le16(0x8000) //
|
||||
#define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
|
||||
#define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
|
||||
#define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down
|
||||
#define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case
|
||||
#define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost
|
||||
#define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
|
||||
|
||||
//
|
||||
// Bits in the TCR0 register
|
||||
|
|
@ -197,25 +172,26 @@
|
|||
*/
|
||||
|
||||
struct rdesc0 {
|
||||
u16 RSR; /* Receive status */
|
||||
u16 len:14; /* Received packet length */
|
||||
u16 reserved:1;
|
||||
u16 owner:1; /* Who owns this buffer ? */
|
||||
__le16 RSR; /* Receive status */
|
||||
__le16 len; /* bits 0--13; bit 15 - owner */
|
||||
};
|
||||
|
||||
struct rdesc1 {
|
||||
u16 PQTAG;
|
||||
__le16 PQTAG;
|
||||
u8 CSM;
|
||||
u8 IPKT;
|
||||
};
|
||||
|
||||
enum {
|
||||
RX_INTEN = __constant_cpu_to_le16(0x8000)
|
||||
};
|
||||
|
||||
struct rx_desc {
|
||||
struct rdesc0 rdesc0;
|
||||
struct rdesc1 rdesc1;
|
||||
u32 pa_low; /* Low 32 bit PCI address */
|
||||
u16 pa_high; /* Next 16 bit PCI address (48 total) */
|
||||
u16 len:15; /* Frame size */
|
||||
u16 inten:1; /* Enable interrupt */
|
||||
__le32 pa_low; /* Low 32 bit PCI address */
|
||||
__le16 pa_high; /* Next 16 bit PCI address (48 total) */
|
||||
__le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
/*
|
||||
|
|
@ -223,32 +199,24 @@ struct rx_desc {
|
|||
*/
|
||||
|
||||
struct tdesc0 {
|
||||
u16 TSR; /* Transmit status register */
|
||||
u16 pktsize:14; /* Size of frame */
|
||||
u16 reserved:1;
|
||||
u16 owner:1; /* Who owns the buffer */
|
||||
__le16 TSR; /* Transmit status register */
|
||||
__le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
|
||||
};
|
||||
|
||||
struct pqinf { /* Priority queue info */
|
||||
u16 VID:12;
|
||||
u16 CFI:1;
|
||||
u16 priority:3;
|
||||
struct tdesc1 {
|
||||
__le16 vlan;
|
||||
u8 TCR;
|
||||
u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
struct tdesc1 {
|
||||
struct pqinf pqinf;
|
||||
u8 TCR;
|
||||
u8 TCPLS:2;
|
||||
u8 reserved:2;
|
||||
u8 CMDZ:4;
|
||||
} __attribute__ ((__packed__));
|
||||
enum {
|
||||
TD_QUEUE = __constant_cpu_to_le16(0x8000)
|
||||
};
|
||||
|
||||
struct td_buf {
|
||||
u32 pa_low;
|
||||
u16 pa_high;
|
||||
u16 bufsize:14;
|
||||
u16 reserved:1;
|
||||
u16 queue:1;
|
||||
__le32 pa_low;
|
||||
__le16 pa_high;
|
||||
__le16 size; /* bits 0--13 - size, bit 15 - queue */
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
struct tx_desc {
|
||||
|
|
@ -276,7 +244,7 @@ struct velocity_td_info {
|
|||
|
||||
enum velocity_owner {
|
||||
OWNED_BY_HOST = 0,
|
||||
OWNED_BY_NIC = 1
|
||||
OWNED_BY_NIC = __constant_cpu_to_le16(0x8000)
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -1012,45 +980,45 @@ struct mac_regs {
|
|||
volatile u8 RCR;
|
||||
volatile u8 TCR;
|
||||
|
||||
volatile u32 CR0Set; /* 0x08 */
|
||||
volatile u32 CR0Clr; /* 0x0C */
|
||||
volatile __le32 CR0Set; /* 0x08 */
|
||||
volatile __le32 CR0Clr; /* 0x0C */
|
||||
|
||||
volatile u8 MARCAM[8]; /* 0x10 */
|
||||
|
||||
volatile u32 DecBaseHi; /* 0x18 */
|
||||
volatile u16 DbfBaseHi; /* 0x1C */
|
||||
volatile u16 reserved_1E;
|
||||
volatile __le32 DecBaseHi; /* 0x18 */
|
||||
volatile __le16 DbfBaseHi; /* 0x1C */
|
||||
volatile __le16 reserved_1E;
|
||||
|
||||
volatile u16 ISRCTL; /* 0x20 */
|
||||
volatile __le16 ISRCTL; /* 0x20 */
|
||||
volatile u8 TXESR;
|
||||
volatile u8 RXESR;
|
||||
|
||||
volatile u32 ISR; /* 0x24 */
|
||||
volatile u32 IMR;
|
||||
volatile __le32 ISR; /* 0x24 */
|
||||
volatile __le32 IMR;
|
||||
|
||||
volatile u32 TDStatusPort; /* 0x2C */
|
||||
volatile __le32 TDStatusPort; /* 0x2C */
|
||||
|
||||
volatile u16 TDCSRSet; /* 0x30 */
|
||||
volatile __le16 TDCSRSet; /* 0x30 */
|
||||
volatile u8 RDCSRSet;
|
||||
volatile u8 reserved_33;
|
||||
volatile u16 TDCSRClr;
|
||||
volatile __le16 TDCSRClr;
|
||||
volatile u8 RDCSRClr;
|
||||
volatile u8 reserved_37;
|
||||
|
||||
volatile u32 RDBaseLo; /* 0x38 */
|
||||
volatile u16 RDIdx; /* 0x3C */
|
||||
volatile u16 reserved_3E;
|
||||
volatile __le32 RDBaseLo; /* 0x38 */
|
||||
volatile __le16 RDIdx; /* 0x3C */
|
||||
volatile __le16 reserved_3E;
|
||||
|
||||
volatile u32 TDBaseLo[4]; /* 0x40 */
|
||||
volatile __le32 TDBaseLo[4]; /* 0x40 */
|
||||
|
||||
volatile u16 RDCSize; /* 0x50 */
|
||||
volatile u16 TDCSize; /* 0x52 */
|
||||
volatile u16 TDIdx[4]; /* 0x54 */
|
||||
volatile u16 tx_pause_timer; /* 0x5C */
|
||||
volatile u16 RBRDU; /* 0x5E */
|
||||
volatile __le16 RDCSize; /* 0x50 */
|
||||
volatile __le16 TDCSize; /* 0x52 */
|
||||
volatile __le16 TDIdx[4]; /* 0x54 */
|
||||
volatile __le16 tx_pause_timer; /* 0x5C */
|
||||
volatile __le16 RBRDU; /* 0x5E */
|
||||
|
||||
volatile u32 FIFOTest0; /* 0x60 */
|
||||
volatile u32 FIFOTest1; /* 0x64 */
|
||||
volatile __le32 FIFOTest0; /* 0x60 */
|
||||
volatile __le32 FIFOTest1; /* 0x64 */
|
||||
|
||||
volatile u8 CAMADDR; /* 0x68 */
|
||||
volatile u8 CAMCR; /* 0x69 */
|
||||
|
|
@ -1063,18 +1031,18 @@ struct mac_regs {
|
|||
volatile u8 PHYSR1;
|
||||
volatile u8 MIICR;
|
||||
volatile u8 MIIADR;
|
||||
volatile u16 MIIDATA;
|
||||
volatile __le16 MIIDATA;
|
||||
|
||||
volatile u16 SoftTimer0; /* 0x74 */
|
||||
volatile u16 SoftTimer1;
|
||||
volatile __le16 SoftTimer0; /* 0x74 */
|
||||
volatile __le16 SoftTimer1;
|
||||
|
||||
volatile u8 CFGA; /* 0x78 */
|
||||
volatile u8 CFGB;
|
||||
volatile u8 CFGC;
|
||||
volatile u8 CFGD;
|
||||
|
||||
volatile u16 DCFG; /* 0x7C */
|
||||
volatile u16 MCFG;
|
||||
volatile __le16 DCFG; /* 0x7C */
|
||||
volatile __le16 MCFG;
|
||||
|
||||
volatile u8 TBIST; /* 0x80 */
|
||||
volatile u8 RBIST;
|
||||
|
|
@ -1086,9 +1054,9 @@ struct mac_regs {
|
|||
volatile u8 rev_id;
|
||||
volatile u8 PORSTS;
|
||||
|
||||
volatile u32 MIBData; /* 0x88 */
|
||||
volatile __le32 MIBData; /* 0x88 */
|
||||
|
||||
volatile u16 EEWrData;
|
||||
volatile __le16 EEWrData;
|
||||
|
||||
volatile u8 reserved_8E;
|
||||
volatile u8 BPMDWr;
|
||||
|
|
@ -1098,7 +1066,7 @@ struct mac_regs {
|
|||
volatile u8 EECHKSUM; /* 0x92 */
|
||||
volatile u8 EECSR;
|
||||
|
||||
volatile u16 EERdData; /* 0x94 */
|
||||
volatile __le16 EERdData; /* 0x94 */
|
||||
volatile u8 EADDR;
|
||||
volatile u8 EMBCMD;
|
||||
|
||||
|
|
@ -1112,22 +1080,22 @@ struct mac_regs {
|
|||
volatile u8 DEBUG;
|
||||
volatile u8 CHIPGCR;
|
||||
|
||||
volatile u16 WOLCRSet; /* 0xA0 */
|
||||
volatile __le16 WOLCRSet; /* 0xA0 */
|
||||
volatile u8 PWCFGSet;
|
||||
volatile u8 WOLCFGSet;
|
||||
|
||||
volatile u16 WOLCRClr; /* 0xA4 */
|
||||
volatile __le16 WOLCRClr; /* 0xA4 */
|
||||
volatile u8 PWCFGCLR;
|
||||
volatile u8 WOLCFGClr;
|
||||
|
||||
volatile u16 WOLSRSet; /* 0xA8 */
|
||||
volatile u16 reserved_AA;
|
||||
volatile __le16 WOLSRSet; /* 0xA8 */
|
||||
volatile __le16 reserved_AA;
|
||||
|
||||
volatile u16 WOLSRClr; /* 0xAC */
|
||||
volatile u16 reserved_AE;
|
||||
volatile __le16 WOLSRClr; /* 0xAC */
|
||||
volatile __le16 reserved_AE;
|
||||
|
||||
volatile u16 PatternCRC[8]; /* 0xB0 */
|
||||
volatile u32 ByteMask[4][4]; /* 0xC0 */
|
||||
volatile __le16 PatternCRC[8]; /* 0xB0 */
|
||||
volatile __le32 ByteMask[4][4]; /* 0xC0 */
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
|
||||
|
|
@ -1238,12 +1206,12 @@ typedef u8 MCAM_ADDR[ETH_ALEN];
|
|||
struct arp_packet {
|
||||
u8 dest_mac[ETH_ALEN];
|
||||
u8 src_mac[ETH_ALEN];
|
||||
u16 type;
|
||||
u16 ar_hrd;
|
||||
u16 ar_pro;
|
||||
__be16 type;
|
||||
__be16 ar_hrd;
|
||||
__be16 ar_pro;
|
||||
u8 ar_hln;
|
||||
u8 ar_pln;
|
||||
u16 ar_op;
|
||||
__be16 ar_op;
|
||||
u8 ar_sha[ETH_ALEN];
|
||||
u8 ar_sip[4];
|
||||
u8 ar_tha[ETH_ALEN];
|
||||
|
|
@ -1253,7 +1221,7 @@ struct arp_packet {
|
|||
struct _magic_packet {
|
||||
u8 dest_mac[6];
|
||||
u8 src_mac[6];
|
||||
u16 type;
|
||||
__be16 type;
|
||||
u8 MAC[16][6];
|
||||
u8 password[6];
|
||||
} __attribute__ ((__packed__));
|
||||
|
|
|
|||
Loading…
Reference in a new issue