164 lines
6.1 KiB
C
164 lines
6.1 KiB
C
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ISA1200_VIBRATOR_H
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#define _ISA1200_VIBRATOR_H
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#include <mach/msm_iomap.h>
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#define VIBRATION_ON 1
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#define VIBRATION_OFF 0
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#define HCTRL0 (0x30) /* 0x09 */ /* Haptic Motor Driver Control Register Group 0*/
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#define HCTRL1 (0x31) /* 0x4B */ /* Haptic Motor Driver Control Register Group 1*/
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#define MAX_INTENSITY 10000
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#define GP_CLK_M_DEFAULT 2
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#if defined (CONFIG_MACH_MATISSELTE_ATT)
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#define GP_CLK_N_DEFAULT 122
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#define GP_CLK_D_DEFAULT 61 /* 50% duty cycle */
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#else
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#if defined CONFIG_MACH_MATISSE3G_OPEN || defined CONFIG_SEC_MATISSELTE_COMMON
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#define GP_CLK_N_DEFAULT 99
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#define GP_CLK_D_DEFAULT 44 /* 50% duty cycle */
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#else
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#define GP_CLK_N_DEFAULT 93
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#define GP_CLK_D_DEFAULT 47 /* 50% duty cycle */
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#endif
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#endif//CONFIG_MACH_MATISSELTE_ATT
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#define IMM_PWM_MULTIPLIER GP_CLK_N_DEFAULT /* Must be integer */
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/*
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* ** Global variables for LRA PWM M,N and D values.
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* */
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#define MOTOR_MIN_STRENGTH 54/*IMMERSION VALUE*/
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#define MOTOR_STRENGTH 98/*MOTOR_STRENGTH 98 %*/
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int32_t g_nlra_gp_clk_m = GP_CLK_M_DEFAULT;
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int32_t g_nlra_gp_clk_n = GP_CLK_N_DEFAULT;
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int32_t g_nlra_gp_clk_d = GP_CLK_D_DEFAULT;
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int32_t g_nlra_gp_clk_pwm_mul = IMM_PWM_MULTIPLIER;
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int32_t motor_strength = MOTOR_STRENGTH;
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int32_t motor_min_strength;
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#define __inp(port) ioread8(port)
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#define __inpw(port) ioread16(port)
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#define __inpdw(port) ioread32(port)
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#define __outp(port, val) iowrite8(val, port)
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#define __outpw(port, val) iowrite16(val, port)
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#define __outpdw(port, val) iowrite32(val, port)
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#define in_dword(addr) (__inpdw(addr))
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#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
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#define out_dword(addr, val) __outpdw(addr, val)
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#define out_dword_masked(io, mask, val, shadow) \
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(void) out_dword(io, \
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((shadow & (unsigned int)(~(mask))) | ((unsigned int)((val) & (mask)))))
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#define out_dword_masked_ns(io, mask, val, current_reg_content) \
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(void) out_dword(io, \
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((current_reg_content & (unsigned int)(~(mask))) \
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| ((unsigned int)((val) & (mask)))))
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#if !defined(CONFIG_MOTOR_DRV_ISA1400)
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static void __iomem *virt_mmss_gp1_base;
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#define HWIO_GP1_CMD_RCGR_ADDR ((void __iomem *)(virt_mmss_gp1_base + 0)) //MMSS_CC_GP1_CMD_RCGR
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#define HWIO_GP1_CFG_RCGR_ADDR ((void __iomem *)(virt_mmss_gp1_base + 4)) //MMSS_CC_GP1_CFG_RCGR
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#define HWIO_GP_M_REG_ADDR ((void __iomem *)(virt_mmss_gp1_base + 8)) //MMSS_CC_GP1_M
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#define HWIO_GP_NS_REG_ADDR ((void __iomem *)(virt_mmss_gp1_base + 0xc)) //MMSS_CC_GP1_N
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#define HWIO_GP_D_REG_ADDR ((void __iomem *)(virt_mmss_gp1_base + 0x10)) //MMSS_CC_GP1_D
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#if defined(CONFIG_MACH_HLTEDCM) || defined(CONFIG_MACH_HLTEKDI) || defined(CONFIG_MACH_JS01LTEDCM)
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#define HWIO_CAMSS_GP1_CBCR_ADDR ((void __iomem *)(virt_mmss_gp1_base - 0x4)) //MMSS_CC_CAMSS_GP3_CBCR
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#else
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#define HWIO_CAMSS_GP1_CBCR_ADDR ((void __iomem *)(virt_mmss_gp1_base + 0x24)) //MMSS_CC_CAMSS_GP1_CBCR
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#endif
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#define HWIO_GP_MD_REG_RMSK 0xffffffff
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#define HWIO_GP_NS_REG_RMSK 0xffffffff
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#define HWIO_GP_MD_REG_M_VAL_BMSK 0xff
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#define HWIO_GP_MD_REG_M_VAL_SHFT 0
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#define HWIO_GP_MD_REG_D_VAL_BMSK 0xff
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#define HWIO_GP_MD_REG_D_VAL_SHFT 0
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#define HWIO_GP_NS_REG_GP_N_VAL_BMSK 0xff
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#define HWIO_GP_SRC_SEL_VAL_BMSK 0x700
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#define HWIO_GP_SRC_SEL_VAL_SHFT 8
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#define HWIO_GP_SRC_DIV_VAL_BMSK 0x1f
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#define HWIO_GP_SRC_DIV_VAL_SHFT 0
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#define HWIO_GP_MODE_VAL_BMSK 0x3000
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#define HWIO_GP_MODE_VAL_SHFT 12
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#define HWIO_CLK_ENABLE_VAL_BMSK 0x1
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#define HWIO_CLK_ENABLE_VAL_SHFT 0
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#define HWIO_UPDATE_VAL_BMSK 0x1
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#define HWIO_UPDATE_VAL_SHFT 0
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#define HWIO_ROOT_EN_VAL_BMSK 0x2
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#define HWIO_ROOT_EN_VAL_SHFT 1
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#define HWIO_GP1_CMD_RCGR_IN \
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in_dword_masked(HWIO_GP1_CMD_RCGR_ADDR, HWIO_GP_NS_REG_RMSK)
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#define HWIO_GP1_CMD_RCGR_OUTM(m, v) \
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out_dword_masked_ns(HWIO_GP1_CMD_RCGR_ADDR, m, v, HWIO_GP1_CMD_RCGR_IN)
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#define HWIO_GP1_CFG_RCGR_IN \
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in_dword_masked(HWIO_GP1_CFG_RCGR_ADDR, HWIO_GP_NS_REG_RMSK)
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#define HWIO_GP1_CFG_RCGR_OUTM(m, v) \
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out_dword_masked_ns(HWIO_GP1_CFG_RCGR_ADDR, m, v, HWIO_GP1_CFG_RCGR_IN)
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#define HWIO_CAMSS_GP1_CBCR_IN \
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in_dword_masked(HWIO_CAMSS_GP1_CBCR_ADDR, HWIO_GP_NS_REG_RMSK)
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#define HWIO_CAMSS_GP1_CBCR_OUTM(m, v) \
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out_dword_masked_ns(HWIO_CAMSS_GP1_CBCR_ADDR, m, v, HWIO_CAMSS_GP1_CBCR_IN)
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#define HWIO_GP_D_REG_IN \
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in_dword_masked(HWIO_GP_D_REG_ADDR, HWIO_GP_MD_REG_RMSK)
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#define HWIO_GP_D_REG_OUTM(m, v)\
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out_dword_masked_ns(HWIO_GP_D_REG_ADDR, m, v, HWIO_GP_D_REG_IN)
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#define HWIO_GP_M_REG_IN \
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in_dword_masked(HWIO_GP_M_REG_ADDR, HWIO_GP_MD_REG_RMSK)
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#define HWIO_GP_M_REG_OUTM(m, v)\
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out_dword_masked_ns(HWIO_GP_M_REG_ADDR, m, v, HWIO_GP_M_REG_IN)
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#define HWIO_GP_NS_REG_IN \
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in_dword_masked(HWIO_GP_NS_REG_ADDR, HWIO_GP_NS_REG_RMSK)
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#define HWIO_GP_NS_REG_OUTM(m, v) \
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out_dword_masked_ns(HWIO_GP_NS_REG_ADDR, m, v, HWIO_GP_NS_REG_IN)
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#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
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#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
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#endif
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int vibrator_write_register(u8 addr, u8 w_data);
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extern struct vibrator_platform_data_isa1200 vibrator_drvdata;
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#endif
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