447 lines
10 KiB
ArmAsm
447 lines
10 KiB
ArmAsm
/*
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* arch/arm/mm/proc-v7-2level.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define TTB_S (1 << 1)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_OC_WBWA (1 << 3)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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#define TTB_NOS (1 << 5)
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#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
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#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
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#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
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#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
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#define PMD_FLAGS_UP PMD_SECT_WB
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
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#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
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#ifdef CONFIG_TIMA_RKP
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#if __GNUC__ >= 4 && __GNUC_MINOR__ >= 6
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.arch_extension sec
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#endif
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#endif
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
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ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
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#ifdef CONFIG_ARM_ERRATA_430973
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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#endif
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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mrc p15, 0, r2, c13, c0, 1 @ read current context ID
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bic r2, r2, #0xff @ extract the PID
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and r1, r1, #0xff
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orr r1, r1, r2 @ insert the PID into r1
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#endif
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#ifdef CONFIG_TIMA_RKP
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stmfd sp!, {r2, r11}
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/* TZ side expects r0 to be in r11 */
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mov r11, r0
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/* r2 : mcr_val */
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mov r2, r0
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/* r0: command */
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ldr r0, =0x3f803221
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smc #1
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/* Restore r0 and r2 */
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ldmfd sp!, {r2, r11}
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#ifdef CONFIG_TIMA_RKP_30
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/* Flush TLB */
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mcr p15, 0, r0, c8, c3, 0
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dsb
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#endif
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#endif
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isb
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#ifdef CONFIG_ARM_ERRATA_754322
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dsb
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#endif
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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isb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_switch_mm)
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#ifdef CONFIG_TIMA_RKP_L2_GROUP
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/*
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* Pass the pointer to the group buffer and its length to TZ side.
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* cpu_v7_timal2group_set_pte_commit(tima_l2group_entry_ptr,
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* tima_l2group_entries_count)
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*/
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ENTRY(cpu_v7_timal2group_set_pte_commit)
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/* Second parameter is the length, move it to r2 */
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mov r2, r1
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/* First parameter is the address, move it to r1 */
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mov r1, r0
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stmfd sp!,{r0-r3, r11}
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stmfd sp!,{r0}
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mov r11, r3
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ldr r0, =0x3f811221 @cmd_id=0x11
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smc #1
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pop {r0}
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pop {r0-r3, r11}
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mov pc, lr
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ENDPROC(cpu_v7_timal2group_set_pte_commit)
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/*
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* Function writes the pte addr, arm pte value and linux
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* pte value at the address pointed to by the L2 group
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* pointer.
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* cpu_v7_timal2group_set_pte_ext(pte_t *ptep, pte_t pte,
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* unsigned int ext, unsigned long tima_l2group_entry_ptr);
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*/
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ENTRY(cpu_v7_timal2group_set_pte_ext)
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#ifdef CONFIG_MMU
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/* r3 has the pointer to the new entry */
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stmfd sp!,{r4}
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stmfd sp!,{r5}
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stmfd sp!,{r1}
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stmfd sp!,{r3}
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bic r3, r1, #0x000003f0
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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tst r1, #1 << 4
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orrne r3, r3, #PTE_EXT_TEX(1)
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
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orrne r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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/* grouped operations*/
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/*pop back the buffer pointer to r2*/
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pop {r2}
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pop {r1}
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mov r5, #0
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ldr r4, [r0]
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cmp r1, r4 /* r1 has linux pte value */
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bne 1f
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ldr r4, [r0, #2048]
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cmp r3, r4 /* r3 has arm pte value */
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bne 1f
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mov r5, #5
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b 2f
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1:
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//ldr r0, =0xdeadbee1
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/* r0 has the pointer to the pte */
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str r0, [r2]
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/* flush cache after the str */
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mcr p15, 0, r2, c7, c14, 1
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//ldr r1, =0xdeadbee2
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add r2, r2, #4
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/* r1 has the linux pte value */
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str r1, [r2]
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/* flush cache after the str */
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mcr p15, 0, r2, c7, c14, 1
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//ldr r3, =0xdeadbee3
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add r2, r2, #4
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/* r3 has the arm pte value */
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str r3, [r2]
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/* flush cache after the str */
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mcr p15, 0, r2, c7, c14, 1
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dsb
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isb
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#endif
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2:
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mov r0, r5
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pop {r5}
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pop {r4}
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mov pc, lr
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ENDPROC(cpu_v7_timal2group_set_pte_ext)
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#endif /* CONFIG_TIMA_RKP_L2_GROUP */
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#ifdef CONFIG_TIMA_RKP
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ENTRY(cpu_v7_tima_iommu_opt)
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stmfd sp!,{r0-r3, r11}
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mov r3, r2
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/* Second parameter is the end addr, move it to r2 */
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mov r2, r1
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/* First parameter is the start addr, move it to r1 */
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mov r1, r0
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stmfd sp!,{r0}
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mov r11, r3
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ldr r0, =0x3f820221 @cmd_id=0x20
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smc #1
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pop {r0}
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pop {r0-r3, r11}
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mov pc, lr
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ENDPROC(cpu_v7_tima_iommu_opt)
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#endif
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* (hardware version is stored at +2048 bytes)
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*/
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#ifdef CONFIG_TIMA_RKP_L2_TABLES
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ENTRY(cpu_v7_tima_set_pte_ext)
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# ifdef CONFIG_MMU
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stmfd sp!, {r1} //added for tima
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bic r3, r1, #0x000003f0
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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tst r1, #1 << 4
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orrne r3, r3, #PTE_EXT_TEX(1)
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
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orrne r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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/*next part is added for tima*/
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/** Check if the kernel is re-writing the same value!
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* In case of tima, such rewrites are unnecessary and expensive.
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*/
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ldr r2, [r0]
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cmp r1, r2
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bne 1f
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ldr r2, [r0, #2048]
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cmp r3, r2
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beq 4f
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1:
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/** Prepare the stack for L2 write emulation!
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*/
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pop {r1}
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stmfd sp!,{r0-r3, r11}
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stmfd sp!,{r0}
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mov r11, r0
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/** Cache invalidate the values to be written
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*/
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#ifndef CONFIG_TIMA_RKP_COHERENT_TT
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mcr p15, 0, r0, c7, c14, 1 @ flush_linux_pte
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#endif
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add r0, r0, #2048
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#ifndef CONFIG_TIMA_RKP_COHERENT_TT
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mcr p15, 0, r0, c7, c14, 1 @ flush_arm_pte
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dsb
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isb
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#endif
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ldr r0, =0x3f807221
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smc #1
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pop {r0}
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/** Cache invalidate again to ensure no
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* values re-cached by speculative fetching
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*/
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#ifndef CONFIG_TIMA_RKP_COHERENT_TT
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mcr p15, 0, r0, c7, c6, 1
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dsb
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isb
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#endif
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#ifdef CONFIG_TIMA_RKP_DEBUG
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ldr r2, [r0]
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cmp r1, r2
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beq 2f
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stmfd sp!, {r0}
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ldr r0, =0x3f80f221 @cmd_id=0x0f
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smc #1
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pop {r0}
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2:
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#endif
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add r0, r0, #2048
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#ifndef CONFIG_TIMA_RKP_COHERENT_TT
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mcr p15, 0, r0, c7, c6, 1
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dsb
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isb
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#else
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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dsb
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isb
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#endif
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#ifdef CONFIG_TIMA_RKP_DEBUG
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ldr r2, [r0]
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cmp r3, r2
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beq 3f
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stmfd sp!, {r0}
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ldr r0, =0x3f80f221 @cmd_id=0x0f
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smc #1
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pop {r0}
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3:
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#endif
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pop {r0-r3, r11}
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4:
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_tima_set_pte_ext)
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#endif
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#ifdef CONFIG_TIMA_RKP
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.global cpu_v7_set_pte_ext_proc_end
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#endif
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0] @ linux version
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bic r3, r1, #0x000003f0
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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tst r1, #1 << 4
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orrne r3, r3, #PTE_EXT_TEX(1)
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
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orrne r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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ARM( str r3, [r0, #2048]! )
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THUMB( add r0, r0, #2048 )
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THUMB( str r3, [r0] )
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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#ifdef CONFIG_TIMA_RKP
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cpu_v7_set_pte_ext_proc_end:
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#endif
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ENDPROC(cpu_v7_set_pte_ext)
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/*
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* Memory region attributes with SCTLR.TRE=1
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*
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* n = TEX[0],C,B
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* TR = PRRR[2n+1:2n] - memory type
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* IR = NMRR[2n+1:2n] - inner cacheable property
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* OR = NMRR[2n+17:2n+16] - outer cacheable property
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*
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* n TR IR OR
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* UNCACHED 000 00
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* BUFFERABLE 001 10 00 00
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* WRITETHROUGH 010 10 10 10
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* WRITEBACK 011 10 11 11
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* reserved 110
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* WRITEALLOC 111 10 01 01
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* DEV_SHARED 100 01
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* DEV_NONSHARED 100 01
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* DEV_WC 001 10
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* DEV_CACHED 011 10
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*
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* Other attributes:
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*
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* DS0 = PRRR[16] = 0 - device shareable property
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* DS1 = PRRR[17] = 1 - device shareable property
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* NS0 = PRRR[18] = 0 - normal shareable property
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* NS1 = PRRR[19] = 1 - normal shareable property
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* NOS = PRRR[24+n] = 1 - not outer shareable
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*/
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.equ PRRR, 0xff0a81a8
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#ifdef CONFIG_ARCH_MSM_SCORPIONMP
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.equ NMRR, 0x40e080e0
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#else
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.equ NMRR, 0x40e040e0
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#endif
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/*
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* Macro for setting up the TTBRx and TTBCR registers.
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* - \ttb0 and \ttb1 updated with the corresponding flags.
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*/
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.macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
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#ifdef CONFIG_TIMA_RKP_EMUL_CP15_INSTR
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ldr r0, =0x3f805221
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smc #1
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#else
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mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
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#endif
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ALT_SMP(orr \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
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ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP)
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ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
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ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
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mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
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.endm
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__CPUINIT
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/* AT
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* TFR EV X F I D LR S
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* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
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* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 1 0 110 0011 1100 .111 1101 < we want
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*/
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.align 2
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
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.previous
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