2014-02-12 00:53:43 +00:00
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/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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2013-02-20 02:59:40 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2012-06-03 21:51:38 +00:00
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#ifndef _CORESIGHT_PRIV_H
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#define _CORESIGHT_PRIV_H
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2013-02-20 02:59:40 +00:00
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#include <linux/bitops.h>
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/* Coresight management registers (0xF00-0xFCC)
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* 0xFA0 - 0xFA4: Management registers in PFTv1.0
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* Trace registers in PFTv1.1
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*/
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2012-06-03 21:51:38 +00:00
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#define CORESIGHT_ITCTRL (0xF00)
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#define CORESIGHT_CLAIMSET (0xFA0)
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#define CORESIGHT_CLAIMCLR (0xFA4)
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#define CORESIGHT_LAR (0xFB0)
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#define CORESIGHT_LSR (0xFB4)
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#define CORESIGHT_AUTHSTATUS (0xFB8)
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#define CORESIGHT_DEVID (0xFC8)
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#define CORESIGHT_DEVTYPE (0xFCC)
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#define CORESIGHT_UNLOCK (0xC5ACCE55)
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2013-02-20 02:59:40 +00:00
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#define TIMEOUT_US (100)
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#define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb))
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#define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb)
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#define BVAL(val, n) ((val & BIT(n)) >> n)
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2013-06-14 06:21:40 +00:00
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#ifdef CONFIG_CORESIGHT_FUSE
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extern bool coresight_fuse_access_disabled(void);
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extern bool coresight_fuse_apps_access_disabled(void);
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2014-02-12 00:53:43 +00:00
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extern bool coresight_fuse_qpdi_access_disabled(void);
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2014-01-14 06:59:32 +00:00
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extern bool coresight_fuse_nidnt_access_disabled(void);
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2013-06-14 06:21:40 +00:00
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#else
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static inline bool coresight_fuse_access_disabled(void) { return false; }
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static inline bool coresight_fuse_apps_access_disabled(void) { return false; }
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2014-02-12 00:53:43 +00:00
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static inline bool coresight_fuse_qpdi_access_disabled(void) { return false; }
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2014-01-14 06:59:32 +00:00
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static inline bool coresight_fuse_nidnt_access_disabled(void) { return false; }
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2013-06-14 06:21:40 +00:00
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#endif
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2013-01-28 04:30:42 +00:00
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#ifdef CONFIG_CORESIGHT_CSR
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2012-07-23 06:09:11 +00:00
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extern void msm_qdss_csr_enable_bam_to_usb(void);
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extern void msm_qdss_csr_disable_bam_to_usb(void);
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2013-01-26 20:14:59 +00:00
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extern void msm_qdss_csr_disable_flush(void);
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2013-07-22 22:19:42 +00:00
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extern int coresight_csr_hwctrl_set(uint64_t addr, uint32_t val);
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2013-05-03 20:18:44 +00:00
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extern void coresight_csr_set_byte_cntr(uint32_t);
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2012-07-23 06:09:11 +00:00
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#else
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static inline void msm_qdss_csr_enable_bam_to_usb(void) {}
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static inline void msm_qdss_csr_disable_bam_to_usb(void) {}
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2013-01-26 20:14:59 +00:00
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static inline void msm_qdss_csr_disable_flush(void) {}
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2013-07-22 22:19:42 +00:00
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static inline int coresight_csr_hwctrl_set(uint64_t addr,
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2013-04-02 20:51:13 +00:00
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uint32_t val) { return -ENOSYS; }
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2013-05-03 20:18:44 +00:00
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static inline void coresight_csr_set_byte_cntr(uint32_t val) {}
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2013-01-28 04:30:42 +00:00
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#endif
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#ifdef CONFIG_CORESIGHT_ETM
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extern unsigned int etm_readl_cp14(uint32_t off);
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extern void etm_writel_cp14(uint32_t val, uint32_t off);
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#else
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2012-09-12 19:50:29 +00:00
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static inline unsigned int etm_readl_cp14(uint32_t off) { return 0; }
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static inline void etm_writel_cp14(uint32_t val, uint32_t off) {}
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2012-07-23 06:09:11 +00:00
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#endif
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2014-07-23 17:58:49 +00:00
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#if defined(CONFIG_CORESIGHT_ETM) || defined(CONFIG_CORESIGHT_ETMV4)
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extern int coresight_etm_get_funnel_port(int cpu);
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#else
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static inline int coresight_etm_get_funnel_port(int cpu) { return -ENOSYS; }
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#endif
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2012-07-23 06:09:11 +00:00
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2013-02-20 02:59:40 +00:00
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#endif
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