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hwmon: qpnp-voltage: Support multiple device instance 

Support multiple voltage ADC device instance. Clients
need to register with the voltage ADC using the device
consumer name used to associate with the corresponding
phandle of the VADC. Clients receive the device instance
which is to be used everytime an ADC request is made.

This change involves changing the interface to issue
ADC request and the corresponding clients changes.

Change-Id: If0557bc657fecd172a8cf960900ee93b4bce37f8
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
This commit is contained in:
Siddartha Mohanadoss 2013-06-21 12:07:05 -07:00 committed by Stephen Boyd
parent 5c8963d93e
commit 000325beb7
20 changed files with 433 additions and 255 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/bif/qpnp-bsi.txt
View File

@ -49,6 +49,7 @@ Optional properties:
- qcom,vref-microvolts: Reference voltage used for BCL divider circuit in
microvolts. If no value is specified, then
1800000 uV is assumed.
- qcom,bsi-vadc: Corresponding VADC device phandle.
All properties specified within for the BIF framework can also be used. These
properties can be found in bif.txt.
@ -86,6 +87,7 @@ Example:
qcom,channel-num = <0x31>;
qcom,pullup-ohms = <100000>;
qcom,vref-microvolts = <1800000>;
qcom,bsi-vadc = <&pm8941_vadc>;
};
};
};

3
Documentation/devicetree/bindings/hwmon/qpnp-adc-current.txt
View File

@ -84,6 +84,8 @@ Required properties:
6 : 64
7 : 128
8 : 256
- qcom,iadc-vadc : Corresponding phandle of the VADC device to read the die_temperature and set
simultaneous voltage and current conversion requests.
Example:
/* Main Node */
@ -97,6 +99,7 @@ Example:
qcom,adc-bit-resolution = <16>;
qcom,adc-vdd-reference = <1800>;
qcom,rsense = <1500>;
qcom,iadc-vadc = <&pm8941_vadc>;
/* Channel Node */
chan@0 = {

12
Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt
View File

@ -20,6 +20,12 @@ Required properties:
Channel nodes
NOTE: Atleast one Channel node is required.
Client required property:
- qcom,<consumer name>-vadc : The phandle to the corresponding vadc device.
The consumer name passed to the driver when calling
qpnp_get_vadc() is used to associate the client
with the corresponding device.
Required properties:
- label : Channel name used for sysfs entry.
- reg : AMUX channel number.
@ -113,6 +119,12 @@ Example:
};
};
Client device example:
/* Add to the clients node that needs the VADC channel A/D */
client_node {
qcom,client-vadc = <&pm8941_vadc>;
};
/* Clients have an option of measuring an analog signal through an MPP.
MPP block is not part of the VADC block but is an individual PMIC
block that has an option to support clients to configure an MPP as

2
Documentation/devicetree/bindings/power/qpnp-bms.txt
View File

@ -86,6 +86,7 @@ Parent node required properties:
for storing the FCC(mAh) in the 8-bit BMS register.
For example - A value of 10 indicates:
FCC value (in mAh) = (8-bit register value) * 10.
- qcom,bms-vadc: Corresponding VADC device's phandle.
Parent node optional properties:
- qcom,ignore-shutdown-soc: A boolean that controls whether BMS will
@ -148,6 +149,7 @@ pm8941_bms: qcom,bms {
qcom,hold-soc-est = <3>;
qcom,tm-temp-margin = <5000>;
qcom,battery-data = <&mtp_batterydata>;
qcom,bms-vadc = <&pm8941_vadc>;
qcom,bms-iadc@3800 {
reg = <0x3800 0x100>;

2
Documentation/devicetree/bindings/power/qpnp-charger.txt
View File

@ -80,6 +80,7 @@ Parent node optional properties:
for the boost regulator.
- qcom,resume-soc Capacity in percent at which charging should resume
when a fully charged battery drops below this level.
- qcom,chg-vadc Corresponding VADC device's phandle.
Sub node required structure:
- A qcom,chg node must be a child of an SPMI node that has specified
@ -196,6 +197,7 @@ Example:
qcom,batt-hot-percent = <25>;
qcom,batt-cold-percent = <85>;
qcom,btc-disabled = <0>;
qcom,chg-vadc = <&pm8941_vadc>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;

2
Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
View File

@ -95,6 +95,7 @@ Required properties:
8 : 256
- qcom,btm-channel-number : There are 5 BTM channels. The BTM channel numbers are statically
allocated to the corresponding channel node.
- qcom,adc_tm-vadc : phandle to the corresponding VADC device to read the ADC channels.
Example:
/* Main Node */
@ -111,6 +112,7 @@ Example:
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,adc_tm-vadc = <&pm8941_vadc>;
/* Channel Node to be registered as part of thermal sysfs */
chan@b5 {

2
Documentation/devicetree/bindings/thermal/qpnp-temp-alarm.txt
View File

@ -37,6 +37,7 @@ Optional properties:
- qcom,default-temp: Specifies the default temperature in millicelcius to use
if no ADC channel is present to read the real time
temperature.
- qcom,temp_alarm-vadc: Corresponding VADC device's phandle.
Note, if a given optional qcom,* binding is not present, then the default
hardware state for that feature will be maintained.
@ -61,6 +62,7 @@ Example:
label = "pm8941_tz";
qcom,channel-num = <8>;
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pm8941_vadc>;
};
};
};

5
arch/arm/boot/dts/msm-pm8110.dtsi
View File

@ -68,6 +68,7 @@
qcom,vbatdet-delta-mv = <350>;
qcom,resume-soc = <99>;
qcom,tchg-mins = <150>;
qcom,chg-vadc = <&pm8110_vadc>;
qcom,chgr@1000 {
status = "disabled";
@ -258,6 +259,7 @@
interrupt-names = "eoc-int-en-set";
qcom,adc-bit-resolution = <16>;
qcom,adc-vdd-reference = <1800>;
qcom,iadc-vadc = <&pm8110_vadc>;
chan@0 {
label = "internal_rsense";
@ -284,6 +286,7 @@
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,adc_tm-vadc = <&pm8110_vadc>;
};
qcom,temp-alarm@2400 {
@ -293,6 +296,7 @@
label = "pm8110_tz";
qcom,channel-num = <8>;
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pm8110_vadc>;
};
pm8110_bms: qcom,bms {
@ -320,6 +324,7 @@
qcom,low-ocv-correction-limit-uv = <100>;
qcom,high-ocv-correction-limit-uv = <50>;
qcom,hold-soc-est = <3>;
qcom,bms-vadc = <&pm8110_vadc>;
qcom,bms-iadc@3800 {
reg = <0x3800 0x100>;

7
arch/arm/boot/dts/msm-pm8226.dtsi
View File

@ -83,6 +83,7 @@
qcom,thermal-mitigation = <1500 700 600 325>;
qcom,resume-soc = <99>;
qcom,tchg-mins = <150>;
qcom,chg-vadc = <&pm8226_vadc>;
qcom,chgr@1000 {
status = "disabled";
@ -196,6 +197,7 @@
qcom,high-ocv-correction-limit-uv = <50>;
qcom,hold-soc-est = <3>;
qcom,low-voltage-threshold = <3420000>;
qcom,bms-vadc = <&pm8226_vadc>;
qcom,bms-iadc@3800 {
reg = <0x3800 0x100>;
@ -396,7 +398,7 @@
};
};
iadc@3600 {
pm8226_iadc: iadc@3600 {
compatible = "qcom,qpnp-iadc";
reg = <0x3600 0x100>;
#address-cells = <1>;
@ -405,6 +407,7 @@
interrupt-names = "eoc-int-en-set";
qcom,adc-bit-resolution = <16>;
qcom,adc-vdd-reference = <1800>;
qcom,iadc-vadc = <&pm8226_vadc>;
chan@0 {
label = "internal_rsense";
@ -431,6 +434,7 @@
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,adc_tm-vadc = <&pm8226_vadc>;
};
qcom,temp-alarm@2400 {
@ -440,6 +444,7 @@
label = "pm8226_tz";
qcom,channel-num = <8>;
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pm8226_vadc>;
};
qcom,pm8226_rtc {

6
arch/arm/boot/dts/msm-pm8941.dtsi
View File

@ -39,6 +39,7 @@
label = "pm8941_tz";
qcom,channel-num = <8>;
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pm8941_vadc>;
};
qcom,power-on@800 {
@ -100,6 +101,7 @@
qcom,min-clock-period = <1000>;
qcom,max-clock-period = <160000>;
qcom,sample-rate = <4>;
qcom,bsi-vadc = <&pm8941_vadc>;
};
pm8941_coincell: qcom,coincell@2800 {
@ -132,6 +134,7 @@
qcom,low-ocv-correction-limit-uv = <100>;
qcom,high-ocv-correction-limit-uv = <50>;
qcom,hold-soc-est = <3>;
qcom,bms-vadc = <&pm8941_vadc>;
qcom,bms-iadc@3800 {
reg = <0x3800 0x100>;
@ -200,6 +203,7 @@
qcom,vbatdet-delta-mv = <100>;
qcom,resume-soc = <99>;
qcom,tchg-mins = <150>;
qcom,chg-vadc = <&pm8941_vadc>;
qcom,chgr@1000 {
status = "disabled";
@ -806,6 +810,7 @@
interrupt-names = "eoc-int-en-set";
qcom,adc-bit-resolution = <16>;
qcom,adc-vdd-reference = <1800>;
qcom,iadc-vadc = <&pm8941_vadc>;
chan@0 {
label = "internal_rsense";
@ -832,6 +837,7 @@
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,adc_tm-vadc = <&pm8941_vadc>;
/* Channel Node */
chan@b9 {

1
arch/arm/boot/dts/msm-pma8084.dtsi
View File

@ -77,6 +77,7 @@
interrupts = <0x0 0x24 0x0>;
label = "pma8084_tz";
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pma8084_vadc>;
};
qcom,coincell@2800 {

11
drivers/bif/qpnp-bsi.c
View File

@ -56,6 +56,7 @@ struct qpnp_bsi_chip {
atomic_t irq_flag[QPNP_BSI_IRQ_COUNT];
int batt_present_irq;
enum qpnp_vadc_channels batt_id_adc_channel;
struct qpnp_vadc_chip *vadc_dev;
};
#define QPNP_BSI_DRIVER_NAME "qcom,qpnp-bsi"
@ -1343,7 +1344,8 @@ static int qpnp_bsi_get_battery_rid(struct bif_ctrl_dev *bdev)
return -ENXIO;
}
rc = qpnp_vadc_read(chip->batt_id_adc_channel, &adc_result);
rc = qpnp_vadc_read(chip->vadc_dev, chip->batt_id_adc_channel,
&adc_result);
if (!rc) {
vid_uV = adc_result.physical;
@ -1672,8 +1674,11 @@ static int qpnp_bsi_probe(struct spmi_device *spmi)
/* Ensure that ADC channel is available if it was specified. */
if (chip->batt_id_adc_channel < ADC_MAX_NUM) {
rc = qpnp_vadc_is_ready();
if (rc) {
chip->vadc_dev = qpnp_get_vadc(dev, "bsi");
if (IS_ERR(chip->vadc_dev)) {
rc = PTR_ERR(chip->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("missing vadc property, rc=%d\n", rc);
/* Probe retry, do not print an error message */
goto cleanup_irqs;
}

53
drivers/hwmon/qpnp-adc-common.c
View File

@ -377,7 +377,8 @@ static int64_t qpnp_adc_scale_ratiometric_calib(int32_t adc_code,
return adc_voltage;
}
int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
int32_t qpnp_adc_scale_pmic_therm(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -421,7 +422,7 @@ int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_pmic_therm);
int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(struct qpnp_vadc_chip *chip,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{
@ -429,7 +430,7 @@ int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
int64_t low_output = 0, high_output = 0;
int rc = 0, sign = 0;
rc = qpnp_get_vadc_gain_and_offset(&btm_param, CALIB_ABSOLUTE);
rc = qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_ABSOLUTE);
if (rc < 0) {
pr_err("Could not acquire gain and offset\n");
return rc;
@ -476,7 +477,8 @@ EXPORT_SYMBOL(qpnp_adc_scale_millidegc_pmic_voltage_thr);
/* Scales the ADC code to degC using the mapping
* table for the XO thermistor.
*/
int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
int32_t qpnp_adc_tdkntcg_therm(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -499,7 +501,8 @@ int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_tdkntcg_therm);
int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
int32_t qpnp_adc_scale_batt_therm(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -517,7 +520,8 @@ int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_batt_therm);
int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
int32_t qpnp_adc_scale_qrd_batt_therm(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -535,7 +539,8 @@ int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_qrd_batt_therm);
int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
int32_t qpnp_adc_scale_therm_pu1(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -553,7 +558,8 @@ int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_therm_pu1);
int32_t qpnp_adc_scale_therm_pu2(int32_t adc_code,
int32_t qpnp_adc_scale_therm_pu2(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -571,13 +577,14 @@ int32_t qpnp_adc_scale_therm_pu2(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_therm_pu2);
int32_t qpnp_adc_tm_scale_voltage_therm_pu2(uint32_t reg, int64_t *result)
int32_t qpnp_adc_tm_scale_voltage_therm_pu2(struct qpnp_vadc_chip *chip,
uint32_t reg, int64_t *result)
{
int64_t adc_voltage = 0;
struct qpnp_vadc_linear_graph param1;
int negative_offset;
qpnp_get_vadc_gain_and_offset(&param1, CALIB_RATIOMETRIC);
qpnp_get_vadc_gain_and_offset(chip, &param1, CALIB_RATIOMETRIC);
adc_voltage = (reg - param1.adc_gnd) * param1.adc_vref;
if (adc_voltage < 0) {
@ -597,12 +604,13 @@ int32_t qpnp_adc_tm_scale_voltage_therm_pu2(uint32_t reg, int64_t *result)
}
EXPORT_SYMBOL(qpnp_adc_tm_scale_voltage_therm_pu2);
int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_adc_tm_config *param)
int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_vadc_chip *chip,
struct qpnp_adc_tm_config *param)
{
struct qpnp_vadc_linear_graph param1;
int rc;
qpnp_get_vadc_gain_and_offset(&param1, CALIB_RATIOMETRIC);
qpnp_get_vadc_gain_and_offset(chip, &param1, CALIB_RATIOMETRIC);
rc = qpnp_adc_map_temp_voltage(adcmap_100k_104ef_104fb,
ARRAY_SIZE(adcmap_100k_104ef_104fb),
@ -628,7 +636,8 @@ int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_adc_tm_config *param)
}
EXPORT_SYMBOL(qpnp_adc_tm_scale_therm_voltage_pu2);
int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
int32_t qpnp_adc_scale_batt_id(struct qpnp_vadc_chip *chip,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -644,7 +653,8 @@ int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_batt_id);
int32_t qpnp_adc_scale_default(int32_t adc_code,
int32_t qpnp_adc_scale_default(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_properties,
const struct qpnp_vadc_chan_properties *chan_properties,
struct qpnp_vadc_result *adc_chan_result)
@ -701,12 +711,13 @@ int32_t qpnp_adc_scale_default(int32_t adc_code,
}
EXPORT_SYMBOL(qpnp_adc_scale_default);
int32_t qpnp_adc_usb_scaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_usb_scaler(struct qpnp_vadc_chip *chip,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{
struct qpnp_vadc_linear_graph usb_param;
qpnp_get_vadc_gain_and_offset(&usb_param, CALIB_RATIOMETRIC);
qpnp_get_vadc_gain_and_offset(chip, &usb_param, CALIB_RATIOMETRIC);
*low_threshold = param->low_thr * usb_param.dy;
do_div(*low_threshold, usb_param.adc_vref);
@ -722,14 +733,15 @@ int32_t qpnp_adc_usb_scaler(struct qpnp_adc_tm_btm_param *param,
}
EXPORT_SYMBOL(qpnp_adc_usb_scaler);
int32_t qpnp_adc_vbatt_rscaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_vbatt_rscaler(struct qpnp_vadc_chip *chip,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{
struct qpnp_vadc_linear_graph vbatt_param;
int rc = 0, sign = 0;
int64_t low_thr = 0, high_thr = 0;
rc = qpnp_get_vadc_gain_and_offset(&vbatt_param, CALIB_ABSOLUTE);
rc = qpnp_get_vadc_gain_and_offset(chip, &vbatt_param, CALIB_ABSOLUTE);
if (rc < 0)
return rc;
@ -764,14 +776,15 @@ int32_t qpnp_adc_vbatt_rscaler(struct qpnp_adc_tm_btm_param *param,
}
EXPORT_SYMBOL(qpnp_adc_vbatt_rscaler);
int32_t qpnp_adc_btm_scaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_btm_scaler(struct qpnp_vadc_chip *chip,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{
struct qpnp_vadc_linear_graph btm_param;
int64_t low_output = 0, high_output = 0;
int rc = 0;
qpnp_get_vadc_gain_and_offset(&btm_param, CALIB_RATIOMETRIC);
qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_RATIOMETRIC);
pr_debug("warm_temp:%d and cool_temp:%d\n", param->high_temp,
param->low_temp);

15
drivers/hwmon/qpnp-adc-current.c
View File

@ -145,6 +145,7 @@ struct qpnp_iadc_drv {
struct mutex iadc_vadc_lock;
bool iadc_mode_sel;
struct qpnp_iadc_comp iadc_comp;
struct qpnp_vadc_chip *vadc_dev;
struct sensor_device_attribute sens_attr[0];
bool skip_auto_calibrations;
};
@ -723,7 +724,7 @@ static int32_t qpnp_check_pmic_temp(void)
int64_t die_temp_offset;
int rc = 0;
rc = qpnp_vadc_read(DIE_TEMP, &result_pmic_therm);
rc = qpnp_vadc_read(iadc->vadc_dev, DIE_TEMP, &result_pmic_therm);
if (rc < 0)
return rc;
@ -882,7 +883,7 @@ int32_t qpnp_iadc_vadc_sync_read(
iadc->iadc_mode_sel = true;
rc = qpnp_vadc_iadc_sync_request(v_channel);
rc = qpnp_vadc_iadc_sync_request(iadc->vadc_dev, v_channel);
if (rc) {
pr_err("Configuring VADC failed\n");
goto fail;
@ -893,7 +894,7 @@ int32_t qpnp_iadc_vadc_sync_read(
pr_err("Configuring IADC failed\n");
/* Intentional fall through to release VADC */
rc = qpnp_vadc_iadc_sync_complete_request(v_channel,
rc = qpnp_vadc_iadc_sync_complete_request(iadc->vadc_dev, v_channel,
v_result);
if (rc)
pr_err("Releasing VADC failed\n");
@ -1005,6 +1006,14 @@ static int qpnp_iadc_probe(struct spmi_device *spmi)
goto fail;
}
iadc->vadc_dev = qpnp_get_vadc(&spmi->dev, "iadc");
if (IS_ERR(iadc->vadc_dev)) {
rc = PTR_ERR(iadc->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("vadc property missing, rc=%d\n", rc);
goto fail;
}
mutex_init(&iadc->adc->adc_lock);
rc = of_property_read_u32(node, "qcom,rsense",

317
drivers/hwmon/qpnp-adc-voltage.c
View File

@ -101,19 +101,21 @@
#define QPNP_ADC_COMPLETION_TIMEOUT HZ
#define QPNP_VADC_ERR_COUNT 5
struct qpnp_vadc_drv {
struct qpnp_vadc_chip {
struct device *dev;
struct qpnp_adc_drv *adc;
struct list_head list;
struct dentry *dent;
struct device *vadc_hwmon;
bool vadc_init_calib;
bool vadc_initialized;
int max_channels_available;
bool vadc_iadc_sync_lock;
u8 id;
struct work_struct trigger_completion_work;
struct sensor_device_attribute sens_attr[0];
};
struct qpnp_vadc_drv *qpnp_vadc;
LIST_HEAD(qpnp_vadc_device_list);
static struct qpnp_vadc_scale_fn vadc_scale_fn[] = {
[SCALE_DEFAULT] = {qpnp_adc_scale_default},
@ -125,9 +127,9 @@ static struct qpnp_vadc_scale_fn vadc_scale_fn[] = {
[SCALE_QRD_BATT_THERM] = {qpnp_adc_scale_qrd_batt_therm},
};
static int32_t qpnp_vadc_read_reg(int16_t reg, u8 *data)
static int32_t qpnp_vadc_read_reg(struct qpnp_vadc_chip *vadc, int16_t reg,
u8 *data)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
int rc;
rc = spmi_ext_register_readl(vadc->adc->spmi->ctrl, vadc->adc->slave,
@ -140,9 +142,9 @@ static int32_t qpnp_vadc_read_reg(int16_t reg, u8 *data)
return 0;
}
static int32_t qpnp_vadc_write_reg(int16_t reg, u8 data)
static int32_t qpnp_vadc_write_reg(struct qpnp_vadc_chip *vadc, int16_t reg,
u8 data)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
int rc;
u8 *buf;
@ -158,24 +160,24 @@ static int32_t qpnp_vadc_write_reg(int16_t reg, u8 data)
return 0;
}
static int32_t qpnp_vadc_warm_rst_configure(void)
static int32_t qpnp_vadc_warm_rst_configure(struct qpnp_vadc_chip *vadc)
{
int rc = 0;
u8 data = 0;
rc = qpnp_vadc_write_reg(QPNP_VADC_ACCESS, QPNP_VADC_ACCESS_DATA);
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, QPNP_VADC_ACCESS_DATA);
if (rc < 0) {
pr_err("VADC write access failed\n");
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_PERH_RESET_CTL3, &data);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, &data);
if (rc < 0) {
pr_err("VADC perh reset ctl3 read failed\n");
return rc;
}
rc = qpnp_vadc_write_reg(QPNP_VADC_ACCESS, QPNP_VADC_ACCESS_DATA);
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, QPNP_VADC_ACCESS_DATA);
if (rc < 0) {
pr_err("VADC write access failed\n");
return rc;
@ -183,7 +185,7 @@ static int32_t qpnp_vadc_warm_rst_configure(void)
data |= QPNP_FOLLOW_WARM_RB;
rc = qpnp_vadc_write_reg(QPNP_VADC_PERH_RESET_CTL3, data);
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, data);
if (rc < 0) {
pr_err("VADC perh reset ctl3 write failed\n");
return rc;
@ -192,21 +194,21 @@ static int32_t qpnp_vadc_warm_rst_configure(void)
return 0;
}
static int32_t qpnp_vadc_enable(bool state)
static int32_t qpnp_vadc_enable(struct qpnp_vadc_chip *vadc, bool state)
{
int rc = 0;
u8 data = 0;
data = QPNP_VADC_ADC_EN;
if (state) {
rc = qpnp_vadc_write_reg(QPNP_VADC_EN_CTL1,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1,
data);
if (rc < 0) {
pr_err("VADC enable failed\n");
return rc;
}
} else {
rc = qpnp_vadc_write_reg(QPNP_VADC_EN_CTL1,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1,
(~data & QPNP_VADC_ADC_EN));
if (rc < 0) {
pr_err("VADC disable failed\n");
@ -217,42 +219,42 @@ static int32_t qpnp_vadc_enable(bool state)
return 0;
}
static int32_t qpnp_vadc_status_debug(void)
static int32_t qpnp_vadc_status_debug(struct qpnp_vadc_chip *vadc)
{
int rc = 0;
u8 mode = 0, status1 = 0, chan = 0, dig = 0, en = 0, status2 = 0;
rc = qpnp_vadc_read_reg(QPNP_VADC_MODE_CTL, &mode);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_MODE_CTL, &mode);
if (rc < 0) {
pr_err("mode ctl register read failed with %d\n", rc);
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_ADC_DIG_PARAM, &dig);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_ADC_DIG_PARAM, &dig);
if (rc < 0) {
pr_err("digital param read failed with %d\n", rc);
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_ADC_CH_SEL_CTL, &chan);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_ADC_CH_SEL_CTL, &chan);
if (rc < 0) {
pr_err("channel read failed with %d\n", rc);
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0) {
pr_err("status1 read failed with %d\n", rc);
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS2, &status2);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS2, &status2);
if (rc < 0) {
pr_err("status2 read failed with %d\n", rc);
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_EN_CTL1, &en);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_EN_CTL1, &en);
if (rc < 0) {
pr_err("en read failed with %d\n", rc);
return rc;
@ -261,7 +263,7 @@ static int32_t qpnp_vadc_status_debug(void)
pr_err("EOC not set - status1/2:%x/%x, dig:%x, ch:%x, mode:%x, en:%x\n",
status1, status2, dig, chan, mode, en);
rc = qpnp_vadc_enable(false);
rc = qpnp_vadc_enable(vadc, false);
if (rc < 0) {
pr_err("VADC disable failed with %d\n", rc);
return rc;
@ -269,10 +271,9 @@ static int32_t qpnp_vadc_status_debug(void)
return 0;
}
static int32_t qpnp_vadc_configure(
static int32_t qpnp_vadc_configure(struct qpnp_vadc_chip *vadc,
struct qpnp_adc_amux_properties *chan_prop)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
u8 decimation = 0, conv_sequence = 0, conv_sequence_trig = 0;
u8 mode_ctrl = 0;
int rc = 0;
@ -280,7 +281,7 @@ static int32_t qpnp_vadc_configure(
/* Mode selection */
mode_ctrl |= ((chan_prop->mode_sel << QPNP_VADC_OP_MODE_SHIFT) |
(QPNP_VADC_ADC_TRIM_EN | QPNP_VADC_AMUX_TRIM_EN));
rc = qpnp_vadc_write_reg(QPNP_VADC_MODE_CTL, mode_ctrl);
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MODE_CTL, mode_ctrl);
if (rc < 0) {
pr_err("Mode configure write error\n");
return rc;
@ -288,7 +289,7 @@ static int32_t qpnp_vadc_configure(
/* Channel selection */
rc = qpnp_vadc_write_reg(QPNP_VADC_ADC_CH_SEL_CTL,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ADC_CH_SEL_CTL,
chan_prop->amux_channel);
if (rc < 0) {
pr_err("Channel configure error\n");
@ -298,14 +299,14 @@ static int32_t qpnp_vadc_configure(
/* Digital parameter setup */
decimation = chan_prop->decimation <<
QPNP_VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT;
rc = qpnp_vadc_write_reg(QPNP_VADC_ADC_DIG_PARAM, decimation);
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ADC_DIG_PARAM, decimation);
if (rc < 0) {
pr_err("Digital parameter configure write error\n");
return rc;
}
/* HW settling time delay */
rc = qpnp_vadc_write_reg(QPNP_VADC_HW_SETTLE_DELAY,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HW_SETTLE_DELAY,
chan_prop->hw_settle_time);
if (rc < 0) {
pr_err("HW settling time setup error\n");
@ -315,7 +316,7 @@ static int32_t qpnp_vadc_configure(
if (chan_prop->mode_sel == (ADC_OP_NORMAL_MODE <<
QPNP_VADC_OP_MODE_SHIFT)) {
/* Normal measurement mode */
rc = qpnp_vadc_write_reg(QPNP_VADC_FAST_AVG_CTL,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_FAST_AVG_CTL,
chan_prop->fast_avg_setup);
if (rc < 0) {
pr_err("Fast averaging configure error\n");
@ -327,7 +328,7 @@ static int32_t qpnp_vadc_configure(
conv_sequence = ((ADC_SEQ_HOLD_100US <<
QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT) |
ADC_CONV_SEQ_TIMEOUT_5MS);
rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_SEQ_CTL,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_CTL,
conv_sequence);
if (rc < 0) {
pr_err("Conversion sequence error\n");
@ -337,7 +338,7 @@ static int32_t qpnp_vadc_configure(
conv_sequence_trig = ((QPNP_VADC_CONV_SEQ_RISING_EDGE <<
QPNP_VADC_CONV_SEQ_EDGE_SHIFT) |
chan_prop->trigger_channel);
rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_SEQ_TRIG_CTL,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_TRIG_CTL,
conv_sequence_trig);
if (rc < 0) {
pr_err("Conversion trigger error\n");
@ -347,13 +348,13 @@ static int32_t qpnp_vadc_configure(
INIT_COMPLETION(vadc->adc->adc_rslt_completion);
rc = qpnp_vadc_enable(true);
rc = qpnp_vadc_enable(vadc, true);
if (rc)
return rc;
if (!vadc->vadc_iadc_sync_lock) {
/* Request conversion */
rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_REQ,
rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_REQ,
QPNP_VADC_CONV_REQ_SET);
if (rc < 0) {
pr_err("Request conversion failed\n");
@ -364,18 +365,19 @@ static int32_t qpnp_vadc_configure(
return 0;
}
static int32_t qpnp_vadc_read_conversion_result(int32_t *data)
static int32_t qpnp_vadc_read_conversion_result(struct qpnp_vadc_chip *vadc,
int32_t *data)
{
uint8_t rslt_lsb, rslt_msb;
int rc = 0, status = 0;
status = qpnp_vadc_read_reg(QPNP_VADC_DATA0, &rslt_lsb);
status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA0, &rslt_lsb);
if (status < 0) {
pr_err("qpnp adc result read failed for data0\n");
goto fail;
}
status = qpnp_vadc_read_reg(QPNP_VADC_DATA1, &rslt_msb);
status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA1, &rslt_msb);
if (status < 0) {
pr_err("qpnp adc result read failed for data1\n");
goto fail;
@ -390,14 +392,14 @@ static int32_t qpnp_vadc_read_conversion_result(int32_t *data)
}
fail:
rc = qpnp_vadc_enable(false);
rc = qpnp_vadc_enable(vadc, false);
if (rc)
return rc;
return status;
}
static int32_t qpnp_vadc_read_status(int mode_sel)
static int32_t qpnp_vadc_read_status(struct qpnp_vadc_chip *vadc, int mode_sel)
{
u8 status1, status2, status2_conv_seq_state;
u8 status_err = QPNP_VADC_CONV_TIMEOUT_ERR;
@ -405,13 +407,13 @@ static int32_t qpnp_vadc_read_status(int mode_sel)
switch (mode_sel) {
case (ADC_OP_CONVERSION_SEQUENCER << QPNP_VADC_OP_MODE_SHIFT):
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc) {
pr_err("qpnp_vadc read mask interrupt failed\n");
return rc;
}
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS2, &status2);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS2, &status2);
if (rc) {
pr_err("qpnp_vadc read mask interrupt failed\n");
return rc;
@ -437,32 +439,45 @@ static int32_t qpnp_vadc_read_status(int mode_sel)
return 0;
}
static int qpnp_vadc_is_valid(struct qpnp_vadc_chip *vadc)
{
struct qpnp_vadc_chip *vadc_chip = NULL;
list_for_each_entry(vadc_chip, &qpnp_vadc_device_list, list)
if (vadc == vadc_chip)
return 0;
return -EINVAL;
}
static void qpnp_vadc_work(struct work_struct *work)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
struct qpnp_vadc_chip *vadc = container_of(work,
struct qpnp_vadc_chip, trigger_completion_work);
if (!vadc || !vadc->vadc_initialized)
if (qpnp_vadc_is_valid(vadc) < 0)
return;
complete(&vadc->adc->adc_rslt_completion);
return;
}
DECLARE_WORK(trigger_completion_work, qpnp_vadc_work);
static irqreturn_t qpnp_vadc_isr(int irq, void *dev_id)
{
schedule_work(&trigger_completion_work);
struct qpnp_vadc_chip *vadc = dev_id;
schedule_work(&vadc->trigger_completion_work);
return IRQ_HANDLED;
}
static int32_t qpnp_vadc_version_check(void)
static int32_t qpnp_vadc_version_check(struct qpnp_vadc_chip *dev)
{
uint8_t revision;
int rc;
rc = qpnp_vadc_read_reg(QPNP_VADC_REVISION2, &revision);
rc = qpnp_vadc_read_reg(dev, QPNP_VADC_REVISION2, &revision);
if (rc < 0) {
pr_err("qpnp adc result read failed with %d\n", rc);
return rc;
@ -510,13 +525,17 @@ static int32_t qpnp_vbat_sns_comp(int64_t *result, u8 id, int64_t die_temp)
return 0;
}
int32_t qpnp_vbat_sns_comp_result(int64_t *result)
int32_t qpnp_vbat_sns_comp_result(struct qpnp_vadc_chip *vadc,
int64_t *result)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
struct qpnp_vadc_result die_temp_result;
int rc = 0;
rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
rc = qpnp_vadc_is_valid(vadc);
if (rc < 0)
return rc;
rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE,
DIE_TEMP, &die_temp_result);
if (rc < 0) {
pr_err("Error reading die_temp\n");
@ -532,9 +551,9 @@ int32_t qpnp_vbat_sns_comp_result(int64_t *result)
}
EXPORT_SYMBOL(qpnp_vbat_sns_comp_result);
static void qpnp_vadc_625mv_channel_sel(uint32_t *ref_channel_sel)
static void qpnp_vadc_625mv_channel_sel(struct qpnp_vadc_chip *vadc,
uint32_t *ref_channel_sel)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
uint32_t dt_index = 0;
/* Check if the buffered 625mV channel exists */
@ -551,9 +570,8 @@ static void qpnp_vadc_625mv_channel_sel(uint32_t *ref_channel_sel)
}
}
static int32_t qpnp_vadc_calib_device(void)
static int32_t qpnp_vadc_calib_device(struct qpnp_vadc_chip *vadc)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
struct qpnp_adc_amux_properties conv;
int rc, calib_read_1, calib_read_2, count = 0;
u8 status1 = 0;
@ -565,14 +583,14 @@ static int32_t qpnp_vadc_calib_device(void)
conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US;
conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1;
rc = qpnp_vadc_configure(&conv);
rc = qpnp_vadc_configure(vadc, &conv);
if (rc) {
pr_err("qpnp_vadc configure failed with %d\n", rc);
goto calib_fail;
}
while (status1 != QPNP_VADC_STATUS1_EOC) {
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0)
return rc;
status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK;
@ -585,19 +603,19 @@ static int32_t qpnp_vadc_calib_device(void)
}
}
rc = qpnp_vadc_read_conversion_result(&calib_read_1);
rc = qpnp_vadc_read_conversion_result(vadc, &calib_read_1);
if (rc) {
pr_err("qpnp adc read adc failed with %d\n", rc);
goto calib_fail;
}
qpnp_vadc_625mv_channel_sel(&ref_channel_sel);
qpnp_vadc_625mv_channel_sel(vadc, &ref_channel_sel);
conv.amux_channel = ref_channel_sel;
conv.decimation = DECIMATION_TYPE2;
conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT;
conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US;
conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1;
rc = qpnp_vadc_configure(&conv);
rc = qpnp_vadc_configure(vadc, &conv);
if (rc) {
pr_err("qpnp adc configure failed with %d\n", rc);
goto calib_fail;
@ -606,7 +624,7 @@ static int32_t qpnp_vadc_calib_device(void)
status1 = 0;
count = 0;
while (status1 != QPNP_VADC_STATUS1_EOC) {
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0)
return rc;
status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK;
@ -619,7 +637,7 @@ static int32_t qpnp_vadc_calib_device(void)
}
}
rc = qpnp_vadc_read_conversion_result(&calib_read_2);
rc = qpnp_vadc_read_conversion_result(vadc, &calib_read_2);
if (rc) {
pr_err("qpnp adc read adc failed with %d\n", rc);
goto calib_fail;
@ -643,7 +661,7 @@ static int32_t qpnp_vadc_calib_device(void)
conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT;
conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US;
conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1;
rc = qpnp_vadc_configure(&conv);
rc = qpnp_vadc_configure(vadc, &conv);
if (rc) {
pr_err("qpnp adc configure failed with %d\n", rc);
goto calib_fail;
@ -652,7 +670,7 @@ static int32_t qpnp_vadc_calib_device(void)
status1 = 0;
count = 0;
while (status1 != QPNP_VADC_STATUS1_EOC) {
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0)
return rc;
status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK;
@ -665,7 +683,7 @@ static int32_t qpnp_vadc_calib_device(void)
}
}
rc = qpnp_vadc_read_conversion_result(&calib_read_1);
rc = qpnp_vadc_read_conversion_result(vadc, &calib_read_1);
if (rc) {
pr_err("qpnp adc read adc failed with %d\n", rc);
goto calib_fail;
@ -676,7 +694,7 @@ static int32_t qpnp_vadc_calib_device(void)
conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT;
conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US;
conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1;
rc = qpnp_vadc_configure(&conv);
rc = qpnp_vadc_configure(vadc, &conv);
if (rc) {
pr_err("qpnp adc configure failed with %d\n", rc);
goto calib_fail;
@ -685,7 +703,7 @@ static int32_t qpnp_vadc_calib_device(void)
status1 = 0;
count = 0;
while (status1 != QPNP_VADC_STATUS1_EOC) {
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0)
return rc;
status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK;
@ -698,7 +716,7 @@ static int32_t qpnp_vadc_calib_device(void)
}
}
rc = qpnp_vadc_read_conversion_result(&calib_read_2);
rc = qpnp_vadc_read_conversion_result(vadc, &calib_read_2);
if (rc) {
pr_err("qpnp adc read adc failed with %d\n", rc);
goto calib_fail;
@ -719,11 +737,15 @@ calib_fail:
return rc;
}
int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_linear_graph *param,
int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_chip *vadc,
struct qpnp_vadc_linear_graph *param,
enum qpnp_adc_calib_type calib_type)
{
int rc = 0;
struct qpnp_vadc_drv *vadc = qpnp_vadc;
rc = qpnp_vadc_is_valid(vadc);
if (rc < 0)
return rc;
switch (calib_type) {
case CALIB_RATIOMETRIC:
@ -752,36 +774,44 @@ int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_linear_graph *param,
}
EXPORT_SYMBOL(qpnp_get_vadc_gain_and_offset);
int32_t qpnp_vadc_is_ready(void)
struct qpnp_vadc_chip *qpnp_get_vadc(struct device *dev, const char *name)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
struct qpnp_vadc_chip *vadc;
struct device_node *node = NULL;
char prop_name[QPNP_MAX_PROP_NAME_LEN];
if (!vadc || !vadc->vadc_initialized)
return -EPROBE_DEFER;
else
return 0;
snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-vadc", name);
node = of_parse_phandle(dev->of_node, prop_name, 0);
if (node == NULL)
return ERR_PTR(-ENODEV);
list_for_each_entry(vadc, &qpnp_vadc_device_list, list)
if (vadc->adc->spmi->dev.of_node == node)
return vadc;
return ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL(qpnp_vadc_is_ready);
EXPORT_SYMBOL(qpnp_get_vadc);
int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
int32_t qpnp_vadc_conv_seq_request(struct qpnp_vadc_chip *vadc,
enum qpnp_vadc_trigger trigger_channel,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
int rc = 0, scale_type, amux_prescaling, dt_index = 0;
uint32_t ref_channel;
if (!vadc || !vadc->vadc_initialized)
if (qpnp_vadc_is_valid(vadc))
return -EPROBE_DEFER;
mutex_lock(&vadc->adc->adc_lock);
if (!vadc->vadc_init_calib) {
rc = qpnp_vadc_version_check();
rc = qpnp_vadc_version_check(vadc);
if (rc)
goto fail_unlock;
rc = qpnp_vadc_calib_device();
rc = qpnp_vadc_calib_device(vadc);
if (rc) {
pr_err("Calibration failed\n");
goto fail_unlock;
@ -790,7 +820,7 @@ int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
}
if (channel == REF_625MV) {
qpnp_vadc_625mv_channel_sel(&ref_channel);
qpnp_vadc_625mv_channel_sel(vadc, &ref_channel);
channel = ref_channel;
}
@ -826,7 +856,7 @@ int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
vadc->adc->amux_prop->trigger_channel = trigger_channel;
rc = qpnp_vadc_configure(vadc->adc->amux_prop);
rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop);
if (rc) {
pr_err("qpnp vadc configure failed with %d\n", rc);
goto fail_unlock;
@ -836,14 +866,14 @@ int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
QPNP_ADC_COMPLETION_TIMEOUT);
if (!rc) {
u8 status1 = 0;
rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1);
if (rc < 0)
goto fail_unlock;
status1 &= (QPNP_VADC_STATUS1_REQ_STS | QPNP_VADC_STATUS1_EOC);
if (status1 == QPNP_VADC_STATUS1_EOC)
pr_debug("End of conversion status set\n");
else {
rc = qpnp_vadc_status_debug();
rc = qpnp_vadc_status_debug(vadc);
if (rc < 0)
pr_err("VADC disable failed\n");
rc = -EINVAL;
@ -852,12 +882,13 @@ int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
}
if (trigger_channel < ADC_SEQ_NONE) {
rc = qpnp_vadc_read_status(vadc->adc->amux_prop->mode_sel);
rc = qpnp_vadc_read_status(vadc,
vadc->adc->amux_prop->mode_sel);
if (rc)
pr_debug("Conversion sequence timed out - %d\n", rc);
}
rc = qpnp_vadc_read_conversion_result(&result->adc_code);
rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code);
if (rc) {
pr_err("qpnp vadc read adc code failed with %d\n", rc);
goto fail_unlock;
@ -882,7 +913,7 @@ int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel,
goto fail_unlock;
}
vadc_scale_fn[scale_type].chan(result->adc_code,
vadc_scale_fn[scale_type].chan(vadc, result->adc_code,
vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result);
fail_unlock:
@ -892,23 +923,22 @@ fail_unlock:
}
EXPORT_SYMBOL(qpnp_vadc_conv_seq_request);
int32_t qpnp_vadc_read(enum qpnp_vadc_channels channel,
int32_t qpnp_vadc_read(struct qpnp_vadc_chip *vadc,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
enum qpnp_vadc_channels;
struct qpnp_vadc_result die_temp_result;
int rc = 0;
if (channel == VBAT_SNS) {
rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE,
channel, result);
if (rc < 0) {
pr_err("Error reading vbatt\n");
return rc;
}
rc = qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE,
DIE_TEMP, &die_temp_result);
if (rc < 0) {
pr_err("Error reading die_temp\n");
@ -922,41 +952,37 @@ int32_t qpnp_vadc_read(enum qpnp_vadc_channels channel,
return 0;
} else
return qpnp_vadc_conv_seq_request(ADC_SEQ_NONE,
return qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE,
channel, result);
}
EXPORT_SYMBOL(qpnp_vadc_read);
static void qpnp_vadc_lock(void)
static void qpnp_vadc_lock(struct qpnp_vadc_chip *vadc)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
mutex_lock(&vadc->adc->adc_lock);
}
static void qpnp_vadc_unlock(void)
static void qpnp_vadc_unlock(struct qpnp_vadc_chip *vadc)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
mutex_unlock(&vadc->adc->adc_lock);
}
int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel)
int32_t qpnp_vadc_iadc_sync_request(struct qpnp_vadc_chip *vadc,
enum qpnp_vadc_channels channel)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
int rc = 0, dt_index = 0;
if (!vadc || !vadc->vadc_initialized)
if (qpnp_vadc_is_valid(vadc))
return -EPROBE_DEFER;
qpnp_vadc_lock();
qpnp_vadc_lock(vadc);
if (!vadc->vadc_init_calib) {
rc = qpnp_vadc_version_check();
rc = qpnp_vadc_version_check(vadc);
if (rc)
goto fail;
rc = qpnp_vadc_calib_device();
rc = qpnp_vadc_calib_device(vadc);
if (rc) {
pr_err("Calibration failed\n");
goto fail;
@ -986,7 +1012,7 @@ int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel)
<< QPNP_VADC_OP_MODE_SHIFT);
vadc->vadc_iadc_sync_lock = true;
rc = qpnp_vadc_configure(vadc->adc->amux_prop);
rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop);
if (rc) {
pr_err("qpnp vadc configure failed with %d\n", rc);
goto fail;
@ -995,15 +1021,15 @@ int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel)
return rc;
fail:
vadc->vadc_iadc_sync_lock = false;
qpnp_vadc_unlock();
qpnp_vadc_unlock(vadc);
return rc;
}
EXPORT_SYMBOL(qpnp_vadc_iadc_sync_request);
int32_t qpnp_vadc_iadc_sync_complete_request(enum qpnp_vadc_channels channel,
int32_t qpnp_vadc_iadc_sync_complete_request(struct qpnp_vadc_chip *vadc,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
int rc = 0, scale_type, amux_prescaling, dt_index = 0;
vadc->adc->amux_prop->amux_channel = channel;
@ -1012,7 +1038,7 @@ int32_t qpnp_vadc_iadc_sync_complete_request(enum qpnp_vadc_channels channel,
!= channel) && (dt_index < vadc->max_channels_available))
dt_index++;
rc = qpnp_vadc_read_conversion_result(&result->adc_code);
rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code);
if (rc) {
pr_err("qpnp vadc read adc code failed with %d\n", rc);
goto fail;
@ -1037,12 +1063,12 @@ int32_t qpnp_vadc_iadc_sync_complete_request(enum qpnp_vadc_channels channel,
goto fail;
}
vadc_scale_fn[scale_type].chan(result->adc_code,
vadc_scale_fn[scale_type].chan(vadc, result->adc_code,
vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result);
fail:
vadc->vadc_iadc_sync_lock = false;
qpnp_vadc_unlock();
qpnp_vadc_unlock(vadc);
return rc;
}
EXPORT_SYMBOL(qpnp_vadc_iadc_sync_complete_request);
@ -1051,10 +1077,11 @@ static ssize_t qpnp_adc_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct qpnp_vadc_chip *vadc = dev_get_drvdata(dev);
struct qpnp_vadc_result result;
int rc = -1;
rc = qpnp_vadc_read(attr->index, &result);
rc = qpnp_vadc_read(vadc, attr->index, &result);
if (rc) {
pr_err("VADC read error with %d\n", rc);
@ -1068,9 +1095,9 @@ static ssize_t qpnp_adc_show(struct device *dev,
static struct sensor_device_attribute qpnp_adc_attr =
SENSOR_ATTR(NULL, S_IRUGO, qpnp_adc_show, NULL, 0);
static int32_t qpnp_vadc_init_hwmon(struct spmi_device *spmi)
static int32_t qpnp_vadc_init_hwmon(struct qpnp_vadc_chip *vadc,
struct spmi_device *spmi)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
struct device_node *child;
struct device_node *node = spmi->dev.of_node;
int rc = 0, i = 0, channel;
@ -1102,21 +1129,13 @@ hwmon_err_sens:
static int qpnp_vadc_probe(struct spmi_device *spmi)
{
struct qpnp_vadc_drv *vadc;
struct qpnp_vadc_chip *vadc;
struct qpnp_adc_drv *adc_qpnp;
struct device_node *node = spmi->dev.of_node;
struct device_node *child;
int rc, count_adc_channel_list = 0;
int rc, count_adc_channel_list = 0, i = 0;
u8 fab_id = 0;
if (!node)
return -EINVAL;
if (qpnp_vadc) {
pr_err("VADC already in use\n");
return -EBUSY;
}
for_each_child_of_node(node, child)
count_adc_channel_list++;
@ -1125,7 +1144,7 @@ static int qpnp_vadc_probe(struct spmi_device *spmi)
return -EINVAL;
}
vadc = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_vadc_drv) +
vadc = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_vadc_chip) +
(sizeof(struct sensor_device_attribute) *
count_adc_channel_list), GFP_KERNEL);
if (!vadc) {
@ -1133,20 +1152,19 @@ static int qpnp_vadc_probe(struct spmi_device *spmi)
return -ENOMEM;
}
vadc->dev = &(spmi->dev);
adc_qpnp = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_adc_drv),
GFP_KERNEL);
if (!adc_qpnp) {
dev_err(&spmi->dev, "Unable to allocate memory\n");
rc = -ENOMEM;
goto fail;
return -ENOMEM;
}
vadc->adc = adc_qpnp;
rc = qpnp_adc_get_devicetree_data(spmi, vadc->adc);
if (rc) {
dev_err(&spmi->dev, "failed to read device tree\n");
goto fail;
return rc;
}
mutex_init(&vadc->adc->adc_lock);
@ -1156,46 +1174,54 @@ static int qpnp_vadc_probe(struct spmi_device *spmi)
if (rc) {
dev_err(&spmi->dev,
"failed to request adc irq with error %d\n", rc);
goto fail;
return rc;
} else {
enable_irq_wake(vadc->adc->adc_irq_eoc);
}
qpnp_vadc = vadc;
dev_set_drvdata(&spmi->dev, vadc);
rc = qpnp_vadc_init_hwmon(spmi);
rc = qpnp_vadc_init_hwmon(vadc, spmi);
if (rc) {
dev_err(&spmi->dev, "failed to initialize qpnp hwmon adc\n");
goto fail;
return rc;
}
vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->spmi->dev);
vadc->vadc_init_calib = false;
vadc->max_channels_available = count_adc_channel_list;
rc = qpnp_vadc_read_reg(QPNP_INT_TEST_VAL, &fab_id);
rc = qpnp_vadc_read_reg(vadc, QPNP_INT_TEST_VAL, &fab_id);
if (rc < 0) {
pr_err("qpnp adc comp id failed with %d\n", rc);
goto fail;
goto err_setup;
}
vadc->id = fab_id;
rc = qpnp_vadc_warm_rst_configure();
rc = qpnp_vadc_warm_rst_configure(vadc);
if (rc < 0) {
pr_err("Setting perp reset on warm reset failed %d\n", rc);
goto fail;
goto err_setup;
}
vadc->vadc_initialized = true;
INIT_WORK(&vadc->trigger_completion_work, qpnp_vadc_work);
vadc->vadc_iadc_sync_lock = false;
dev_set_drvdata(&spmi->dev, vadc);
list_add(&vadc->list, &qpnp_vadc_device_list);
return 0;
fail:
qpnp_vadc = NULL;
err_setup:
for_each_child_of_node(node, child) {
device_remove_file(&spmi->dev,
&vadc->sens_attr[i].dev_attr);
i++;
}
hwmon_device_unregister(vadc->vadc_hwmon);
return rc;
}
static int qpnp_vadc_remove(struct spmi_device *spmi)
{
struct qpnp_vadc_drv *vadc = dev_get_drvdata(&spmi->dev);
struct qpnp_vadc_chip *vadc = dev_get_drvdata(&spmi->dev);
struct device_node *node = spmi->dev.of_node;
struct device_node *child;
int i = 0;
@ -1205,7 +1231,8 @@ static int qpnp_vadc_remove(struct spmi_device *spmi)
&vadc->sens_attr[i].dev_attr);
i++;
}
vadc->vadc_initialized = false;
hwmon_device_unregister(vadc->vadc_hwmon);
list_del(&vadc->list);
dev_set_drvdata(&spmi->dev, NULL);
return 0;

49
drivers/power/qpnp-bms.c
View File

@ -276,6 +276,7 @@ struct qpnp_bms_chip {
bool battery_removed;
struct bms_irq sw_cc_thr_irq;
struct bms_irq ocv_thr_irq;
struct qpnp_vadc_chip *vadc_dev;
};
static struct of_device_id qpnp_bms_match_table[] = {
@ -481,7 +482,7 @@ static inline int convert_vbatt_raw_to_uv(struct qpnp_bms_chip *chip,
pr_debug("%u raw converted into %lld uv\n", reading, uv);
uv = adjust_vbatt_reading(chip, uv);
pr_debug("adjusted into %lld uv\n", uv);
rc = qpnp_vbat_sns_comp_result(&uv);
rc = qpnp_vbat_sns_comp_result(chip->vadc_dev, &uv);
if (rc)
pr_debug("could not compensate vbatt\n");
pr_debug("compensated into %lld uv\n", uv);
@ -596,12 +597,12 @@ static int get_battery_current(struct qpnp_bms_chip *chip, int *result_ua)
return 0;
}
static int get_battery_voltage(int *result_uv)
static int get_battery_voltage(struct qpnp_bms_chip *chip, int *result_uv)
{
int rc;
struct qpnp_vadc_result adc_result;
rc = qpnp_vadc_read(VBAT_SNS, &adc_result);
rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &adc_result);
if (rc) {
pr_err("error reading adc channel = %d, rc = %d\n",
VBAT_SNS, rc);
@ -655,14 +656,14 @@ static int calib_vadc(struct qpnp_bms_chip *chip)
int rc, raw_0625, raw_1250;
struct qpnp_vadc_result result;
rc = qpnp_vadc_read(REF_625MV, &result);
rc = qpnp_vadc_read(chip->vadc_dev, REF_625MV, &result);
if (rc) {
pr_debug("vadc read failed with rc = %d\n", rc);
return rc;
}
raw_0625 = result.adc_code;
rc = qpnp_vadc_read(REF_125V, &result);
rc = qpnp_vadc_read(chip->vadc_dev, REF_125V, &result);
if (rc) {
pr_debug("vadc read failed with rc = %d\n", rc);
return rc;
@ -807,7 +808,7 @@ static int get_simultaneous_batt_v_and_i(struct qpnp_bms_chip *chip,
pr_err("bms current read failed with rc: %d\n", rc);
return rc;
}
rc = qpnp_vadc_read(VBAT_SNS, &v_result);
rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &v_result);
if (rc) {
pr_err("vadc read failed with rc: %d\n", rc);
return rc;
@ -1049,7 +1050,7 @@ static int calculate_cc(struct qpnp_bms_chip *chip, int64_t cc,
software_counter = cc_type == SHDW_CC ?
&chip->software_shdw_cc_uah : &chip->software_cc_uah;
rc = qpnp_vadc_read(DIE_TEMP, &result);
rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result);
if (rc) {
pr_err("could not read pmic die temperature: %d\n", rc);
return *software_counter;
@ -1430,7 +1431,7 @@ static int get_prop_bms_charge_full(struct qpnp_bms_chip *chip)
int rc;
struct qpnp_vadc_result result;
rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result);
if (rc) {
pr_err("Unable to read battery temperature\n");
return rc;
@ -1689,7 +1690,7 @@ static int report_cc_based_soc(struct qpnp_bms_chip *chip)
int rc;
bool charging, charging_since_last_report;
rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result);
if (rc) {
pr_err("error reading adc channel = %d, rc = %d\n",
@ -2059,7 +2060,7 @@ static int clamp_soc_based_on_voltage(struct qpnp_bms_chip *chip, int soc)
{
int rc, vbat_uv;
rc = get_battery_voltage(&vbat_uv);
rc = get_battery_voltage(chip, &vbat_uv);
if (rc < 0) {
pr_err("adc vbat failed err = %d\n", rc);
return soc;
@ -2318,7 +2319,7 @@ static int calculate_soc_from_voltage(struct qpnp_bms_chip *chip)
int voltage_range_uv, voltage_remaining_uv, voltage_based_soc;
int rc, vbat_uv;
rc = get_battery_voltage(&vbat_uv);
rc = get_battery_voltage(chip, &vbat_uv);
if (rc < 0) {
pr_err("adc vbat failed err = %d\n", rc);
return rc;
@ -2358,7 +2359,8 @@ static int recalculate_soc(struct qpnp_bms_chip *chip)
} else {
if (!chip->batfet_closed)
qpnp_iadc_calibrate_for_trim(true);
rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM,
&result);
if (rc) {
pr_err("error reading vadc LR_MUX1_BATT_THERM = %d, rc = %d\n",
LR_MUX1_BATT_THERM, rc);
@ -2511,10 +2513,10 @@ static void btm_notify_vbat(enum qpnp_tm_state state, void *ctx)
struct qpnp_vadc_result result;
int rc;
rc = qpnp_vadc_read(VBAT_SNS, &result);
rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &result);
pr_debug("vbat = %lld, raw = 0x%x\n", result.physical, result.adc_code);
get_battery_voltage(&vbat_uv);
get_battery_voltage(chip, &vbat_uv);
pr_debug("vbat is at %d, state is at %d\n", vbat_uv, state);
if (state == ADC_TM_LOW_STATE) {
@ -2892,7 +2894,7 @@ static void fcc_learning_config(struct qpnp_bms_chip *chip, bool start)
struct qpnp_vadc_result result;
int fcc_uah, new_fcc_uah, delta_cc_uah, delta_soc;
rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result);
if (rc) {
pr_err("Unable to read batt_temp\n");
return;
@ -3291,7 +3293,7 @@ static int64_t read_battery_id(struct qpnp_bms_chip *chip)
int rc;
struct qpnp_vadc_result result;
rc = qpnp_vadc_read(LR_MUX2_BAT_ID, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX2_BAT_ID, &result);
if (rc) {
pr_err("error reading batt id channel = %d, rc = %d\n",
LR_MUX2_BAT_ID, rc);
@ -3726,7 +3728,7 @@ static int refresh_die_temp_monitor(struct qpnp_bms_chip *chip)
struct qpnp_vadc_result result;
int rc;
rc = qpnp_vadc_read(DIE_TEMP, &result);
rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result);
pr_debug("low = %lld, high = %lld\n",
result.physical - chip->temperature_margin,
@ -3746,7 +3748,7 @@ static void btm_notify_die_temp(enum qpnp_tm_state state, void *ctx)
struct qpnp_vadc_result result;
int rc;
rc = qpnp_vadc_read(DIE_TEMP, &result);
rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result);
if (state == ADC_TM_LOW_STATE)
pr_debug("low state triggered\n");
@ -3792,10 +3794,11 @@ static int qpnp_bms_probe(struct spmi_device *spmi)
return -ENOMEM;
}
rc = qpnp_vadc_is_ready();
if (rc) {
pr_info("vadc not ready: %d, deferring probe\n", rc);
rc = -EPROBE_DEFER;
chip->vadc_dev = qpnp_get_vadc(&(spmi->dev), "bms");
if (IS_ERR(chip->vadc_dev)) {
rc = PTR_ERR(chip->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("vadc property missing, rc=%d\n", rc);
goto error_read;
}
@ -3956,7 +3959,7 @@ static int qpnp_bms_probe(struct spmi_device *spmi)
chip->bms_psy_registered = true;
vbatt = 0;
rc = get_battery_voltage(&vbatt);
rc = get_battery_voltage(chip, &vbatt);
if (rc) {
pr_err("error reading vbat_sns adc channel = %d, rc = %d\n",
VBAT_SNS, rc);

17
drivers/power/qpnp-charger.c
View File

@ -328,6 +328,7 @@ struct qpnp_chg_chip {
struct wake_lock eoc_wake_lock;
struct qpnp_chg_regulator otg_vreg;
struct qpnp_chg_regulator boost_vreg;
struct qpnp_vadc_chip *vadc_dev;
};
@ -1331,7 +1332,7 @@ get_prop_battery_voltage_now(struct qpnp_chg_chip *chip)
pr_err("vbat reading not supported for 1.0 rc=%d\n", rc);
return 0;
} else {
rc = qpnp_vadc_read(VBAT_SNS, &results);
rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &results);
if (rc) {
pr_err("Unable to read vbat rc=%d\n", rc);
return 0;
@ -1524,7 +1525,7 @@ get_prop_batt_temp(struct qpnp_chg_chip *chip)
if (chip->use_default_batt_values || !get_prop_batt_present(chip))
return DEFAULT_TEMP;
rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &results);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &results);
if (rc) {
pr_debug("Unable to read batt temperature rc=%d\n", rc);
return 0;
@ -2672,7 +2673,7 @@ qpnp_chg_load_battery_data(struct qpnp_chg_chip *chip)
"qcom,battery-data");
if (node) {
memset(&batt_data, 0, sizeof(struct bms_battery_data));
rc = qpnp_vadc_read(LR_MUX2_BAT_ID, &result);
rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX2_BAT_ID, &result);
if (rc) {
pr_err("error reading batt id channel = %d, rc = %d\n",
LR_MUX2_BAT_ID, rc);
@ -3140,14 +3141,18 @@ qpnp_charger_probe(struct spmi_device *spmi)
if (subtype == SMBB_BAT_IF_SUBTYPE ||
subtype == SMBBP_BAT_IF_SUBTYPE ||
subtype == SMBCL_BAT_IF_SUBTYPE){
rc = qpnp_vadc_is_ready();
if (rc)
subtype == SMBCL_BAT_IF_SUBTYPE) {
chip->vadc_dev = qpnp_get_vadc(chip->dev, "chg");
if (IS_ERR(chip->vadc_dev)) {
rc = PTR_ERR(chip->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("vadc property missing\n");
goto fail_chg_enable;
rc = qpnp_chg_load_battery_data(chip);
if (rc)
goto fail_chg_enable;
}
}
}

20
drivers/thermal/qpnp-adc-tm.c
View File

@ -191,6 +191,7 @@ struct qpnp_adc_tm_drv {
struct qpnp_adc_drv *adc;
bool adc_tm_initialized;
int max_channels_available;
struct qpnp_vadc_chip *vadc_dev;
struct qpnp_adc_tm_sensor sensor[0];
};
@ -873,7 +874,8 @@ static int qpnp_adc_tm_get_trip_temp(struct thermal_zone_device *thermal,
return -EINVAL;
}
rc = qpnp_adc_tm_scale_voltage_therm_pu2(reg, &result);
rc = qpnp_adc_tm_scale_voltage_therm_pu2(adc_tm->vadc_dev, reg,
&result);
if (rc < 0) {
pr_err("Failed to lookup the therm thresholds\n");
return rc;
@ -913,7 +915,7 @@ static int qpnp_adc_tm_set_trip_temp(struct thermal_zone_device *thermal,
pr_debug("requested a high - %d and low - %d with trip - %d\n",
tm_config.high_thr_temp, tm_config.low_thr_temp, trip);
rc = qpnp_adc_tm_scale_therm_voltage_pu2(&tm_config);
rc = qpnp_adc_tm_scale_therm_voltage_pu2(adc_tm->vadc_dev, &tm_config);
if (rc < 0) {
pr_err("Failed to lookup the adc-tm thresholds\n");
return rc;
@ -1282,10 +1284,12 @@ static int qpnp_adc_read_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
{
struct qpnp_adc_tm_sensor *adc_tm_sensor = thermal->devdata;
struct qpnp_adc_tm_drv *adc_tm = qpnp_adc_tm;
struct qpnp_vadc_result result;
int rc = 0;
rc = qpnp_vadc_read(adc_tm_sensor->vadc_channel_num, &result);
rc = qpnp_vadc_read(adc_tm->vadc_dev,
adc_tm_sensor->vadc_channel_num, &result);
if (rc)
return rc;
@ -1362,7 +1366,7 @@ int32_t qpnp_adc_tm_channel_measure(struct qpnp_adc_tm_btm_param *param)
ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
adc_tm->adc->amux_prop->chan_prop->meas_interval1 =
ADC_MEAS1_INTERVAL_1S;
adc_tm_rscale_fn[scale_type].chan(param,
adc_tm_rscale_fn[scale_type].chan(adc_tm->vadc_dev, param,
&adc_tm->adc->amux_prop->chan_prop->low_thr,
&adc_tm->adc->amux_prop->chan_prop->high_thr);
adc_tm->adc->amux_prop->chan_prop->tm_channel_select =
@ -1553,6 +1557,14 @@ static int qpnp_adc_tm_probe(struct spmi_device *spmi)
goto fail;
}
adc_tm->vadc_dev = qpnp_get_vadc(&spmi->dev, "adc_tm");
if (IS_ERR(adc_tm->vadc_dev)) {
rc = PTR_ERR(adc_tm->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("vadc property missing, rc=%d\n", rc);
goto fail;
}
rc = devm_request_irq(&spmi->dev, adc_tm->adc->adc_irq_eoc,
qpnp_adc_tm_isr, IRQF_TRIGGER_RISING,
"qpnp_adc_tm_interrupt", adc_tm);

14
drivers/thermal/qpnp-temp-alarm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -93,6 +93,7 @@ struct qpnp_tm_chip {
enum qpnp_vadc_channels adc_channel;
u16 base_addr;
bool allow_software_override;
struct qpnp_vadc_chip *vadc_dev;
};
/* Delay between TEMP_STAT IRQ going high and status value changing in ms. */
@ -160,7 +161,7 @@ static int qpnp_tm_update_temp(struct qpnp_tm_chip *chip)
struct qpnp_vadc_result adc_result;
int rc;
rc = qpnp_vadc_read(chip->adc_channel, &adc_result);
rc = qpnp_vadc_read(chip->vadc_dev, chip->adc_channel, &adc_result);
if (!rc)
chip->temperature = adc_result.physical;
else
@ -543,9 +544,12 @@ static int qpnp_tm_probe(struct spmi_device *spmi)
__func__, chip->adc_channel);
} else {
chip->adc_type = QPNP_TM_ADC_QPNP_ADC;
rc = qpnp_vadc_is_ready();
if (rc) {
/* Probe retry, do not print an error message */
chip->vadc_dev = qpnp_get_vadc(&spmi->dev,
"temp_alarm");
if (IS_ERR(chip->vadc_dev)) {
rc = PTR_ERR(chip->vadc_dev);
if (rc != -EPROBE_DEFER)
pr_err("vadc property missing\n");
goto err_cancel_work;
}
}

148
include/linux/qpnp/qpnp-adc.h
View File

@ -138,6 +138,10 @@ enum qpnp_iadc_channels {
#define QPNP_ADC_625_UV 625000
#define QPNP_ADC_HWMON_NAME_LENGTH 64
#define QPNP_MAX_PROP_NAME_LEN 32
/* Structure device for qpnp vadc */
struct qpnp_vadc_chip;
/**
* enum qpnp_adc_decimation_type - Sampling rate supported.
@ -895,7 +899,7 @@ static const struct qpnp_vadc_scaling_ratio qpnp_vadc_amux_scaling_ratio[] = {
* and returns the physical result
*/
struct qpnp_vadc_scale_fn {
int32_t (*chan) (int32_t,
int32_t (*chan) (struct qpnp_vadc_chip *, int32_t,
const struct qpnp_adc_properties *,
const struct qpnp_vadc_chan_properties *,
struct qpnp_vadc_result *);
@ -908,7 +912,8 @@ struct qpnp_vadc_scale_fn {
* and returns the physical result
*/
struct qpnp_adc_tm_reverse_scale_fn {
int32_t (*chan) (struct qpnp_adc_tm_btm_param *,
int32_t (*chan) (struct qpnp_vadc_chip *,
struct qpnp_adc_tm_btm_param *,
uint32_t *, uint32_t *);
};
@ -1006,21 +1011,24 @@ struct qpnp_adc_amux_properties {
|| defined(CONFIG_SENSORS_QPNP_ADC_VOLTAGE_MODULE)
/**
* qpnp_vadc_read() - Performs ADC read on the channel.
* @dev: Structure device for qpnp vadc
* @channel: Input channel to perform the ADC read.
* @result: Structure pointer of type adc_chan_result
* in which the ADC read results are stored.
*/
int32_t qpnp_vadc_read(enum qpnp_vadc_channels channel,
int32_t qpnp_vadc_read(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result);
/**
* qpnp_vadc_conv_seq_request() - Performs ADC read on the conversion
* sequencer channel.
* @dev: Structure device for qpnp vadc
* @channel: Input channel to perform the ADC read.
* @result: Structure pointer of type adc_chan_result
* in which the ADC read results are stored.
*/
int32_t qpnp_vadc_conv_seq_request(
int32_t qpnp_vadc_conv_seq_request(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_trigger trigger_channel,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result);
@ -1043,6 +1051,7 @@ int32_t qpnp_adc_get_devicetree_data(struct spmi_device *spmi,
* qpnp_adc_scale_default() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the qpnp adc such as bit resolution,
* reference voltage.
@ -1050,7 +1059,8 @@ int32_t qpnp_adc_get_devicetree_data(struct spmi_device *spmi,
* slope and offset.
* @chan_rslt: Physical result to be stored.
*/
int32_t qpnp_adc_scale_default(int32_t adc_code,
int32_t qpnp_adc_scale_default(struct qpnp_vadc_chip *dev,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1059,6 +1069,7 @@ int32_t qpnp_adc_scale_default(int32_t adc_code,
* of an ADC to the ADC reference and compensates for the
* gain and offset. Performs the AMUX out as 2mV/K and returns
* the temperature in milli degC.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the qpnp adc such as bit resolution,
* reference voltage.
@ -1066,7 +1077,8 @@ int32_t qpnp_adc_scale_default(int32_t adc_code,
* slope and offset.
* @chan_rslt: Physical result to be stored.
*/
int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
int32_t qpnp_adc_scale_pmic_therm(struct qpnp_vadc_chip *dev,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1074,6 +1086,7 @@ int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
* qpnp_adc_scale_batt_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature in decidegC.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1081,7 +1094,8 @@ int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
int32_t qpnp_adc_scale_batt_therm(struct qpnp_vadc_chip *dev,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1089,6 +1103,7 @@ int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
* qpnp_adc_scale_qrd_batt_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature in decidegC.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1096,7 +1111,8 @@ int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
int32_t qpnp_adc_scale_qrd_batt_therm(struct qpnp_vadc_chip *dev,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1104,6 +1120,7 @@ int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
* qpnp_adc_scale_batt_id() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1111,7 +1128,7 @@ int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
int32_t qpnp_adc_scale_batt_id(struct qpnp_vadc_chip *dev, int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1120,6 +1137,7 @@ int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature of the xo therm in mili
degC.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1127,7 +1145,7 @@ int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
int32_t qpnp_adc_tdkntcg_therm(struct qpnp_vadc_chip *dev, int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1137,6 +1155,7 @@ int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
* gain and offset. Returns the temperature of the therm in degC.
* It uses a mapping table computed for a 150K pull-up.
* Pull-up1 is an internal pull-up on the AMUX of 150K.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1144,7 +1163,7 @@ int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
int32_t qpnp_adc_scale_therm_pu1(struct qpnp_vadc_chip *dev, int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
@ -1154,6 +1173,7 @@ int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
* gain and offset. Returns the temperature of the therm in degC.
* It uses a mapping table computed for a 100K pull-up.
* Pull-up2 is an internal pull-up on the AMUX of 100K.
* @dev: Structure device for qpnp vadc
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
@ -1161,17 +1181,22 @@ int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t qpnp_adc_scale_therm_pu2(int32_t adc_code,
int32_t qpnp_adc_scale_therm_pu2(struct qpnp_vadc_chip *dev, int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
/**
* qpnp_vadc_is_ready() - Clients can use this API to check if the
* device is ready to use.
* @result: 0 on success and -EPROBE_DEFER when probe for the device
* has not occured.
* qpnp_get_vadc() - Clients need to register with the vadc using the
* corresponding device instance it wants to read the channels
* from. Read the bindings document on how to pass the phandle
* for the corresponding vadc driver to register with.
* @dev: Clients device structure
* @name: Corresponding client's DT parser name. Read the DT bindings
* document on how to register with the vadc
* @struct qpnp_vadc_chip * - On success returns the vadc device structure
* pointer that needs to be used during an ADC request.
*/
int32_t qpnp_vadc_is_ready(void);
struct qpnp_vadc_chip *qpnp_get_vadc(struct device *dev, const char *name);
/**
* qpnp_adc_tm_scaler() - Performs reverse calibration.
* @config: Thermal monitoring configuration.
@ -1187,17 +1212,20 @@ static inline int32_t qpnp_adc_tm_scaler(struct qpnp_adc_tm_config *tm_config,
/**
* qpnp_get_vadc_gain_and_offset() - Obtains the VADC gain and offset
* for absolute and ratiometric calibration.
* @dev: Structure device for qpnp vadc
* @param: The result in which the ADC offset and gain values are stored.
* @type: The calibration type whether client needs the absolute or
* ratiometric gain and offset values.
*/
int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_linear_graph *param,
int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_chip *dev,
struct qpnp_vadc_linear_graph *param,
enum qpnp_adc_calib_type calib_type);
/**
* qpnp_adc_scale_millidegc_pmic_voltage_thr() - Performs reverse calibration
* on the low/high temperature threshold values passed by the
* client. The function coverts milldegC to voltage threshold
* and accounts for the corresponding channels scaling as (2mV/K).
* @dev: Structure device for qpnp vadc
* @param: The input parameters that contain the low/high temperature
* values.
* @low_threshold: The low threshold value that needs to be updated with
@ -1205,7 +1233,7 @@ int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_linear_graph *param,
* @high_threshold: The low threshold value that needs to be updated with
* the above calibrated voltage value.
*/
int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold);
/**
@ -1213,6 +1241,7 @@ int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
* temperature threshold values passed by the client.
* The function maps the temperature to voltage and applies
* ratiometric calibration on the voltage values.
* @dev: Structure device for qpnp vadc
* @param: The input parameters that contain the low/high temperature
* values.
* @low_threshold: The low threshold value that needs to be updated with
@ -1220,28 +1249,34 @@ int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
* @high_threshold: The low threshold value that needs to be updated with
* the above calibrated voltage value.
*/
int32_t qpnp_adc_btm_scaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_btm_scaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold);
/**
* qpnp_adc_tm_scale_therm_voltage_pu2() - Performs reverse calibration
* and convert given temperature to voltage on supported
* thermistor channels using 100k pull-up.
* @dev: Structure device for qpnp vadc
* @param: The input temperature values.
*/
int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_adc_tm_config *param);
int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_config *param);
/**
* qpnp_adc_tm_scale_therm_voltage_pu2() - Performs reverse calibration
* and converts the given ADC code to temperature for
* thermistor channels using 100k pull-up.
* @dev: Structure device for qpnp vadc
* @reg: The input ADC code.
* @result: The physical measurement temperature on the thermistor.
*/
int32_t qpnp_adc_tm_scale_voltage_therm_pu2(uint32_t reg, int64_t *result);
int32_t qpnp_adc_tm_scale_voltage_therm_pu2(struct qpnp_vadc_chip *dev,
uint32_t reg, int64_t *result);
/**
* qpnp_adc_usb_scaler() - Performs reverse calibration on the low/high
* voltage threshold values passed by the client.
* The function applies ratiometric calibration on the
* voltage values.
* @dev: Structure device for qpnp vadc
* @param: The input parameters that contain the low/high voltage
* threshold values.
* @low_threshold: The low threshold value that needs to be updated with
@ -1249,13 +1284,15 @@ int32_t qpnp_adc_tm_scale_voltage_therm_pu2(uint32_t reg, int64_t *result);
* @high_threshold: The low threshold value that needs to be updated with
* the above calibrated voltage value.
*/
int32_t qpnp_adc_usb_scaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_usb_scaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold);
/**
* qpnp_adc_vbatt_rscaler() - Performs reverse calibration on the low/high
* voltage threshold values passed by the client.
* The function applies ratiometric calibration on the
* voltage values.
* @dev: Structure device for qpnp vadc
* @param: The input parameters that contain the low/high voltage
* threshold values.
* @low_threshold: The low threshold value that needs to be updated with
@ -1263,7 +1300,8 @@ int32_t qpnp_adc_usb_scaler(struct qpnp_adc_tm_btm_param *param,
* @high_threshold: The low threshold value that needs to be updated with
* the above calibrated voltage value.
*/
int32_t qpnp_adc_vbatt_rscaler(struct qpnp_adc_tm_btm_param *param,
int32_t qpnp_adc_vbatt_rscaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold);
/**
* qpnp_vadc_iadc_sync_request() - Performs Voltage ADC read and
@ -1271,107 +1309,127 @@ int32_t qpnp_adc_vbatt_rscaler(struct qpnp_adc_tm_btm_param *param,
* voltage and current request the VADC peripheral is
* prepared for conversion and the IADC sync conversion
* is done from the IADC peripheral.
* @dev: Structure device for qpnp vadc
* @channel: Input channel to perform the voltage ADC read.
*/
int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel);
int32_t qpnp_vadc_iadc_sync_request(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_channels channel);
/**
* qpnp_vadc_iadc_sync_complete_request() - Reads the ADC result and
* unlocks the peripheral.
* @dev: Structure device for qpnp vadc
* @result: Structure pointer of type adc_chan_result
* in which the ADC read results are stored.
*/
int32_t qpnp_vadc_iadc_sync_complete_request(
int32_t qpnp_vadc_iadc_sync_complete_request(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_channels channel, struct qpnp_vadc_result *result);
/**
* qpnp_vadc_sns_comp_result() - Compensate vbatt readings based on temperature
* @dev: Structure device for qpnp vadc
* @result: Voltage in uV that needs compensation.
*/
int32_t qpnp_vbat_sns_comp_result(int64_t *result);
int32_t qpnp_vbat_sns_comp_result(struct qpnp_vadc_chip *dev,
int64_t *result);
#else
static inline int32_t qpnp_vadc_read(uint32_t channel,
static inline int32_t qpnp_vadc_read(struct qpnp_vadc_chip *dev,
uint32_t channel,
struct qpnp_vadc_result *result)
{ return -ENXIO; }
static inline int32_t qpnp_vadc_conv_seq_request(
static inline int32_t qpnp_vadc_conv_seq_request(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_trigger trigger_channel,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_default(int32_t adc_code,
static inline int32_t qpnp_adc_scale_default(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_pmic_therm(int32_t adc_code,
static inline int32_t qpnp_adc_scale_pmic_therm(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_batt_therm(int32_t adc_code,
static inline int32_t qpnp_adc_scale_batt_therm(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_qrd_batt_therm(int32_t adc_code,
static inline int32_t qpnp_adc_scale_qrd_batt_therm(
struct qpnp_vadc_chip *vadc, int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt);
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_batt_id(int32_t adc_code,
static inline int32_t qpnp_adc_scale_batt_id(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_tdkntcg_therm(int32_t adc_code,
static inline int32_t qpnp_adc_tdkntcg_therm(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_therm_pu1(int32_t adc_code,
static inline int32_t qpnp_adc_scale_therm_pu1(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_therm_pu2(int32_t adc_code,
static inline int32_t qpnp_adc_scale_therm_pu2(struct qpnp_vadc_chip *vadc,
int32_t adc_code,
const struct qpnp_adc_properties *adc_prop,
const struct qpnp_vadc_chan_properties *chan_prop,
struct qpnp_vadc_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t qpnp_vadc_is_ready(void)
{ return -ENXIO; }
static inline int32_t qpnp_get_vadc_gain_and_offset(
static inline struct qpnp_vadc_chip *qpnp_get_vadc(struct device *dev,
const char *name)
{ return ERR_PTR(-ENXIO); }
static inline int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_chip *dev,
struct qpnp_vadc_linear_graph *param,
enum qpnp_adc_calib_type calib_type)
{ return -ENXIO; }
static inline int32_t qpnp_adc_usb_scaler(
static inline int32_t qpnp_adc_usb_scaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{ return -ENXIO; }
static inline int32_t qpnp_adc_vbatt_rscaler(
static inline int32_t qpnp_adc_vbatt_rscaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{ return -ENXIO; }
static inline int32_t qpnp_adc_btm_scaler(
static inline int32_t qpnp_adc_btm_scaler(struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{ return -ENXIO; }
static inline int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(
struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_btm_param *param,
uint32_t *low_threshold, uint32_t *high_threshold)
{ return -ENXIO; }
static inline int32_t qpnp_adc_tm_scale_therm_voltage_pu2(
struct qpnp_vadc_chip *dev,
struct qpnp_adc_tm_config *param)
{ return -ENXIO; }
static inline int32_t qpnp_adc_tm_scale_voltage_therm_pu2(
struct qpnp_vadc_chip *dev,
uint32_t reg, int64_t *result)
{ return -ENXIO; }
static inline int32_t qpnp_vadc_iadc_sync_request(
static inline int32_t qpnp_vadc_iadc_sync_request(struct qpnp_vadc_chip *dev,
enum qpnp_vadc_channels channel)
{ return -ENXIO; }
static inline int32_t qpnp_vadc_iadc_sync_complete_request(
struct qpnp_vadc_chip *dev,
enum qpnp_vadc_channels channel,
struct qpnp_vadc_result *result)
{ return -ENXIO; }
static inline int32_t qpnp_vbat_sns_comp_result(int64_t *result)
static inline int32_t qpnp_vbat_sns_comp_result(struct qpnp_vadc_chip *dev,
int64_t *result)
{ return -ENXIO; }
#endif