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qcom: msm-pm: Partial goods support for sleep status driver 

On certains devices, some of the CPUs within the apps subsystem are not
functional and might be removed from the CPU possible map. To handle this
dynamic list of CPUs, sleep driver shouldn't make any assumptions with
regards to the logical mapping of the CPU.

Remove the assumption on how physical CPUs are mapped onto logical CPUs and
populate create a reference of sleep status driver in the corresponding
CPU phandles. When the sleep status driver is probed, it would probe
iterating the list of possble CPUs.

CRs-fixed: 756327
Change-Id: I3afe8c9afd26000ab08f0e0c2703f2ce9e15f374
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
This commit is contained in:
Mahesh Sivasubramanian 2015-01-14 14:23:50 -07:00 committed by Srinivas Rao L
parent 85d129267a
commit 04c58e4455
22 changed files with 316 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt
View File

@ -6,19 +6,44 @@ sleep status device before CPU_DEAD notifications are sent out. Some hardware
devices require that the offlined core is power collapsed before turning off
the resources that are used by the offlined core.
The required properties of sleep status device are:
The required properties of core sleep status node are:
- compatible: qcom,cpu-sleep-status
- reg: physical address of the sleep status register for Core 0
- qcom,cpu-alias-addr - On MSM chipset, the each cores registers are at a
fixed offset each other.
The required properties of sleep status node are:
- reg: physical address of the sleep status register for the cpus
- qcom,cpu-sleep-status-mask - The bit mask within the status register that
indicates the Core's sleep state.
Example:
qcom,cpu-sleep-status@f9088008 {
qcom,cpu-sleep-status {
compatible = "qcom,cpu-sleep-status";
reg = <0xf9088008 0x4>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
qcom,sleep-status = <&cpu0_slp_sts>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
qcom,sleep-status = <&cpu1_slp_sts>;
};
};
cpu0_slp_sts: cpu-sleep-status@9981058 {
reg = <0x9981058 0x100>;
qcom,sleep-status-mask = <0xc00000>;
};
cpu1_slp_sts: cpu-sleep-status@9991058 {
reg = <0x9991058 0x100>;
qcom,sleep-status-mask = <0xc00000>;
}

5
arch/arm/boot/dts/qcom/apq8084-pm.dtsi
View File

@ -446,11 +446,8 @@
<54 585 0 800000>;
};
qcom,cpu-sleep-status@f9088008{
qcom,cpu-sleep-status {
compatible = "qcom,cpu-sleep-status";
reg = <0xf9088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
};

24
arch/arm/boot/dts/qcom/apq8084.dtsi
View File

@ -36,24 +36,28 @@
device_type = "cpu";
compatible = "qcom,krait";
reg = <0x0>;
qcom,sleep-status = <&cpu0_slp_sts>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <0x1>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <0x2>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <0x3>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
};
@ -5582,6 +5586,26 @@
<0xFE0C9010 0x4>;
reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
};
cpu0_slp_sts: cpu-sleep-status@f9088008 {
reg = <0xf9088008 0x100>;
qcom,sleep-status-mask = <0x80000>;
};
cpu1_slp_sts: cpu-sleep-status@f9098008 {
reg = <0xf9098008 0x100>;
qcom,sleep-status-mask = <0x80000>;
};
cpu2_slp_sts: cpu-sleep-status@f90a8008 {
reg = <0xf90a8008 0x100>;
qcom,sleep-status-mask = <0x80000>;
};
cpu3_slp_sts: cpu-sleep-status@f90b8008 {
reg = <0xf90b8008 0x100>;
qcom,sleep-status-mask = <0x80000>;
};
};
&gdsc_venus {

5
arch/arm/boot/dts/qcom/msm8909-pm8909-pm.dtsi
View File

@ -387,11 +387,8 @@
qcom,tz-flushes-cache;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
qcom,rpm-log@29dc00 {

5
arch/arm/boot/dts/qcom/msm8909-pm8916-pm.dtsi
View File

@ -394,11 +394,8 @@
qcom,synced-clocks;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
qcom,rpm-log@29dc00 {

24
arch/arm/boot/dts/qcom/msm8909.dtsi
View File

@ -57,24 +57,28 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
qcom,sleep-status = <&cpu0_slp_sts>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
};
@ -1772,6 +1776,26 @@
"iface_clk", "bus_clk";
qcom,ce-opp-freq = <100000000>;
};
cpu0_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu1_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu2_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu3_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
};
&gdsc_venus {

5
arch/arm/boot/dts/qcom/msm8916-pm.dtsi
View File

@ -320,11 +320,8 @@
qcom,synced-clocks;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

24
arch/arm/boot/dts/qcom/msm8916.dtsi
View File

@ -63,6 +63,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc0>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu0_slp_sts>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -77,6 +78,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc1>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@2 {
@ -86,6 +88,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc2>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@3 {
@ -95,6 +98,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc3>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
};
@ -1901,6 +1905,26 @@
"iface_clk", "bus_clk";
qcom,ce-opp-freq = <100000000>;
};
cpu0_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
com,sleep-status-mask= <0x40000>;
};
cpu1_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
com,sleep-status-mask= <0x40000>;
};
cpu2_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
com,sleep-status-mask= <0x40000>;
};
cpu3_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
com,sleep-status-mask= <0x40000>;
};
};
&gdsc_venus {

24
arch/arm/boot/dts/qcom/msm8936-cpu.dtsi
View File

@ -22,6 +22,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc0>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu0_slp_sts>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -36,6 +37,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc1>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@2 {
@ -45,6 +47,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc2>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@3 {
@ -54,6 +57,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc3>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
};
};
@ -84,4 +88,24 @@
compatible = "qcom,arm-cortex-acc";
reg = <0x0b0b8000 0x1000>;
};
cpu0_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu1_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu2_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu3_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
};

7
arch/arm/boot/dts/qcom/msm8936-pm.dtsi
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -361,11 +361,8 @@
<&clock_cpu clk_a53ssmux_cci>;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

48
arch/arm/boot/dts/qcom/msm8939-cpu.dtsi
View File

@ -53,6 +53,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc0>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu0_slp_sts>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -67,6 +68,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc1>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@102 {
@ -76,6 +78,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc2>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@103 {
@ -85,6 +88,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc3>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
CPU4: cpu@0 {
@ -94,6 +98,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc4>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu4_slp_sts>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -108,6 +113,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc5>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu5_slp_sts>;
};
CPU6: cpu@2 {
@ -117,6 +123,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc6>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu6_slp_sts>;
};
CPU7: cpu@3 {
@ -126,6 +133,7 @@
enable-method = "qcom,arm-cortex-acc";
qcom,acc = <&acc7>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu7_slp_sts>;
};
};
};
@ -182,4 +190,44 @@
compatible = "qcom,arm-cortex-acc";
reg = <0x0b1b8000 0x1000>;
};
cpu0_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu1_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu2_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu3_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu4_slp_sts: cpu-sleep-status@b188008 {
reg = <0xb188008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu5_slp_sts: cpu-sleep-status@b198008 {
reg = <0xb198008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu6_slp_sts: cpu-sleep-status@b1a8008 {
reg = <0xb1a8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu7_slp_sts: cpu-sleep-status@b1b8008 {
reg = <0xb1b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
};

11
arch/arm/boot/dts/qcom/msm8939-pm.dtsi
View File

@ -576,17 +576,8 @@
qcom,tz-flushes-cache;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>,
<0xb098008 0x100>,
<0xb0a8008 0x100>,
<0xb0b8008 0x100>,
<0xb188008 0x100>,
<0xb198008 0x100>,
<0xb1a8008 0x100>,
<0xb1b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

11
arch/arm/boot/dts/qcom/msm8939-v3.0-pm.dtsi
View File

@ -580,17 +580,8 @@
qcom,tz-flushes-cache;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>,
<0xb098008 0x100>,
<0xb0a8008 0x100>,
<0xb0b8008 0x100>,
<0xb188008 0x100>,
<0xb198008 0x100>,
<0xb1a8008 0x100>,
<0xb1b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

11
arch/arm/boot/dts/qcom/msm8952-pm.dtsi
View File

@ -397,17 +397,8 @@
<0xff 88>;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>,
<0xb098008 0x100>,
<0xb0a8008 0x100>,
<0xb0b8008 0x100>,
<0xb188008 0x100>,
<0xb198008 0x100>,
<0xb1a8008 0x100>,
<0xb1b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

2
arch/arm/boot/dts/qcom/msm8956.dtsi
View File

@ -127,7 +127,7 @@
#include "msm8976-bus.dtsi"
#include "msm8976-jtag.dtsi"
#include "msm8976-coresight.dtsi"
#include "msm8956-pm.dtsi"
#include "msm8976-pm.dtsi"
#include "msm8976-gpu.dtsi"
#include "msm8976-cpu.dtsi"
#include "msm8976-mdss.dtsi"

51
arch/arm/boot/dts/qcom/msm8976-cpu.dtsi
View File

@ -61,6 +61,7 @@
efficiency = <1024>;
qcom,acc = <&acc0>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu0_slp_sts>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -76,6 +77,7 @@
efficiency = <1024>;
qcom,acc = <&acc1>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu1_slp_sts>;
};
CPU2: cpu@2 {
@ -86,6 +88,7 @@
efficiency = <1024>;
qcom,acc = <&acc2>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu2_slp_sts>;
};
CPU3: cpu@3 {
@ -96,6 +99,7 @@
efficiency = <1024>;
qcom,acc = <&acc3>;
next-level-cache = <&L2_0>;
qcom,sleep-status = <&cpu3_slp_sts>;
};
CPU4: cpu@100 {
@ -107,12 +111,13 @@
qcom,acc = <&acc4>;
qcom,ldo = <&ldo4>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu4_slp_sts>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
power-domain = <&l2ccc_1>;
};
};
};
CPU5: cpu@101 {
device_type = "cpu";
@ -123,6 +128,7 @@
qcom,acc = <&acc5>;
qcom,ldo = <&ldo5>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu5_slp_sts>;
};
CPU6: cpu@102 {
@ -134,6 +140,7 @@
qcom,acc = <&acc6>;
qcom,ldo = <&ldo6>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu6_slp_sts>;
};
CPU7: cpu@103 {
@ -145,6 +152,7 @@
qcom,acc = <&acc7>;
qcom,ldo = <&ldo7>;
next-level-cache = <&L2_1>;
qcom,sleep-status = <&cpu7_slp_sts>;
};
};
};
@ -227,4 +235,45 @@
reg = <0xb0b6000 0x40>;
qcom,ldo-vref-ret = <0x9>;
};
cpu0_slp_sts: cpu-sleep-status@b188008 {
reg = <0xb188008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu1_slp_sts: cpu-sleep-status@b198008 {
reg = <0xb198008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu2_slp_sts: cpu-sleep-status@b1a8008 {
reg = <0xb1a8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu3_slp_sts: cpu-sleep-status@b1b8008 {
reg = <0xb1b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu4_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu5_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu6_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
cpu7_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
};

11
arch/arm/boot/dts/qcom/msm8976-pm.dtsi
View File

@ -453,17 +453,8 @@
<56 35>;
};
qcom,cpu-sleep-status@b088008{
qcom,cpu-sleep-status{
compatible = "qcom,cpu-sleep-status";
reg = <0xb188008 0x100>,
<0xb198008 0x100>,
<0xb1a8008 0x100>,
<0xb1b8008 0x100>,
<0xb088008 0x100>,
<0xb098008 0x100>,
<0xb0a8008 0x100>,
<0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x40000>;
};
qcom,rpm-log@29dc00 {

7
arch/arm/boot/dts/qcom/msm8994-v1-pm.dtsi
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -557,11 +557,8 @@
};
qcom,cpu-sleep-status@f908b008{
qcom,cpu-sleep-status {
compatible = "qcom,cpu-sleep-status";
reg = <0xf908b008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
qcom,rpm-log@fc000000 {

5
arch/arm/boot/dts/qcom/msm8994-v2-pm.dtsi
View File

@ -649,11 +649,8 @@
};
qcom,cpu-sleep-status@f908b008{
qcom,cpu-sleep-status {
compatible = "qcom,cpu-sleep-status";
reg = <0xf908b008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
qcom,rpm-log@fc000000 {

48
arch/arm/boot/dts/qcom/msm8994.dtsi
View File

@ -82,6 +82,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc0>;
qcom,ldo = <&ldo0>;
qcom,sleep-status = <&cpu0_slp_sts>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@ -109,6 +110,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc1>;
qcom,ldo = <&ldo1>;
qcom,sleep-status = <&cpu1_slp_sts>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
@ -127,6 +129,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc2>;
qcom,ldo = <&ldo2>;
qcom,sleep-status = <&cpu2_slp_sts>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
@ -145,6 +148,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc3>;
qcom,ldo = <&ldo3>;
qcom,sleep-status = <&cpu3_slp_sts>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
@ -163,6 +167,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc4>;
qcom,ldo = <&ldo4>;
qcom,sleep-status = <&cpu4_slp_sts>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@ -196,6 +201,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc5>;
qcom,ldo = <&ldo5>;
qcom,sleep-status = <&cpu5_slp_sts>;
next-level-cache = <&L2_1>;
L1_itlb_101: l1-itlb {
qcom,dump-size = <0x400>;
@ -220,6 +226,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc6>;
qcom,ldo = <&ldo6>;
qcom,sleep-status = <&cpu6_slp_sts>;
next-level-cache = <&L2_1>;
L1_itlb_102: l1-itlb {
qcom,dump-size = <0x400>;
@ -244,6 +251,7 @@
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc7>;
qcom,ldo = <&ldo7>;
qcom,sleep-status = <&cpu7_slp_sts>;
next-level-cache = <&L2_1>;
L1_itlb_103: l1-itlb {
qcom,dump-size = <0x400>;
@ -3515,6 +3523,46 @@
};
};
cpu0_slp_sts: cpu-sleep-status@f908b008 {
reg = <0xf908b008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu1_slp_sts: cpu-sleep-status@f909b008 {
reg = <0xf909b008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu2_slp_sts: cpu-sleep-status@f90ab008 {
reg = <0xf90ab008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu3_slp_sts: cpu-sleep-status@f90bb008 {
reg = <0xf90bb008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu4_slp_sts: cpu-sleep-status@f90cb008 {
reg = <0xf90cb008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu5_slp_sts: cpu-sleep-status@f90db008 {
reg = <0xf90db008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu6_slp_sts: cpu-sleep-status@f90eb008 {
reg = <0xf90eb008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu7_slp_sts: cpu-sleep-status@f90fb008 {
reg = <0xf90fb008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
};
&gdsc_usb30 {

77
drivers/power/qcom/msm-pm.c
View File

@ -24,6 +24,7 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/msm-bus.h>
#include <linux/uaccess.h>
#include <linux/dma-mapping.h>
@ -551,11 +552,10 @@ snoc_cl_probe_done:
static int msm_cpu_status_probe(struct platform_device *pdev)
{
struct msm_pm_sleep_status_data *pdata;
char *key;
u32 cpu;
int rc;
if (!pdev)
if (!pdev | !pdev->dev.of_node)
return -EFAULT;
msm_pm_slp_sts = devm_kzalloc(&pdev->dev,
@ -565,59 +565,34 @@ static int msm_cpu_status_probe(struct platform_device *pdev)
if (!msm_pm_slp_sts)
return -ENOMEM;
if (pdev->dev.of_node) {
struct resource *res;
u32 offset;
int rc;
u32 mask;
bool offset_available = true;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
for_each_possible_cpu(cpu) {
struct device_node *cpun, *node;
char *key;
cpun = of_get_cpu_node(cpu, NULL);
if (!cpun) {
__WARN();
continue;
}
node = of_parse_phandle(cpun, "qcom,sleep-status", 0);
if (!node)
return -ENODEV;
key = "qcom,cpu-alias-addr";
rc = of_property_read_u32(pdev->dev.of_node, key, &offset);
if (rc)
offset_available = false;
msm_pm_slp_sts[cpu].base_addr = of_iomap(node, 0);
if (!msm_pm_slp_sts[cpu].base_addr) {
pr_err("%s: Can't find base addr\n", __func__);
return -ENODEV;
}
key = "qcom,sleep-status-mask";
rc = of_property_read_u32(pdev->dev.of_node, key, &mask);
if (rc)
return -ENODEV;
for_each_possible_cpu(cpu) {
phys_addr_t base_c;
if (offset_available)
base_c = res->start + cpu * offset;
else {
res = platform_get_resource(pdev,
IORESOURCE_MEM, cpu);
if (!res)
return -ENODEV;
base_c = res->start;
}
msm_pm_slp_sts[cpu].base_addr =
devm_ioremap(&pdev->dev, base_c,
resource_size(res));
msm_pm_slp_sts[cpu].mask = mask;
if (!msm_pm_slp_sts[cpu].base_addr)
return -ENOMEM;
}
} else {
pdata = pdev->dev.platform_data;
if (!pdev->dev.platform_data)
return -EINVAL;
for_each_possible_cpu(cpu) {
msm_pm_slp_sts[cpu].base_addr =
pdata->base_addr + cpu * pdata->cpu_offset;
msm_pm_slp_sts[cpu].mask = pdata->mask;
rc = of_property_read_u32(node, key, &msm_pm_slp_sts[cpu].mask);
if (rc) {
pr_err("%s: Can't find %s property\n", __func__, key);
iounmap(msm_pm_slp_sts[cpu].base_addr);
return rc;
}
}

1
include/soc/qcom/pm.h
View File

@ -59,7 +59,6 @@ struct msm_pm_time_params {
struct msm_pm_sleep_status_data {
void *base_addr;
uint32_t cpu_offset;
uint32_t mask;
};